static int da8xx_usb20_phy_power_on(struct phy *phy)
{
struct da8xx_usb_phy *d_phy = phy_get_drvdata(phy);
int ret;
ret = clk_prepare_enable(d_phy->usb20_clk);
if (ret)
return ret;
regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGPWRDN, 0);
return 0;
}
static unsigned long da8xx_usb0_clk48_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
unsigned int mask, val;
/* The parent clock rate must be one of the following */
mask = CFGCHIP2_REFFREQ_MASK;
switch (parent_rate) {
case 12000000:
val = CFGCHIP2_REFFREQ_12MHZ;
break;
case 13000000:
val = CFGCHIP2_REFFREQ_13MHZ;
break;
case 19200000:
val = CFGCHIP2_REFFREQ_19_2MHZ;
break;
case 20000000:
val = CFGCHIP2_REFFREQ_20MHZ;
break;
case 24000000:
val = CFGCHIP2_REFFREQ_24MHZ;
break;
case 26000000:
val = CFGCHIP2_REFFREQ_26MHZ;
break;
case 38400000:
val = CFGCHIP2_REFFREQ_38_4MHZ;
break;
case 40000000:
val = CFGCHIP2_REFFREQ_40MHZ;
break;
case 48000000:
val = CFGCHIP2_REFFREQ_48MHZ;
break;
default:
return 0;
}
regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
/* USB 2.0 PLL always supplies 48MHz */
return 48000000;
}
static int da8xx_usb20_phy_set_mode(struct phy *phy, enum phy_mode mode)
{
struct da8xx_usb_phy *d_phy = phy_get_drvdata(phy);
u32 val;
switch (mode) {
case PHY_MODE_USB_HOST: /* Force VBUS valid, ID = 0 */
val = CFGCHIP2_OTGMODE_FORCE_HOST;
break;
case PHY_MODE_USB_DEVICE: /* Force VBUS valid, ID = 1 */
val = CFGCHIP2_OTGMODE_FORCE_DEVICE;
break;
case PHY_MODE_USB_OTG: /* Don't override the VBUS/ID comparators */
val = CFGCHIP2_OTGMODE_NO_OVERRIDE;
break;
default:
return -EINVAL;
}
regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGMODE_MASK,
val);
return 0;
}
gate->hw.init = &init;
gate->regmap = regmap;
gate->reg = info->cfgchip;
gate->mask = info->bit;
ret = devm_clk_hw_register(dev, &gate->hw);
if (ret < 0)
return ERR_PTR(ret);
return gate;
}
static const struct da8xx_cfgchip_gate_clk_info da8xx_tbclksync_info __initconst = {
.name = "ehrpwm_tbclk",
.cfgchip = CFGCHIP(1),
.bit = CFGCHIP1_TBCLKSYNC,
};
static int __init da8xx_cfgchip_register_tbclk(struct device *dev,
struct regmap *regmap)
{
struct da8xx_cfgchip_gate_clk *gate;
gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_tbclksync_info,
regmap);
if (IS_ERR(gate))
return PTR_ERR(gate);
clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.0");
clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.1");
#include <linux/mfd/da8xx-cfgchip.h>
#include <linux/mfd/syscon.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/types.h>
#include "pll.h"
#define OCSEL_OCSRC_OSCIN 0x14
#define OCSEL_OCSRC_PLL0_SYSCLK(n) (0x16 + (n))
#define OCSEL_OCSRC_PLL1_OBSCLK 0x1e
#define OCSEL_OCSRC_PLL1_SYSCLK(n) (0x16 + (n))
static const struct davinci_pll_clk_info da850_pll0_info = {
.name = "pll0",
.unlock_reg = CFGCHIP(0),
.unlock_mask = CFGCHIP0_PLL_MASTER_LOCK,
.pllm_mask = GENMASK(4, 0),
.pllm_min = 4,
.pllm_max = 32,
.pllout_min_rate = 300000000,
.pllout_max_rate = 600000000,
.flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV |
PLL_HAS_EXTCLKSRC,
};
/*
* NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
* meaning that we could change the divider as long as we keep the correct
* ratio between all of the clocks, but we don't support that because there is
* currently not a need for it.
