static void lowpower_earlyinit(void) { unsigned int reg_val; ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD, BIT_DCDC_TOP_CLKF_EN|BIT_DCDC_TOP_OSC_EN); ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0, BIT_SLP_IO_EN); ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1, BIT_SLP_LDO_PD_EN); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0, BIT_LDO_XTL_EN); CHIP_REG_SET(REG_PMU_APB_CGM_AP_EN,0x1FFF81); reg_val = ANA_REG_GET(ANA_REG_GLB_DCDC_SLP_CTRL0); reg_val &= ~BITS_DCDC_CORE_CTL_DS_SW(7); reg_val |= BITS_DCDC_CORE_CTL_DS_SW(4); ANA_REG_SET(ANA_REG_GLB_DCDC_SLP_CTRL0,reg_val); ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM,0x0908); /*plls wait, xtl0/1 wait, xtlbuf0/1 wait time*/ if (ANA_GET_CHIP_ID() != 0x2711a000) { CHIP_REG_SET(REG_AON_CLK_FM_CFG, //BIT_CLK_FM_PAD_SEL | //BIT_CLK_FM_SEL | 0 ); CHIP_REG_SET(REG_AON_APB_GPS_26M_REF_SEL, //BIT_XTLBUF1_GPS_SEL | BIT_XTLBUF0_GPS_SEL | //BIT_GPS_26M_REF_SEL | 0 ); } }
static int Zip_Dec_Wait_Pool(ZIPDEC_INT_TYPE num) { uint32_t int_sts; while (1) { int_sts=CHIP_REG_GET(ZIPDEC_INT_RAW); if(int_sts&(0x1<<ZIPDEC_TIMEOUT_INT)) { ZipDec_Set_Timeout(zipdec_param.timeout); CHIP_REG_SET (ZIPDEC_INT_CLR ,0xFF );// ZIPDEC_TIMEOUT_CLR); //printk("zip dec timeout: 0x%x \n", int_sts); //printk("ZIPDEC_STS0:0x%x\n",CHIP_REG_GET(ZIPDEC_STS0)); //printk("ZIPDEC_STS1:0x%x\n",CHIP_REG_GET(ZIPDEC_STS1)); //printk("ZIPDEC_STS2:0x%x\n",CHIP_REG_GET(ZIPDEC_STS2)); //printk("ZIPDEC_STS3:0x%x\n",CHIP_REG_GET(ZIPDEC_STS3)); //printk("ZIPDEC_STS4:0x%x\n",CHIP_REG_GET(ZIPDEC_STS4)); return -1; } if(int_sts&0x1e) { CHIP_REG_SET (ZIPDEC_INT_CLR , 0xFF ); //printk("zip dec err: 0x%x \n", int_sts); //printk("ZIPDEC_STS0:0x%x\n",CHIP_REG_GET(ZIPDEC_STS0)); //printk("ZIPDEC_STS1:0x%x\n",CHIP_REG_GET(ZIPDEC_STS1)); //printk("ZIPDEC_STS2:0x%x\n",CHIP_REG_GET(ZIPDEC_STS2)); //printk("ZIPDEC_STS3:0x%x\n",CHIP_REG_GET(ZIPDEC_STS3)); //printk("ZIPDEC_STS4:0x%x\n",CHIP_REG_GET(ZIPDEC_STS4)); return -1; } if(int_sts&(0x1<<num)) { CHIP_REG_SET (ZIPDEC_INT_CLR , 0xFF );//ZIPDEC_DONE_CLR); break; } } return 0; }
PUBLIC BOOLEAN CHIP_PHY_IsWDGRstByMCU (uint32 flag) { // Copy the value of HW_RST register to the register specific to reset mode CHIP_REG_SET (CHIP_PHY_GetRstModeAddr (), (CHIP_PHY_GetHWFlag () & 0xFFFF)); if ((CHIP_PHY_GetHWFlag () & 0xFFFF) == (flag & 0xFFFF)) { return SCI_FALSE; } else { return SCI_TRUE; } }
void init_ldo_sleep_gr(void) { unsigned int reg_val; #if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723) ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE, BITS_PWR_WR_PROT_VALUE(0x5e6f) | 0 ); while((ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT) == BIT_PWR_WR_PROT); ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD, BIT_LDO_EMM_PD | //BIT_DCDC_TOPCLK6M_PD | //BIT_DCDC_RF_PD | //BIT_DCDC_GEN_PD | //BIT_DCDC_MEM_PD | //BIT_DCDC_ARM_PD | //BIT_DCDC_CORE_PD | //BIT_LDO_RF0_PD | //BIT_LDO_EMMCCORE_PD | //BIT_LDO_GEN1_PD | //BIT_LDO_DCXO_PD | //BIT_LDO_GEN0_PD | //BIT_LDO_VDD25_PD | //BIT_LDO_VDD28_PD | //BIT_LDO_VDD18_PD | //BIT_BG_PD | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE, BITS_PWR_WR_PROT_VALUE(0x0000) | 0 ); ANA_REG_SET(ANA_REG_GLB_LDO_PD_CTRL, BIT_LDO_LPREF_PD_SW | BIT_DCDC_WPA_PD | BIT_DCDC_CON_PD | BIT_LDO_WIFIPA_PD | BIT_LDO_SDCORE_PD | BIT_LDO_USB_PD | BIT_LDO_CAMMOT_PD | BIT_LDO_CAMIO_PD | BIT_LDO_CAMD_PD | BIT_LDO_CAMA_PD | BIT_LDO_SIM2_PD | //BIT_LDO_SIM1_PD | //BIT_LDO_SIM0_PD | //BIT_LDO_SDIO_PD | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0, BIT_SLP_IO_EN | BIT_SLP_DCDCRF_PD_EN | BIT_SLP_DCDCCON_PD_EN | //BIT_SLP_DCDCGEN_PD_EN | BIT_SLP_DCDCWPA_PD_EN | BIT_SLP_DCDCARM_PD_EN | BIT_SLP_LDOVDD25_PD_EN | BIT_SLP_LDORF0_PD_EN | BIT_SLP_LDOEMMCCORE_PD_EN | BIT_SLP_LDOGEN0_PD_EN | BIT_SLP_LDODCXO_PD_EN | //BIT_SLP_LDOGEN1_PD_EN | BIT_SLP_LDOWIFIPA_PD_EN | //BIT_SLP_LDOVDD28_PD_EN | //BIT_SLP_LDOVDD18_PD_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1, BIT_SLP_LDO_PD_EN | BIT_SLP_LDOLPREF_PD_EN | BIT_SLP_LDOSDCORE_PD_EN | BIT_SLP_LDOUSB_PD_EN | BIT_SLP_LDOCAMMOT_PD_EN | BIT_SLP_LDOCAMIO_PD_EN | BIT_SLP_LDOCAMD_PD_EN | BIT_SLP_LDOCAMA_PD_EN | BIT_SLP_LDOSIM2_PD_EN | //BIT_SLP_LDOSIM1_PD_EN | //BIT_SLP_LDOSIM0_PD_EN | BIT_SLP_LDOSDIO_PD_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2, //BIT_SLP_DCDCRF_LP_EN | //BIT_SLP_DCDCCON_LP_EN | //BIT_SLP_DCDCCORE_LP_EN | //BIT_SLP_DCDCMEM_LP_EN | //BIT_SLP_DCDCARM_LP_EN | //BIT_SLP_DCDCGEN_LP_EN | //BIT_SLP_DCDCWPA_LP_EN | //BIT_SLP_LDORF0_LP_EN | //BIT_SLP_LDOEMMCCORE_LP_EN | //BIT_SLP_LDOGEN0_LP_EN | //BIT_SLP_LDODCXO_LP_EN | //BIT_SLP_LDOGEN1_LP_EN | //BIT_SLP_LDOWIFIPA_LP_EN | //BIT_SLP_LDOVDD28_LP_EN | //BIT_SLP_LDOVDD18_LP_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3, //BIT_SLP_BG_LP_EN | //BIT_LDOVDD25_LP_EN_SW | //BIT_LDOSDCORE_LP_EN_SW | //BIT_LDOUSB_LP_EN_SW | //BIT_SLP_LDOVDD25_LP_EN | //BIT_SLP_LDOSDCORE_LP_EN | //BIT_SLP_LDOUSB_LP_EN | //BIT_SLP_LDOCAMMOT_LP_EN | //BIT_SLP_LDOCAMIO_LP_EN | //BIT_SLP_LDOCAMD_LP_EN | //BIT_SLP_LDOCAMA_LP_EN | //BIT_SLP_LDOSIM2_LP_EN | //BIT_SLP_LDOSIM1_LP_EN | //BIT_SLP_LDOSIM0_LP_EN | //BIT_SLP_LDOSDIO_LP_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL4, //BIT_LDOCAMIO_LP_EN_SW | //BIT_LDOCAMMOT_LP_EN_SW | //BIT_LDOCAMD_LP_EN_SW | //BIT_LDOCAMA_LP_EN_SW | //BIT_LDOSIM2_LP_EN_SW | //BIT_LDOSIM1_LP_EN_SW | //BIT_LDOSIM0_LP_EN_SW | //BIT_LDOSDIO_LP_EN_SW | //BIT_LDORF0_LP_EN_SW | //BIT_LDOEMMCCORE_LP_EN_SW | //BIT_LDOGEN0_LP_EN_SW | //BIT_LDODCXO_LP_EN_SW | //BIT_LDOGEN1_LP_EN_SW | //BIT_LDOWIFIPA_LP_EN_SW | //BIT_LDOVDD28_LP_EN_SW | //BIT_LDOVDD18_LP_EN_SW | 0 ); ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL, BIT_SLP_XTLBUF_PD_EN | BIT_XTL_EN | BITS_XTL_WAIT(0x32) | 0 ); /**************************************** * Following is CP LDO Sleep Control * ****************************************/ ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0, BIT_LDO_XTL_EN | //BIT_LDO_GEN0_EXT_XTL0_EN | //BIT_LDO_GEN0_XTL1_EN | BIT_LDO_GEN0_XTL0_EN | //BIT_LDO_GEN1_EXT_XTL0_EN | //BIT_LDO_GEN1_XTL1_EN | //BIT_LDO_GEN1_XTL0_EN | BIT_LDO_DCXO_EXT_XTL0_EN | BIT_LDO_DCXO_XTL1_EN | BIT_LDO_DCXO_XTL0_EN | //BIT_LDO_VDD18_EXT_XTL0_EN | //BIT_LDO_VDD18_XTL1_EN | //BIT_LDO_VDD18_XTL0_EN | //BIT_LDO_VDD28_EXT_XTL0_EN | //BIT_LDO_VDD28_XTL1_EN | //BIT_LDO_VDD28_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1, BIT_LDO_RF0_EXT_XTL0_EN | BIT_LDO_RF0_XTL1_EN | BIT_LDO_RF0_XTL0_EN | BIT_LDO_WIFIPA_EXT_XTL0_EN | BIT_LDO_WIFIPA_XTL1_EN | BIT_LDO_WIFIPA_XTL0_EN | //BIT_LDO_SIM2_EXT_XTL0_EN | //BIT_LDO_SIM2_XTL1_EN | //BIT_LDO_SIM2_XTL0_EN | BIT_LDO_SIM1_EXT_XTL0_EN | BIT_LDO_SIM1_XTL1_EN | BIT_LDO_SIM1_XTL0_EN | BIT_LDO_SIM0_EXT_XTL0_EN | BIT_LDO_SIM0_XTL1_EN | BIT_LDO_SIM0_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2, BIT_LDO_VDD25_EXT_XTL0_EN | BIT_LDO_VDD25_XTL1_EN | BIT_LDO_VDD25_XTL0_EN | BIT_DCDC_RF_EXT_XTL0_EN | BIT_DCDC_RF_XTL1_EN | BIT_DCDC_RF_XTL0_EN | BIT_XO_EXT_XTL0_EN | BIT_XO_XTL1_EN | BIT_XO_XTL0_EN | BIT_BG_EXT_XTL0_EN | BIT_BG_XTL1_EN | BIT_BG_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3, BIT_DCDC_CON_EXT_XTL0_EN | BIT_DCDC_CON_XTL1_EN | BIT_DCDC_CON_XTL0_EN | BIT_DCDC_WPA_EXT_XTL0_EN | BIT_DCDC_WPA_XTL1_EN | BIT_DCDC_WPA_XTL0_EN | BIT_DCDC_MEM_EXT_XTL0_EN | BIT_DCDC_MEM_XTL1_EN | BIT_DCDC_MEM_XTL0_EN | BIT_DCDC_GEN_EXT_XTL0_EN | BIT_DCDC_GEN_XTL1_EN | BIT_DCDC_GEN_XTL0_EN | BIT_DCDC_CORE_EXT_XTL0_EN | BIT_DCDC_CORE_XTL1_EN | BIT_DCDC_CORE_XTL0_EN | 0 ); #else ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, //BIT_LDO_AVDD18_PD_RTCCLR | BIT_DCDC_OTP_PD_RTCCLR | //BIT_DCDC_WRF_PD_RTCCLR | BIT_DCDC_GEN_PD_RTCCLR | BIT_DCDC_MEM_PD_RTCCLR | BIT_DCDC_ARM_PD_RTCCLR | BIT_DCDC_CORE_PD_RTCCLR| BIT_LDO_EMMCCORE_PD_RTCCLR | BIT_LDO_EMMCIO_PD_RTCCLR | BIT_LDO_RF2_PD_RTCCLR | //BIT_LDO_RF1_PD_RTCCLR | BIT_LDO_RF0_PD_RTCCLR | BIT_LDO_VDD25_PD_RTCCLR | BIT_LDO_VDD28_PD_RTCCLR | BIT_LDO_VDD18_PD_RTCCLR | BIT_BG_PD_RTCCLR | 0 ); ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT_LDO_AVDD18_PD_RTCSET | //BIT_DCDC_OTP_PD_RTCSET | BIT_DCDC_WRF_PD_RTCSET | //BIT_DCDC_GEN_PD_RTCSET | //BIT_DCDC_MEM_PD_RTCSET | //BIT_DCDC_ARM_PD_RTCSET | //BIT_DCDC_CORE_PD_RTCSET| //BIT_LDO_EMMCCORE_PD_RTCSET | //BIT_LDO_EMMCIO_PD_RTCSET | //BIT_LDO_RF2_PD_RTCSET | BIT_LDO_RF1_PD_RTCSET | //BIT_LDO_RF0_PD_RTCSET | //BIT_LDO_VDD25_PD_RTCSET | //BIT_LDO_VDD28_PD_RTCSET | //BIT_LDO_VDD18_PD_RTCSET | //BIT_BG_PD_RTCSET | 0 ); /********************************************** * Following is AP LDO A DIE Sleep Control * *********************************************/ ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0, BIT_SLP_IO_EN | BIT_SLP_DCDC_OTP_PD_EN | //BIT_SLP_DCDCGEN_PD_EN | BIT_SLP_DCDCWPA_PD_EN | //BIT_SLP_DCDCWRF_PD_EN | BIT_SLP_DCDCARM_PD_EN | BIT_SLP_LDOEMMCCORE_PD_EN | BIT_SLP_LDOEMMCIO_PD_EN | BIT_SLP_LDORF2_PD_EN | //BIT_SLP_LDORF1_PD_EN | BIT_SLP_LDORF0_PD_EN | BIT_SLP_LDOVDD25_PD_EN | //BIT_SLP_LDOVDD28_PD_EN | //BIT_SLP_LDOVDD18_PD_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1, BIT_SLP_LDO_PD_EN | BIT_SLP_LDOLPREF_PD_EN | BIT_SLP_LDOCLSG_PD_EN | BIT_SLP_LDOUSB_PD_EN | BIT_SLP_LDOCAMMOT_PD_EN | BIT_SLP_LDOCAMIO_PD_EN | BIT_SLP_LDOCAMD_PD_EN | BIT_SLP_LDOCAMA_PD_EN | BIT_SLP_LDOSIM2_PD_EN | //BIT_SLP_LDOSIM1_PD_EN | //BIT_SLP_LDOSIM0_PD_EN | BIT_SLP_LDOSD_PD_EN | BIT_SLP_LDOAVDD18_PD_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2, //BIT_SLP_DCDC_BG_LP_EN | //BIT_SLP_DCDCCORE_LP_EN | //BIT_SLP_DCDCMEM_LP_EN | //BIT_SLP_DCDCARM_LP_EN | //BIT_SLP_DCDCGEN_LP_EN | //BIT_SLP_DCDCWPA_LP_EN | //BIT_SLP_DCDCWRF_LP_EN | //BIT_SLP_LDOEMMCCORE_LP_EN | //BIT_SLP_LDOEMMCIO_LP_EN | //BIT_SLP_LDORF2_LP_EN | //BIT_SLP_LDORF1_LP_EN | //BIT_SLP_LDORF0_LP_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3, //BIT_SLP_BG_LP_EN | //BIT_SLP_LDOVDD25_LP_EN | //BIT_SLP_LDOVDD28_LP_EN | //BIT_SLP_LDOVDD18_LP_EN | //BIT_SLP_LDOCLSG_LP_EN | //BIT_SLP_LDOUSB_LP_EN | //BIT_SLP_LDOCAMMOT_LP_EN | //BIT_SLP_LDOCAMIO_LP_EN | //BIT_SLP_LDOCAMD_LP_EN | //BIT_SLP_LDOCAMA_LP_EN | //BIT_SLP_LDOSIM2_LP_EN | //BIT_SLP_LDOSIM1_LP_EN | //BIT_SLP_LDOSIM0_LP_EN | //BIT_SLP_LDOSD_LP_EN | //BIT_SLP_LDOAVDD18_LP_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_XTL_WAIT_CTRL, BIT_SLP_XTLBUF_PD_EN | BIT_XTL_EN | BITS_XTL_WAIT(0x32)| 0 ); ANA_REG_SET(ANA_REG_GLB_DDR2_CTRL, BIT_DDR2_BUF_PD_HW | BITS_DDR2_BUF_S_DS(0x0) | BITS_DDR2_BUF_CHNS_DS(0x0) | //BIT_DDR2_BUF_PD | BITS_DDR2_BUF_S(0x3) | BITS_DDR2_BUF_CHNS(0x0) | 0 ); /**************************************** * Following is CP LDO Sleep Control * ****************************************/ ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL, //BIT_LDO_VDD18_EXT_XTL2_EN | //BIT_LDO_VDD18_EXT_XTL1_EN | //BIT_LDO_VDD18_EXT_XTL0_EN | //BIT_LDO_VDD18_XTL2_EN | //BIT_LDO_VDD18_XTL1_EN | //BIT_LDO_VDD18_XTL0_EN | //BIT_LDO_VDD28_EXT_XTL2_EN | //BIT_LDO_VDD28_EXT_XTL1_EN | //BIT_LDO_VDD28_EXT_XTL0_EN | //BIT_LDO_VDD28_XTL2_EN | //BIT_LDO_VDD28_XTL1_EN | //BIT_LDO_VDD28_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0, BIT_LDO_XTL_EN | //BIT_LDO_RF1_EXT_XTL2_EN | //BIT_LDO_RF1_EXT_XTL1_EN | //BIT_LDO_RF1_EXT_XTL0_EN | //BIT_LDO_RF1_XTL2_EN | //BIT_LDO_RF1_XTL1_EN | //BIT_LDO_RF1_XTL0_EN | //BIT_LDO_RF0_EXT_XTL2_EN | //BIT_LDO_RF0_EXT_XTL1_EN | //BIT_LDO_RF0_EXT_XTL0_EN | BIT_LDO_RF0_XTL2_EN | BIT_LDO_RF0_XTL1_EN | BIT_LDO_RF0_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1, //BIT_LDO_VDD25_EXT_XTL2_EN | //BIT_LDO_VDD25_EXT_XTL1_EN | //BIT_LDO_VDD25_EXT_XTL0_EN | BIT_LDO_VDD25_XTL2_EN | BIT_LDO_VDD25_XTL1_EN | BIT_LDO_VDD25_XTL0_EN | //BIT_LDO_RF2_EXT_XTL2_EN | //BIT_LDO_RF2_EXT_XTL1_EN | //BIT_LDO_RF2_EXT_XTL0_EN | BIT_LDO_RF2_XTL2_EN | BIT_LDO_RF2_XTL1_EN | BIT_LDO_RF2_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2, //BIT_LDO_AVDD18_EXT_XTL2_EN | //BIT_LDO_AVDD18_EXT_XTL1_EN | //BIT_LDO_AVDD18_EXT_XTL0_EN | //BIT_LDO_AVDD18_XTL2_EN | //BIT_LDO_AVDD18_XTL1_EN | //BIT_LDO_AVDD18_XTL0_EN | //BIT_LDO_SIM2_EXT_XTL2_EN | //BIT_LDO_SIM2_EXT_XTL1_EN | //BIT_LDO_SIM2_EXT_XTL0_EN | //BIT_LDO_SIM2_XTL2_EN | //BIT_LDO_SIM2_XTL1_EN | //BIT_LDO_SIM2_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3, //BIT_DCDC_BG_EXT_XTL2_EN | //BIT_DCDC_BG_EXT_XTL1_EN | //BIT_DCDC_BG_EXT_XTL0_EN | BIT_DCDC_BG_XTL2_EN | BIT_DCDC_BG_XTL1_EN | BIT_DCDC_BG_XTL0_EN | //BIT_BG_EXT_XTL2_EN | //BIT_BG_EXT_XTL1_EN | //BIT_BG_EXT_XTL0_EN | //BIT_BG_XTL2_EN | //BIT_BG_XTL1_EN | //BIT_BG_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4, //BIT_DCDC_WRF_XTL2_EN | //BIT_DCDC_WRF_XTL1_EN | //BIT_DCDC_WRF_XTL0_EN | BIT_DCDC_WPA_XTL2_EN | //BIT_DCDC_WPA_XTL1_EN | //BIT_DCDC_WPA_XTL0_EN | BIT_DCDC_MEM_XTL2_EN | BIT_DCDC_MEM_XTL1_EN | BIT_DCDC_MEM_XTL0_EN | BIT_DCDC_GEN_XTL2_EN | BIT_DCDC_GEN_XTL1_EN | BIT_DCDC_GEN_XTL0_EN | BIT_DCDC_CORE_XTL2_EN | BIT_DCDC_CORE_XTL1_EN | BIT_DCDC_CORE_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5, //BIT_DCDC_WRF_EXT_XTL2_EN | //BIT_DCDC_WRF_EXT_XTL1_EN | //BIT_DCDC_WRF_EXT_XTL0_EN | //BIT_DCDC_WPA_EXT_XTL2_EN | //BIT_DCDC_WPA_EXT_XTL1_EN | //BIT_DCDC_WPA_EXT_XTL0_EN | //BIT_DCDC_MEM_EXT_XTL2_EN | //BIT_DCDC_MEM_EXT_XTL1_EN | //BIT_DCDC_MEM_EXT_XTL0_EN | //BIT_DCDC_GEN_EXT_XTL2_EN | //BIT_DCDC_GEN_EXT_XTL1_EN | //BIT_DCDC_GEN_EXT_XTL0_EN | //BIT_DCDC_CORE_EXT_XTL2_EN | //BIT_DCDC_CORE_EXT_XTL1_EN | //BIT_DCDC_CORE_EXT_XTL0_EN | 0 ); #endif /************************************************ * Following is AP/CP LDO D DIE Sleep Control * *************************************************/ CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG, BIT_XTL0_AP_SEL | BIT_XTL0_CP0_SEL | BIT_XTL0_CP1_SEL | BIT_XTL0_CP2_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG, BIT_XTL1_AP_SEL | BIT_XTL1_CP0_SEL | BIT_XTL1_CP1_SEL | BIT_XTL1_CP2_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG, //BIT_XTL2_AP_SEL | //BIT_XTL2_CP0_SEL | //BIT_XTL2_CP1_SEL | BIT_XTL2_CP2_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG, BIT_XTLBUF0_CP2_SEL | BIT_XTLBUF0_CP1_SEL | BIT_XTLBUF0_CP0_SEL | BIT_XTLBUF0_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG, BIT_XTLBUF1_CP2_SEL | BIT_XTLBUF1_CP1_SEL | BIT_XTLBUF1_CP0_SEL | BIT_XTLBUF1_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG, //BIT_MPLL_REF_SEL | //BIT_MPLL_CP2_SEL | //BIT_MPLL_CP1_SEL | //BIT_MPLL_CP0_SEL | BIT_MPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG, //BIT_DPLL_REF_SEL | BIT_DPLL_CP2_SEL | BIT_DPLL_CP1_SEL | BIT_DPLL_CP0_SEL | BIT_DPLL_AP_SEL | 0 ); /*caution tdpll & wpll sel config in spl*/ reg_val = CHIP_REG_GET(REG_PMU_APB_TDPLL_REL_CFG); reg_val &= ~0xF; reg_val |= ( BIT_TDPLL_CP2_SEL| BIT_TDPLL_CP1_SEL| BIT_TDPLL_CP0_SEL| BIT_TDPLL_AP_SEL | 0); CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG,reg_val); reg_val = CHIP_REG_GET(REG_PMU_APB_WPLL_REL_CFG); reg_val &= ~0xF; reg_val |= ( //BIT_WPLL_CP2_SEL| //BIT_WPLL_CP1_SEL| BIT_WPLL_CP0_SEL| //BIT_WPLL_AP_SEL | 0); CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG,reg_val); CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG, //BIT_CPLL_REF_SEL | BIT_CPLL_CP2_SEL | //BIT_CPLL_CP1_SEL | //BIT_CPLL_CP0_SEL | //BIT_CPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG, BIT_WIFIPLL1_REF_SEL | BIT_WIFIPLL1_CP2_SEL | //BIT_WIFIPLL1_CP1_SEL | //BIT_WIFIPLL1_CP0_SEL | //BIT_WIFIPLL1_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG, BIT_WIFIPLL2_REF_SEL | BIT_WIFIPLL2_CP2_SEL | //BIT_WIFIPLL2_CP1_SEL | //BIT_WIFIPLL2_CP0_SEL | //BIT_WIFIPLL2_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG, BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN | BITS_PD_CA7_TOP_PWR_ON_DLY(8) | BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) | BITS_PD_CA7_TOP_ISO_ON_DLY(4) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG, BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN | BITS_PD_CA7_C0_PWR_ON_DLY(8) | BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) | BITS_PD_CA7_C0_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG, BIT_PD_CA7_C1_FORCE_SHUTDOWN | BITS_PD_CA7_C1_PWR_ON_DLY(8) | BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) | BITS_PD_CA7_C1_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG, BIT_PD_CA7_C2_FORCE_SHUTDOWN | BITS_PD_CA7_C2_PWR_ON_DLY(8) | BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) | BITS_PD_CA7_C2_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG, BIT_PD_CA7_C3_FORCE_SHUTDOWN | BITS_PD_CA7_C3_PWR_ON_DLY(8) | BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) | BITS_PD_CA7_C3_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG, BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN | BITS_PD_AP_SYS_PWR_ON_DLY(8) | BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) | BITS_PD_AP_SYS_ISO_ON_DLY(6) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG, BIT_PD_MM_TOP_FORCE_SHUTDOWN | BITS_PD_MM_TOP_PWR_ON_DLY(8) | BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) | BITS_PD_MM_TOP_ISO_ON_DLY(4) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG, BIT_PD_GPU_TOP_FORCE_SHUTDOWN | BITS_PD_GPU_TOP_PWR_ON_DLY(8) | BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) | BITS_PD_GPU_TOP_ISO_ON_DLY(4) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG, BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN | BITS_PD_PUB_SYS_PWR_ON_DLY(8) | BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) | BITS_PD_PUB_SYS_ISO_ON_DLY(6) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_DDR_PUBL_CFG, BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN | BITS_PD_DDR_PUBL_PWR_ON_DLY(8) | BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(0) | BITS_PD_DDR_PUBL_ISO_ON_DLY(6) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_DDR_PHY_CFG, BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN | BITS_PD_DDR_PHY_PWR_ON_DLY(8) | BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(0) | BITS_PD_DDR_PHY_ISO_ON_DLY(6) | 0 ); CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT, BITS_XTL1_WAIT_CNT(0x39) | BITS_XTL0_WAIT_CNT(0x39) | 0 ); CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT, BITS_XTLBUF1_WAIT_CNT(7) | BITS_XTLBUF0_WAIT_CNT(7) | 0 ); CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1, BITS_WPLL_WAIT_CNT(7) | BITS_TDPLL_WAIT_CNT(7) | BITS_DPLL_WAIT_CNT(7) | BITS_MPLL_WAIT_CNT(7) | 0 ); CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2, BITS_WIFIPLL2_WAIT_CNT(7) | BITS_WIFIPLL1_WAIT_CNT(7) | BITS_CPLL_WAIT_CNT(7) | 0 ); ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM, BITS_SLP_IN_WAIT_DCDCARM(7) | BITS_SLP_OUT_WAIT_DCDCARM(8) | 0 ); /*chip service package init*/ CSP_Init(0); }
void init_ldo_sleep_gr(void) { u32 reg_val; ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0x6e7f)); do{ reg_val = (ANA_REG_GET(ANA_REG_GLB_PWR_WR_PROT_VALUE) & BIT_PWR_WR_PROT); }while(reg_val == 0); ANA_REG_SET(ANA_REG_GLB_LDO_DCDC_PD, BIT_DCDC_TOP_CLKF_EN| BIT_DCDC_TOP_OSC_EN| //BIT_DCDC_GEN_PD| //BIT_DCDC_MEM_PD| //BIT_DCDC_ARM_PD| //BIT_DCDC_CORE_PD| //BIT_LDO_RF0_PD| //BIT_LDO_EMMCCORE_PD| //BIT_LDO_EMMCIO_PD| //BIT_LDO_DCXO_PD| BIT_LDO_CON_PD| //BIT_LDO_VDD25_PD| //BIT_LDO_VDD28_PD| //BIT_LDO_VDD18_PD| //BIT_BG_PD| 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_WR_PROT_VALUE,BITS_PWR_WR_PROT_VALUE(0)); /********************************************** * Following is AP LDO A DIE Sleep Control * *********************************************/ ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL0, BIT_SLP_IO_EN | //BIT_SLP_DCDCGEN_PD_EN | BIT_SLP_DCDCWPA_PD_EN | BIT_SLP_DCDCARM_PD_EN | BIT_SLP_LDORF0_PD_EN | BIT_SLP_LDOEMMCCORE_PD_EN | BIT_SLP_LDOEMMCIO_PD_EN | BIT_SLP_LDODCXO_PD_EN | BIT_SLP_LDOCON_PD_EN | BIT_SLP_LDOVDD25_PD_EN | //BIT_SLP_LDOVDD28_PD_EN | //BIT_SLP_LODVDD18_PD_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL1, BIT_SLP_LDO_PD_EN | BIT_SLP_LDOLPREF_PD_EN | BIT_SLP_LDOCLSG_PD_EN | BIT_SLP_LDOUSB_PD_EN | BIT_SLP_LDOCAMMOT_PD_EN | BIT_SLP_LDOCAMIO_PD_EN | BIT_SLP_LDOCAMD_PD_EN | BIT_SLP_LDOCAMA_PD_EN | BIT_SLP_LDOSIM2_PD_EN | //BIT_SLP_LDOSIM1_PD_EN | //BIT_SLP_LDOSIM0_PD_EN | BIT_SLP_LDOSD_PD_EN | 0); ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL2, BIT_SLP_DCDCCORE_LP_EN | BIT_SLP_DCDCMEM_LP_EN | //BIT_SLP_DCDCARM_LP_EN | //BIT_SLP_DCDCGEN_LP_EN | //BIT_SLP_DCDCWPA_LP_EN | //BIT_SLP_LDORF0_LP_EN | //BIT_SLP_LDOEMMCCORE_LP_EN | //BIT_SLP_LDOEMMCIO_LP_EN | //BIT_SLP_LDODCXO_LP_EN | //BIT_SLP_LDOCON_LP_EN | //BIT_SLP_LDOVDD25_LP_EN | //BIT_SLP_LDOVDD28_LP_EN | //BIT_SLP_LDOVDD18_LP_EN | 0); ANA_REG_SET(ANA_REG_GLB_PWR_SLP_CTRL3, BIT_SLP_BG_LP_EN| //BIT_SLP_LDOCLSG_LP_EN | //BIT_SLP_LDOUSB_LP_EN | //BIT_SLP_LDOCAMMOT_LP_EN | //BIT_SLP_LDOCAMIO_LP_EN | //BIT_SLP_LDOCAMD_LP_EN | //BIT_SLP_LDOCAMA_LP_EN | //BIT_SLP_LDOSIM2_LP_EN | //BIT_SLP_LDOSIM1_LP_EN | //BIT_SLP_LDOSIM0_LP_EN | //BIT_SLP_LDOSD_LP_EN | 0); /**************************************** * Following is CP LDO Sleep Control * ****************************************/ ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0, BIT_LDO_XTL_EN | BIT_LDO_DCXO_EXT_XTL1_EN | BIT_LDO_DCXO_EXT_XTL0_EN | BIT_LDO_DCXO_XTL2_EN | BIT_LDO_DCXO_XTL0_EN | //BIT_LDO_VDD18_EXT_XTL1_EN | //BIT_LDO_VDD18_EXT_XTL0_EN | //BIT_LDO_VDD18_XTL2_EN | //BIT_LDO_VDD18_XTL0_EN | //BIT_LDO_VDD28_EXT_XTL1_EN | //BIT_LDO_VDD28_EXT_XTL0_EN | //BIT_LDO_VDD28_XTL2_EN | //BIT_LDO_VDD28_XTL0_EN | 0); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1, BIT_LDO_RF0_EXT_XTL1_EN | BIT_LDO_RF0_EXT_XTL0_EN | BIT_LDO_RF0_XTL2_EN | BIT_LDO_RF0_XTL0_EN | //BIT_LDO_VDD25_EXT_XTL1_EN | //BIT_LDO_VDD25_EXT_XTL0_EN | BIT_LDO_VDD25_XTL2_EN | BIT_LDO_VDD25_XTL0_EN | //BIT_LDO_CON_EXT_XTL1_EN | //BIT_LDO_CON_EXT_XTL0_EN | //BIT_LDO_CON_XTL2_EN | //BIT_LDO_CON_XTL0_EN | 0); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2, //BIT_LDO_SIM2_EXT_XTL1_EN | //BIT_LDO_SIM2_EXT_XTL0_EN | //BIT_LDO_SIM2_XTL2_EN | //BIT_LDO_SIM2_XTL0_EN | //BIT_LDO_SIM1_EXT_XTL1_EN | //BIT_LDO_SIM1_EXT_XTL0_EN | //BIT_LDO_SIM1_XTL2_EN | //BIT_LDO_SIM1_XTL0_EN | //BIT_LDO_SIM0_EXT_XTL1_EN | //BIT_LDO_SIM0_EXT_XTL0_EN | //BIT_LDO_SIM0_XTL2_EN | //BIT_LDO_SIM0_XTL0_EN | 0); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3, //BIT_XO_EXT_XTL1_EN | //BIT_XO_EXT_XTL0_EN | //BIT_XO_XTL2_EN | //BIT_XO_XTL0_EN | //BIT_BG_EXT_XTL1_EN | //BIT_BG_EXT_XTL0_EN | BIT_BG_XTL2_EN | BIT_BG_XTL0_EN | 0); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4, //BIT_DCDC_WPA_EXT_XTL1_EN | //BIT_DCDC_WPA_EXT_XTL0_EN | //BIT_DCDC_WPA_XTL2_EN | BIT_DCDC_WPA_XTL0_EN | //BIT_DCDC_MEM_EXT_XTL1_EN | //BIT_DCDC_MEM_EXT_XTL0_EN | //BIT_DCDC_MEM_XTL2_EN | //BIT_DCDC_MEM_XTL0_EN | //BIT_DCDC_GEN_EXT_XTL1_EN | //BIT_DCDC_GEN_EXT_XTL0_EN | //BIT_DCDC_GEN_XTL2_EN | //BIT_DCDC_GEN_XTL0_EN | //BIT_DCDC_CORE_EXT_XTL1_EN | //BIT_DCDC_CORE_EXT_XTL0_EN | BIT_DCDC_CORE_XTL2_EN | BIT_DCDC_CORE_XTL0_EN | 0); /************************************************ * Following is AP/CP LDO D DIE Sleep Control * *************************************************/ CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG, BIT_XTL0_AP_SEL | BIT_XTL0_CP0_SEL | //BIT_XTL0_CP1_SEL | BIT_XTL0_CP2_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG, BIT_XTL1_AP_SEL | BIT_XTL1_CP0_SEL | //BIT_XTL1_CP1_SEL | BIT_XTL1_CP2_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG, //BIT_XTL2_AP_SEL | //BIT_XTL2_CP0_SEL | //BIT_XTL2_CP1_SEL | BIT_XTL2_CP2_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG, BIT_XTLBUF0_CP2_SEL | BIT_XTLBUF0_CP1_SEL | BIT_XTLBUF0_CP0_SEL | BIT_XTLBUF0_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG, BIT_XTLBUF1_CP2_SEL | //BIT_XTLBUF1_CP1_SEL | BIT_XTLBUF1_CP0_SEL | BIT_XTLBUF1_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG, //BIT_MPLL_REF_SEL | //BIT_MPLL_CP2_SEL | //BIT_MPLL_CP1_SEL | //BIT_MPLL_CP0_SEL | BIT_MPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG, //BIT_DPLL_REF_SEL | BIT_DPLL_CP2_SEL | //BIT_DPLL_CP1_SEL | BIT_DPLL_CP0_SEL | BIT_DPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG, //BIT_TDPLL_REF_SEL | BIT_TDPLL_CP2_SEL | //BIT_TDPLL_CP1_SEL | BIT_TDPLL_CP0_SEL | BIT_TDPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG, //BIT_WPLL_REF_SEL | //BIT_WPLL_CP2_SEL | //BIT_WPLL_CP1_SEL | BIT_WPLL_CP0_SEL | //BIT_WPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG, //BIT_CPLL_REF_SEL | BIT_CPLL_CP2_SEL | //BIT_CPLL_CP1_SEL | //BIT_CPLL_CP0_SEL | //BIT_CPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_WIFIPLL1_REL_CFG, //BIT_WIFIPLL1_REF_SEL | BIT_WIFIPLL1_CP2_SEL | //BIT_WIFIPLL1_CP1_SEL | //BIT_WIFIPLL1_CP0_SEL | //BIT_WIFIPLL1_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_WIFIPLL2_REL_CFG, //BIT_WIFIPLL2_REF_SEL | BIT_WIFIPLL2_CP2_SEL | //BIT_WIFIPLL2_CP1_SEL | //BIT_WIFIPLL2_CP0_SEL | //BIT_WIFIPLL2_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_CGM_AP_EN, BIT_CGM_208M_AP_EN | BIT_CGM_12M_AP_EN | BIT_CGM_24M_AP_EN | BIT_CGM_48M_AP_EN | BIT_CGM_51M2_AP_EN | BIT_CGM_64M_AP_EN | BIT_CGM_76M8_AP_EN | BIT_CGM_96M_AP_EN | BIT_CGM_128M_AP_EN | BIT_CGM_153M6_AP_EN | BIT_CGM_192M_AP_EN | BIT_CGM_256M_AP_EN | BIT_CGM_384M_AP_EN | BIT_CGM_312M_AP_EN | BIT_CGM_MPLL_AP_EN | //BIT_CGM_WPLL_AP_EN | //BIT_CGM_WIFIPLL1_AP_EN | BIT_CGM_TDPLL_AP_EN | //BIT_CGM_CPLL_AP_EN | BIT_CGM_DPLL_AP_EN | BIT_CGM_26M_AP_EN | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG, BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN | BITS_PD_CA7_TOP_PWR_ON_DLY(8) | BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) | BITS_PD_CA7_TOP_ISO_ON_DLY(4) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG, BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN | BITS_PD_CA7_C0_PWR_ON_DLY(8) | BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) | BITS_PD_CA7_C0_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG, BIT_PD_CA7_C1_FORCE_SHUTDOWN | BITS_PD_CA7_C1_PWR_ON_DLY(8) | BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) | BITS_PD_CA7_C1_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG, BIT_PD_CA7_C2_FORCE_SHUTDOWN | BITS_PD_CA7_C2_PWR_ON_DLY(8) | BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) | BITS_PD_CA7_C2_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG, BIT_PD_CA7_C3_FORCE_SHUTDOWN | BITS_PD_CA7_C3_PWR_ON_DLY(8) | BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) | BITS_PD_CA7_C3_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG, BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN | BITS_PD_AP_SYS_PWR_ON_DLY(8) | BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) | BITS_PD_AP_SYS_ISO_ON_DLY(6) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG, BIT_PD_MM_TOP_FORCE_SHUTDOWN | BITS_PD_MM_TOP_PWR_ON_DLY(8) | BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) | BITS_PD_MM_TOP_ISO_ON_DLY(4) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG, BIT_PD_GPU_TOP_FORCE_SHUTDOWN | BITS_PD_GPU_TOP_PWR_ON_DLY(8) | BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) | BITS_PD_GPU_TOP_ISO_ON_DLY(4) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG, BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN | BITS_PD_PUB_SYS_PWR_ON_DLY(8) | BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) | BITS_PD_PUB_SYS_ISO_ON_DLY(6) | 0 ); CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT, BITS_XTL1_WAIT_CNT(0x39) | BITS_XTL0_WAIT_CNT(0x39) | 0 ); CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT, BITS_XTLBUF1_WAIT_CNT(7) | BITS_XTLBUF0_WAIT_CNT(7) | 0 ); CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1, BITS_WPLL_WAIT_CNT(7) | BITS_TDPLL_WAIT_CNT(7) | BITS_DPLL_WAIT_CNT(7) | BITS_MPLL_WAIT_CNT(7) | 0 ); CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2, BITS_WIFIPLL2_WAIT_CNT(7) | BITS_WIFIPLL1_WAIT_CNT(7) | BITS_CPLL_WAIT_CNT(7) | 0 ); ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM, BITS_SLP_IN_WAIT_DCDCARM(9) | BITS_SLP_OUT_WAIT_DCDCARM(8) | 0 ); /*work round sin0 disconnect*/ reg_val = CHIP_REG_GET(REG_AON_APB_SINDRV_CTRL); reg_val |= BIT_SINDRV_ENA_SQUARE; CHIP_REG_SET(REG_AON_APB_SINDRV_CTRL, reg_val); }
void init_ldo_sleep_gr(void) { ANA_REG_OR(ANA_REG_GLB_LDO_DCDC_PD_RTCSET, (BIT_LDO_RF1_PD_RTCSET | BIT_DCDC_WRF_PD_RTCSET)); ANA_REG_AND(ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, (~(BIT_LDO_RF1_PD_RTCSET | BIT_DCDC_WRF_PD_RTCSET))); ANA_REG_OR(ANA_REG_GLB_LDO_PD_CTRL, (BIT_DCDC_WPA_PD)); /********************************************** * Following is AP LDO A DIE Sleep Control * *********************************************/ ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL0, BIT_SLP_IO_EN | BIT_SLP_DCDC_OTP_PD_EN | //BIT_SLP_DCDCGEN_PD_EN | //BIT_SLP_DCDCWPA_PD_EN | //BIT_SLP_DCDCWRF_PD_EN | BIT_SLP_DCDCARM_PD_EN | BIT_SLP_LDOEMMCCORE_PD_EN | BIT_SLP_LDOEMMCIO_PD_EN | BIT_SLP_LDORF2_PD_EN | //BIT_SLP_LDORF1_PD_EN | BIT_SLP_LDORF0_PD_EN | BIT_SLP_LDOVDD25_PD_EN | //BIT_SLP_LDOVDD28_PD_EN | //BIT_SLP_LDOVDD18_PD_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL1, BIT_SLP_LDO_PD_EN | BIT_SLP_LDOLPREF_PD_EN | BIT_SLP_LDOCLSG_PD_EN | BIT_SLP_LDOUSB_PD_EN | BIT_SLP_LDOCAMMOT_PD_EN | BIT_SLP_LDOCAMIO_PD_EN | BIT_SLP_LDOCAMD_PD_EN | BIT_SLP_LDOCAMA_PD_EN | BIT_SLP_LDOSIM2_PD_EN | //BIT_SLP_LDOSIM1_PD_EN | //BIT_SLP_LDOSIM0_PD_EN | BIT_SLP_LDOSD_PD_EN | BIT_SLP_LDOAVDD18_PD_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL2, //BIT_SLP_DCDC_BG_LP_EN | //BIT_SLP_DCDCCORE_LP_EN | //BIT_SLP_DCDCMEM_LP_EN | //BIT_SLP_DCDCARM_LP_EN | //BIT_SLP_DCDCGEN_LP_EN | //BIT_SLP_DCDCWPA_LP_EN | //BIT_SLP_DCDCWRF_LP_EN | //BIT_SLP_LDOEMMCCORE_LP_EN | //BIT_SLP_LDOEMMCIO_LP_EN | //BIT_SLP_LDORF2_LP_EN | //BIT_SLP_LDORF1_LP_EN | //BIT_SLP_LDORF0_LP_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_LDO_SLP_CTRL3, //BIT_SLP_BG_LP_EN | //BIT_SLP_LDOVDD25_LP_EN | //BIT_SLP_LDOVDD28_LP_EN | //BIT_SLP_LDOVDD18_LP_EN | //BIT_SLP_LDOCLSG_LP_EN | //BIT_SLP_LDOUSB_LP_EN | //BIT_SLP_LDOCAMMOT_LP_EN | //BIT_SLP_LDOCAMIO_LP_EN | //BIT_SLP_LDOCAMD_LP_EN | //BIT_SLP_LDOCAMA_LP_EN | //BIT_SLP_LDOSIM2_LP_EN | //BIT_SLP_LDOSIM1_LP_EN | //BIT_SLP_LDOSIM0_LP_EN | //BIT_SLP_LDOSD_LP_EN | //BIT_SLP_LDOAVDD18_LP_EN | 0 ); /**************************************** * Following is CP LDO Sleep Control * ****************************************/ ANA_REG_SET(ANA_REG_GLB_LDO1828_XTL_CTL, //BIT_LDO_VDD18_EXT_XTL2_EN | //BIT_LDO_VDD18_EXT_XTL1_EN | //BIT_LDO_VDD18_EXT_XTL0_EN | //BIT_LDO_VDD18_XTL2_EN | //BIT_LDO_VDD18_XTL1_EN | //BIT_LDO_VDD18_XTL0_EN | //BIT_LDO_VDD28_EXT_XTL2_EN | //BIT_LDO_VDD28_EXT_XTL1_EN | //BIT_LDO_VDD28_EXT_XTL0_EN | //BIT_LDO_VDD28_XTL2_EN | //BIT_LDO_VDD28_XTL1_EN | //BIT_LDO_VDD28_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN0, BIT_LDO_XTL_EN | //BIT_LDO_RF1_EXT_XTL2_EN | //BIT_LDO_RF1_EXT_XTL1_EN | //BIT_LDO_RF1_EXT_XTL0_EN | //BIT_LDO_RF1_XTL2_EN | //BIT_LDO_RF1_XTL1_EN | //BIT_LDO_RF1_XTL0_EN | //BIT_LDO_RF0_EXT_XTL2_EN | //BIT_LDO_RF0_EXT_XTL1_EN | //BIT_LDO_RF0_EXT_XTL0_EN | BIT_LDO_RF0_XTL2_EN | BIT_LDO_RF0_XTL1_EN | BIT_LDO_RF0_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN1, //BIT_LDO_VDD25_EXT_XTL2_EN | //BIT_LDO_VDD25_EXT_XTL1_EN | //BIT_LDO_VDD25_EXT_XTL0_EN | BIT_LDO_VDD25_XTL2_EN | BIT_LDO_VDD25_XTL1_EN | BIT_LDO_VDD25_XTL0_EN | //BIT_LDO_RF2_EXT_XTL2_EN | //BIT_LDO_RF2_EXT_XTL1_EN | //BIT_LDO_RF2_EXT_XTL0_EN | BIT_LDO_RF2_XTL2_EN | BIT_LDO_RF2_XTL1_EN | BIT_LDO_RF2_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN2, //BIT_LDO_AVDD18_EXT_XTL2_EN | //BIT_LDO_AVDD18_EXT_XTL1_EN | //BIT_LDO_AVDD18_EXT_XTL0_EN | //BIT_LDO_AVDD18_XTL2_EN | //BIT_LDO_AVDD18_XTL1_EN | //BIT_LDO_AVDD18_XTL0_EN | //BIT_LDO_SIM2_EXT_XTL2_EN | //BIT_LDO_SIM2_EXT_XTL1_EN | //BIT_LDO_SIM2_EXT_XTL0_EN | //BIT_LDO_SIM2_XTL2_EN | //BIT_LDO_SIM2_XTL1_EN | //BIT_LDO_SIM2_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN3, //BIT_DCDC_BG_EXT_XTL2_EN | //BIT_DCDC_BG_EXT_XTL1_EN | //BIT_DCDC_BG_EXT_XTL0_EN | BIT_DCDC_BG_XTL2_EN | BIT_DCDC_BG_XTL1_EN | BIT_DCDC_BG_XTL0_EN | //BIT_BG_EXT_XTL2_EN | //BIT_BG_EXT_XTL1_EN | //BIT_BG_EXT_XTL0_EN | //BIT_BG_XTL2_EN | //BIT_BG_XTL1_EN | //BIT_BG_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN4, //BIT_DCDC_WRF_XTL2_EN | //BIT_DCDC_WRF_XTL1_EN | //BIT_DCDC_WRF_XTL0_EN | //BIT_DCDC_WPA_XTL2_EN | //BIT_DCDC_WPA_XTL1_EN | //BIT_DCDC_WPA_XTL0_EN | BIT_DCDC_MEM_XTL2_EN | BIT_DCDC_MEM_XTL1_EN | BIT_DCDC_MEM_XTL0_EN | BIT_DCDC_GEN_XTL2_EN | BIT_DCDC_GEN_XTL1_EN | BIT_DCDC_GEN_XTL0_EN | BIT_DCDC_CORE_XTL2_EN | BIT_DCDC_CORE_XTL1_EN | BIT_DCDC_CORE_XTL0_EN | 0 ); ANA_REG_SET(ANA_REG_GLB_PWR_XTL_EN5, //BIT_DCDC_WRF_EXT_XTL2_EN | //BIT_DCDC_WRF_EXT_XTL1_EN | //BIT_DCDC_WRF_EXT_XTL0_EN | //BIT_DCDC_WPA_EXT_XTL2_EN | //BIT_DCDC_WPA_EXT_XTL1_EN | //BIT_DCDC_WPA_EXT_XTL0_EN | //BIT_DCDC_MEM_EXT_XTL2_EN | //BIT_DCDC_MEM_EXT_XTL1_EN | //BIT_DCDC_MEM_EXT_XTL0_EN | //BIT_DCDC_GEN_EXT_XTL2_EN | //BIT_DCDC_GEN_EXT_XTL1_EN | //BIT_DCDC_GEN_EXT_XTL0_EN | //BIT_DCDC_CORE_EXT_XTL2_EN | //BIT_DCDC_CORE_EXT_XTL1_EN | //BIT_DCDC_CORE_EXT_XTL0_EN | 0 ); /************************************************ * Following is AP/CP LDO D DIE Sleep Control * *************************************************/ CHIP_REG_SET(REG_PMU_APB_XTL0_REL_CFG, BIT_XTL0_AP_SEL | BIT_XTL0_CP0_SEL | BIT_XTL0_CP1_SEL | BIT_XTL0_CP2_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTL1_REL_CFG, BIT_XTL1_AP_SEL | BIT_XTL1_CP0_SEL | BIT_XTL1_CP1_SEL | BIT_XTL1_CP2_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTL2_REL_CFG, BIT_XTL2_AP_SEL | BIT_XTL2_CP0_SEL | BIT_XTL2_CP1_SEL | BIT_XTL2_CP2_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTLBUF0_REL_CFG, BIT_XTLBUF0_CP2_SEL | BIT_XTLBUF0_CP1_SEL | BIT_XTLBUF0_CP0_SEL | BIT_XTLBUF0_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_XTLBUF1_REL_CFG, BIT_XTLBUF1_CP2_SEL | BIT_XTLBUF1_CP1_SEL | BIT_XTLBUF1_CP0_SEL | BIT_XTLBUF1_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_MPLL_REL_CFG, //BIT_MPLL_REF_SEL | //BIT_MPLL_CP2_SEL | //BIT_MPLL_CP1_SEL | //BIT_MPLL_CP0_SEL | BIT_MPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_DPLL_REL_CFG, //BIT_DPLL_REF_SEL | BIT_DPLL_CP2_SEL | BIT_DPLL_CP1_SEL | BIT_DPLL_CP0_SEL | BIT_DPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_TDPLL_REL_CFG, //BIT_TDPLL_REF_SEL | BIT_TDPLL_CP2_SEL | BIT_TDPLL_CP1_SEL | BIT_TDPLL_CP0_SEL | BIT_TDPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_WPLL_REL_CFG, //BIT_WPLL_REF_SEL | //BIT_WPLL_CP2_SEL | //BIT_WPLL_CP1_SEL | BIT_WPLL_CP0_SEL | //BIT_WPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_CPLL_REL_CFG, //BIT_CPLL_REF_SEL | BIT_CPLL_CP2_SEL | BIT_CPLL_CP1_SEL | //BIT_CPLL_CP0_SEL | //BIT_CPLL_AP_SEL | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_TOP_CFG, BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN | BITS_PD_CA7_TOP_PWR_ON_DLY(8) | BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(2) | BITS_PD_CA7_TOP_ISO_ON_DLY(4) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C0_CFG, BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN | BITS_PD_CA7_C0_PWR_ON_DLY(8) | BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(6) | BITS_PD_CA7_C0_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C1_CFG, BIT_PD_CA7_C1_FORCE_SHUTDOWN | BITS_PD_CA7_C1_PWR_ON_DLY(8) | BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(4) | BITS_PD_CA7_C1_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C2_CFG, BIT_PD_CA7_C2_FORCE_SHUTDOWN | BITS_PD_CA7_C2_PWR_ON_DLY(8) | BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(4) | BITS_PD_CA7_C2_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_CA7_C3_CFG, BIT_PD_CA7_C3_FORCE_SHUTDOWN | BITS_PD_CA7_C3_PWR_ON_DLY(8) | BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(4) | BITS_PD_CA7_C3_ISO_ON_DLY(2) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_AP_SYS_CFG, BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN | BITS_PD_AP_SYS_PWR_ON_DLY(8) | BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(0) | BITS_PD_AP_SYS_ISO_ON_DLY(6) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_MM_TOP_CFG, BIT_PD_MM_TOP_FORCE_SHUTDOWN | BITS_PD_MM_TOP_PWR_ON_DLY(8) | BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(0) | BITS_PD_MM_TOP_ISO_ON_DLY(4) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_GPU_TOP_CFG, BIT_PD_GPU_TOP_FORCE_SHUTDOWN | BITS_PD_GPU_TOP_PWR_ON_DLY(8) | BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(0) | BITS_PD_GPU_TOP_ISO_ON_DLY(4) | 0 ); CHIP_REG_SET(REG_PMU_APB_PD_PUB_SYS_CFG, BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN | BITS_PD_PUB_SYS_PWR_ON_DLY(8) | BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(0) | BITS_PD_PUB_SYS_ISO_ON_DLY(6) | 0 ); CHIP_REG_SET(REG_PMU_APB_XTL_WAIT_CNT, BITS_XTL1_WAIT_CNT(0x39) | BITS_XTL0_WAIT_CNT(0x39) | 0 ); CHIP_REG_SET(REG_PMU_APB_XTLBUF_WAIT_CNT, BITS_XTLBUF1_WAIT_CNT(7) | BITS_XTLBUF0_WAIT_CNT(7) | 0 ); CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT1, BITS_WPLL_WAIT_CNT(7) | BITS_TDPLL_WAIT_CNT(7) | BITS_DPLL_WAIT_CNT(7) | BITS_MPLL_WAIT_CNT(7) | 0 ); CHIP_REG_SET(REG_PMU_APB_PLL_WAIT_CNT2, BITS_WIFIPLL2_WAIT_CNT(7) | BITS_WIFIPLL1_WAIT_CNT(7) | BITS_CPLL_WAIT_CNT(7) | 0 ); ANA_REG_SET(ANA_REG_GLB_SLP_WAIT_DCDCARM, BITS_SLP_IN_WAIT_DCDCARM(9) | BITS_SLP_OUT_WAIT_DCDCARM(8) | 0 ); }
/* pll */ static void pll_xtl_with_sys_config(struct pll_cfg *cfg, struct pll_reg_bit *pll_reg) { /*enable all xtl for simply config. xtlbuf0 is for ap, xtlbuf1 is for tdpll, choose!*/ unsigned int i = 0, j; unsigned int sel_mode = 0, sel_tmp = 0; if ((!cfg) || (cfg[0].pll_id == RESERVED_NUM) || (pll_reg == NULL)) { return; } /*collecting the current system mode, like TD only ..etc.*/ while (cfg[i].pll_id != RESERVED_NUM) { j = 0; while (pll_reg[j].pll_id != RESERVED_NUM) { if (cfg[i].pll_id == pll_reg[j].pll_id) { break; } ++j; } /* set xtl ref */ if (pll_reg[j].cgm_ap_reg != -1) { if (cfg[i].cgm_ap_en != NO_USED) { if (cfg[i].cgm_ap_en == LP_EN) { CHIP_REG_OR(pll_reg[j].cgm_ap_reg, pll_reg[j].cgm_ap_reg_bitmsk); } else if (cfg[i].cgm_ap_en == LP_DIS){ CHIP_REG_AND(pll_reg[j].cgm_ap_reg, ~(pll_reg[j].cgm_ap_reg_bitmsk)); } } } sel_mode = 0; /* set select by ap,cp0,cp1,cp2 */ if (pll_reg[j].pll_sys_reg != -1) { if(cfg[i].sys != NO_USED) { if (cfg[i].sys & AP_SYS) { sel_mode |= BIT(0); } if (cfg[i].sys & CP0_SYS) { sel_mode |= BIT(1); } if (cfg[i].sys & CP1_SYS) { sel_mode |= BIT(2); } if (cfg[i].sys & CP2_SYS) { sel_mode |= BIT(3); } if (cfg[i].sys & REF_SYS) { sel_mode |= BIT(4); } sel_tmp = CHIP_REG_GET(pll_reg[j].pll_sys_reg); sel_tmp &= ~pll_reg[j].pll_sys_reg_bitmsk; sel_tmp |= (sel_mode << __ffs(pll_reg[j].pll_sys_reg_bitmsk) & pll_reg[j].pll_sys_reg_bitmsk); CHIP_REG_SET(pll_reg[j].pll_sys_reg, sel_tmp); } } if (pll_reg[j].pll_wait_reg != -1) { if (cfg[i].wait != NO_USED) { sel_mode = cfg[i].wait << __ffs(pll_reg[j].pll_wait_reg_bitmsk); sel_mode &= pll_reg[j].pll_wait_reg_bitmsk; sel_tmp = CHIP_REG_GET(pll_reg[j].pll_wait_reg); sel_tmp &= ~pll_reg[j].pll_wait_reg_bitmsk; sel_tmp |= sel_mode; CHIP_REG_SET(pll_reg[j].pll_wait_reg, sel_tmp); } } ++i; } }