static inline void resettimer(int count) {
tcu_writel(CH_TDFR(CLKEVENT_CH),count);
tcu_writel(CH_TCNT(CLKEVENT_CH),0);
tcu_writel(TCU_TMCR , (1 << CLKEVENT_CH));
tcu_writel(TCU_TFCR , (1 << CLKEVENT_CH));
tcu_writel(TCU_TESR , (1 << CLKEVENT_CH));
}
void __cpuinit jzcpu_timer_setup(void)
{
int cpu = smp_processor_id();
struct jz_timerevent *evt = &per_cpu(jzclockevent, cpu);
evt->cpu = cpu;
evt->state = INIT;
switch(cpu) {
case 0:
evt->state = FINI;
evt->ch = 5;
evt->irq = IRQ_TCU1;
evt->count_addr = TCU_IOBASE + CH_TCNT(evt->ch);
evt->latch_addr = TCU_IOBASE + CH_TDFR(evt->ch);
evt->ctrl_addr = TCU_IOBASE;
evt->config_addr = TCU_IOBASE + CH_TCSR(evt->ch);
tcu_writel(CH_TDHR(evt->ch), 0xffff);
tcu_writel(TCU_TMSR, ((1 << evt->ch) | (1 << (evt->ch + 16))));
break;
case 1:
evt->ch = 15;
evt->irq = IRQ_TCU0;
evt->count_addr = APB_OST_IOBASE + OSTCNTL;
evt->latch_addr = APB_OST_IOBASE + OSTDR;
evt->ctrl_addr = TCU_IOBASE;
evt->config_addr = APB_OST_IOBASE + OSTCSR;
apbost_writel(OSTCNTH, 0);
break;
}
#ifdef CONFIG_HOTPLUG_CPU
jz_set_cpu_affinity(evt->irq,0);
#endif
jz_clockevent_init(evt,cpu);
}
static void reset_timer(int count)
{
unsigned int tcsr = tcu_readl(CH_TCSR(tcu_channel));
/* set count */
tcu_writel(CH_TDFR(tcu_channel),count);
tcu_writel(CH_TDHR(tcu_channel),count/2);
tcu_writel(TCU_TMCR , (1 << tcu_channel));
start_timer();
}
