void ezTWI_MasterMode_Read(unsigned short DeviceAddr, unsigned char *TWI_SensorDataREAD, unsigned short TX_Count, unsigned short TWI_TX_Length)
{
#define PRESCALE120M 12 // factor = 12, 120MHz/10MHz
*pTWI_FIFO_CTL |= RCVFLUSH; // Clear the TX FIFO
*pTWI_MASTER_STAT = BUFWRERR | BUFRDERR | DNAK | ANAK | LOSTARB; // Clear all status error
ssync();
*pTWI_FIFO_CTL = 0; // Clear the bit manually
*pTWI_CONTROL = TWI_ENA | PRESCALE120M; // PRESCALE = fsclk/10MHz
*pTWI_CLKDIV = CLKLOW(50) | CLKHI(50); // For 100KHz SCL speed: CLKDIV = (1/100KHz)/(1/10MHz) = 100 -> SCL symetric: CLKHI = 50, CLKLOW = 50
*pTWI_MASTER_ADDR = DeviceAddr; // Target address (7-bits plus the read/write bit the TWI controls
for (i = 0; i < TX_Count; i++)
{
*pTWI_MASTER_CTL = (TWI_TX_Length<<6) | MEN | MDIR; // Start transmission
for (j = 0; j < (TWI_TX_Length-1); j++)
{
while (*pTWI_FIFO_STAT == 0) // wait to load the next sample into the TX FIFO
ssync();
TWI_SensorDataREAD[j] = *pTWI_RCV_DATA8; // Load the next sample into the TX FIFO. Pointer to an array where a list of data is located
ssync();
}
while ((*pTWI_INT_STAT & MCOMP) == 0) // Wait until transmission complete and MCOMP is set
ssync();
*pTWI_INT_STAT = RCVSTAT | MCOMP; // service TWI for next transmission
}
}
void initDSP() {
// Clock
// 158.0544MHz
int ssel = 8;
int csel = 0;
ADI_SYSCTRL_VALUES pll;
pll.uwPllCtl = SET_MSEL(14);
pll.uwPllDiv = ssel + (csel << 4);
pll.uwVrCtl = 0x7000;
bfrom_SysControl(SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV, &pll, NULL);
while ((*pPLL_STAT & PLL_LOCKED) == 0);
// GPIO G
*pPORTG_FER = 0;
*pPORTGIO_DIR = CODEC_RESET | CODEC_CS;
*pPORTGIO_SET = CODEC_CS;
*pPORTGIO_CLEAR = CODEC_RESET;
// GPIO F
*pPORTF_FER = 0;
*pPORTFIO_DIR = TEST_PIN;
*pPORTFIO_SET = TEST_PIN;
// I2C
*pTWI_CLKDIV = CLKLOW(I2C_CLK_LOHI) | CLKHI(I2C_CLK_LOHI);
ssync();
*pTWI_CONTROL = TWI_ENA | 10;
// I2S
*pPORTG_FER |= PG1 | PG5 | PG6 | PG7;
// SPI
*pPORTF_FER |= PF15 | PF14 | PF13;
*pSPI0_FLG = 0b00000000000010;
*pSPI0_BAUD = SPI_BAUD;
ssync();
*pSPI0_CTL = 0b0101000000001101;
}