MUX_SRC_LIST(
{&cnoc_clk.c, 0x0008},
{&pnoc_clk.c, 0x0010},
{&snoc_clk.c, 0x0000},
{&bimc_clk.c, 0x0155},
),
.c = {
.dbg_name = "rpm_debug_mux",
.ops = &clk_ops_gen_mux,
.flags = CLKFLAG_NO_RATE_CACHE,
CLK_INIT(rpm_debug_mux.c),
},
};
static struct clk_lookup msm_clocks_rpm_8974[] = {
CLK_LOOKUP_OF("rpm_debug_mux", rpm_debug_mux,
"fc401880.qcom,cc-debug"),
CLK_LOOKUP_OF("xo", cxo_gcc, "fc400000.qcom,gcc"),
CLK_LOOKUP_OF("xo", cxo_mmss, "fd8c0000.qcom,mmsscc"),
CLK_LOOKUP_OF("mmssnoc_ahb", mmssnoc_ahb_clk, "fd8c0000.qcom,mmsscc"),
CLK_LOOKUP_OF("xo", cxo_otg_clk, "msm_otg"),
CLK_LOOKUP_OF("xo", cxo_pil_lpass_clk, "fe200000.qcom,lpass"),
CLK_LOOKUP_OF("xo", cxo_pil_mss_clk, "fc880000.qcom,mss"),
CLK_LOOKUP_OF("xo", cxo_wlan_clk, "fb000000.qcom,wcnss-wlan"),
CLK_LOOKUP_OF("rf_clk", cxo_a2, "fb000000.qcom,wcnss-wlan"),
CLK_LOOKUP_OF("xo", cxo_pil_pronto_clk, "fb21b000.qcom,pronto"),
CLK_LOOKUP_OF("xo", cxo_dwc3_clk, "msm_dwc3"),
CLK_LOOKUP_OF("xo", cxo_ehci_host_clk, "msm_ehci_host"),
CLK_LOOKUP_OF("xo", cxo_lpm_clk, "fc4281d0.qcom,mpm"),
CLK_LOOKUP_OF("hfpll_src", cxo_a_clk_src, "f9016000.qcom,clock-krait"),
static struct platform_driver msm_clock_gcc_driver = {
.probe = msm_gcc_probe,
.driver = {
.name = "qcom,gcc-fsm9010",
.of_match_table = msm_clock_gcc_match_table,
.owner = THIS_MODULE,
},
};
static int __init msm_gcc_init(void)
{
return platform_driver_register(&msm_clock_gcc_driver);
}
static struct clk_lookup msm_clocks_measure[] = {
CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),
};
static int msm_clock_debug_probe(struct platform_device *pdev)
{
int ret;
clk_ops_debug_mux = clk_ops_gen_mux;
clk_ops_debug_mux.get_rate = measure_get_rate;
ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_measure,
ARRAY_SIZE(msm_clocks_measure));
if (ret) {
dev_err(&pdev->dev, "Failed to register debug Mux\n");
return ret;
}
struct div_clk byte_clk_src_8974 = {
.ops = &fixed_4div_ops,
.data = {
.min_div = 4,
.max_div = 4,
},
.c = {
.parent = &byte_mux_8974.c,
.dbg_name = "byte_clk_src",
.ops = &byte_clk_src_ops,
CLK_INIT(byte_clk_src_8974.c),
},
};
static struct clk_lookup mdss_dsi_pllcc_8974[] = {
CLK_LOOKUP_OF("pixel_src", pixel_clk_src_8974,
"fd8c0000.qcom,mmsscc-mdss"),
CLK_LOOKUP_OF("byte_src", byte_clk_src_8974,
"fd8c0000.qcom,mmsscc-mdss"),
};
int dsi_pll_clock_register(struct platform_device *pdev,
struct mdss_pll_resources *pll_res)
{
int rc;
if (!pll_res || !pll_res->pll_base) {
pr_err("Invalide input parameters\n");
return -EPROBE_DEFER;
}
/* Set client data to mux, div and vco clocks */
},
};
static struct branch_clk q6ss_ahbm_clk = {
.cbcr_reg = Q6SS_AHBM_CBCR,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
.dbg_name = "q6ss_ahbm_clk",
.ops = &clk_ops_branch,
CLK_INIT(q6ss_ahbm_clk.c),
},
};
static struct clk_lookup msm_clocks_lpass_8974[] = {
CLK_LOOKUP_OF("core_clk", q6ss_xo_clk, "fe200000.qti,lpass"),
CLK_LOOKUP_OF("iface_clk", q6ss_ahb_lfabif_clk, "fe200000.qti,lpass"),
CLK_LOOKUP_OF("reg_clk", q6ss_ahbm_clk, "fe200000.qti,lpass"),
};
static struct of_device_id msm_clock_lpasscc_match_table[] = {
{ .compatible = "qcom,lpasscc-8974" },
{}
};
static int msm_lpasscc_8974_probe(struct platform_device *pdev)
{
struct resource *res;
int ret;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
