/*!
* @brief Example function to show how to change from BLPE to PEE mode.
* MCG transition: BLPE -> PBE -> PEE
*/
void APP_ChangeBlpeToPeeExample(void)
{
/* Change BLPE -> PBE */
CLOCK_SetPbeMode(kMCG_PllClkSelPll0, &g_pllConfig);
assert(kMCG_ModePBE == CLOCK_GetMode());
/* Change PBE -> PEE */
CLOCK_SetPeeMode();
assert(kMCG_ModePEE == CLOCK_GetMode());
}
/*!
* @brief Example function to show how to change from BLPE to FEE mode.
* MCG transition: BLPE -> FBE -> FEE
*/
void APP_ChangeBlpeToFeeExample(void)
{
/* Change BLPE -> FBE */
CLOCK_SetLowPowerEnable(false);
assert(kMCG_ModeFBE == CLOCK_GetMode());
/* Change FBE -> FEE */
CLOCK_SetFeeMode(g_frdivValue, kMCG_Dmx32Default, kMCG_DrsLow, APP_FllStableDelay);
assert(kMCG_ModeFEE == CLOCK_GetMode());
}
/*!
* @brief Example function to show how to change from PEE to BLPE mode.
* MCG transition: PEE -> FBE -> BLPE
*/
void APP_ChangePeeToBlpeExample(void)
{
/* Quick change PEE -> FBE */
CLOCK_ExternalModeToFbeModeQuick();
assert(kMCG_ModeFBE == CLOCK_GetMode());
/* Change FBE -> BLPE */
CLOCK_SetLowPowerEnable(true);
assert(kMCG_ModeBLPE == CLOCK_GetMode());
}
/*!
* @brief Example function to show how to change from FEE to BLPE mode.
* MCG transition: FEE -> FBE -> BLPE
*/
void APP_ChangeFeeToBlpeExample(void)
{
/* Change FEE -> FBE
* It's transitional mode, don't need to wait for FLL stable,
* so NULL is passed as variable here.
*/
CLOCK_SetFbeMode(g_frdivValue, kMCG_Dmx32Default, kMCG_DrsLow, NULL);
assert(kMCG_ModeFBE == CLOCK_GetMode());
/* Change FBE -> BLPE */
CLOCK_SetLowPowerEnable(true);
assert(kMCG_ModeBLPE == CLOCK_GetMode());
}
/*!
* @brief Example function to show how to change from FEE to BLPI mode.
* MCG transition: FEE -> FBI -> BLPI
*/
void APP_ChangeFeeToBlpiExample(void)
{
/* Change FEE -> FBI
* It's transitional mode, don't need to wait for FLL stable,
* so NULL is passed as variable here.
*/
CLOCK_SetFbiMode(kMCG_DrsLow, NULL);
assert(kMCG_ModeFBI == CLOCK_GetMode());
/* Change FBI -> BLPI */
CLOCK_SetLowPowerEnable(true);
assert(kMCG_ModeBLPI == CLOCK_GetMode());
}
void hal_deepsleep(void)
{
#if (defined(FSL_FEATURE_SOC_MCG_COUNT) && FSL_FEATURE_SOC_MCG_COUNT)
#if (defined(FSL_FEATURE_MCG_HAS_PLL) && FSL_FEATURE_MCG_HAS_PLL)
mcg_mode_t mode = CLOCK_GetMode();
#endif // FSL_FEATURE_MCG_HAS_PLL
#endif // FSL_FEATURE_SOC_MCG_COUNT
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
PreEnterStopModes();
SMC_SetPowerModeVlps(SMC);
PostExitStopModes();
#if (defined(FSL_FEATURE_SOC_MCG_COUNT) && FSL_FEATURE_SOC_MCG_COUNT)
#if (defined(FSL_FEATURE_MCG_HAS_PLL) && FSL_FEATURE_MCG_HAS_PLL)
/*
* If enter stop modes when MCG in PEE mode, then after wakeup, the MCG is in PBE mode,
* need to enter PEE mode manually.
*/
if (mode == kMCG_ModePEE) {
BOARD_BootClockRUN();
}
#endif // FSL_FEATURE_MCG_HAS_PLL
#endif // FSL_FEATURE_SOC_MCG_COUNT
}
status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
uint8_t mcg_c4;
bool change_drs = false;
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
mcg_mode_t mode = CLOCK_GetMode();
if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode)))
{
return kStatus_MCG_ModeUnreachable;
}
#endif
mcg_c4 = MCG->C4;
/*
Errata: ERR007993
Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
reference clock source changes, then reset to previous value after
reference clock changes.
*/
if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL)
{
change_drs = true;
/* Change the LSB of DRST_DRS. */
MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
}
/* Set CLKS and IREFS. */
MCG->C1 =
((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
| MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */
/* Wait and check status. */
while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
{
}
/* Errata: ERR007993 */
if (change_drs)
{
MCG->C4 = mcg_c4;
}
/* In FEI mode, the MCG_C4[DMX32] is set to 0U. */
MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs));
/* Check MCG_S[CLKST] */
while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL)
{
}
/* Wait for FLL stable time. */
if (fllStableDelay)
{
fllStableDelay();
}
return kStatus_Success;
}
/*!
* @brief Example function to show how to change from PEE to BLPI mode.
* MCG transition: BLPI -> FBI -> FBE -> PBE -> PEE
*/
void APP_ChangeBlpiToPeeExample(void)
{
/* Change BLPI -> FBI */
CLOCK_SetLowPowerEnable(false);
assert(kMCG_ModeFBI == CLOCK_GetMode());
/* Change FBI -> FBE
* It's transitional mode, don't need to wait for FLL stable
* so NULL is passed as variable here.
*/
CLOCK_SetFbeMode(g_frdivValue, kMCG_Dmx32Default, kMCG_DrsLow, NULL);
assert(kMCG_ModeFBE == CLOCK_GetMode());
/* Change FBE -> PBE */
CLOCK_SetPbeMode(kMCG_PllClkSelPll0, &g_pllConfig);
assert(kMCG_ModePBE == CLOCK_GetMode());
/* Change PBE -> PEE */
CLOCK_SetPeeMode();
assert(kMCG_ModePEE == CLOCK_GetMode());
}
status_t CLOCK_SetPeeMode(void)
{
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
mcg_mode_t mode = CLOCK_GetMode();
if (kMCG_ModePBE != mode)
{
return kStatus_MCG_ModeUnreachable;
}
#endif
/* Change to use PLL/FLL output clock first. */
MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut);
/* Wait for clock status bits to update */
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
{
}
return kStatus_Success;
}
status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
{
mcg_mode_t next_mode;
status_t status = kStatus_Success;
mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0;
/* If need to change external clock, MCG_C7[OSCSEL]. */
if (MCG_C7_OSCSEL_VAL != config->oscsel)
{
/* If external clock is in use, change to FEI first. */
if (!(MCG->S & MCG_S_IRCST_MASK))
{
CLOCK_ExternalModeToFbeModeQuick();
CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0);
}
CLOCK_SetExternalRefClkConfig(config->oscsel);
}
/* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt)
{
MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
{
CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
}
}
/* Configure MCGIRCLK. */
CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv);
next_mode = CLOCK_GetMode();
do
{
next_mode = mcgModeMatrix[next_mode][config->mcgMode];
switch (next_mode)
{
case kMCG_ModeFEI:
status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
break;
case kMCG_ModeFEE:
status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
break;
case kMCG_ModeFBI:
status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0);
break;
case kMCG_ModeFBE:
status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0);
break;
case kMCG_ModeBLPI:
status = CLOCK_SetBlpiMode();
break;
case kMCG_ModeBLPE:
status = CLOCK_SetBlpeMode();
break;
case kMCG_ModePBE:
/* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */
if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode))
{
{
status = CLOCK_SetPbeMode(pllcs, &config->pll0Config);
}
}
else
{
MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
{
}
}
break;
case kMCG_ModePEE:
status = CLOCK_SetPeeMode();
break;
default:
break;
}
if (kStatus_Success != status)
{
return status;
}
} while (next_mode != config->mcgMode);
if (config->pll0Config.enableMode & kMCG_PllEnableIndependent)
{
CLOCK_EnablePll0(&config->pll0Config);
}
else
{
MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent;
}
return kStatus_Success;
}
status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void))
{
uint8_t mcg_c4;
bool change_drs = false;
#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM)
mcg_mode_t mode = CLOCK_GetMode();
if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) ||
(kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode)))
{
return kStatus_MCG_ModeUnreachable;
}
#endif
/* Change to FLL mode. */
MCG->C6 &= ~MCG_C6_PLLS_MASK;
while (MCG->S & MCG_S_PLLST_MASK)
{
}
/* Set LP bit to enable the FLL */
MCG->C2 &= ~MCG_C2_LP_MASK;
mcg_c4 = MCG->C4;
/*
Errata: ERR007993
Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before
reference clock source changes, then reset to previous value after
reference clock changes.
*/
if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL)
{
change_drs = true;
/* Change the LSB of DRST_DRS. */
MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT);
}
/* Set CLKS and IREFS. */
MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
(MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
| MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
/* Wait for Reference clock Status bit to clear */
while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL)
{
}
/* Errata: ERR007993 */
if (change_drs)
{
MCG->C4 = mcg_c4;
}
/* Set DRST_DRS and DMX32. */
mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)));
/* Wait for clock status bits to show clock source is ext ref clk */
while (kMCG_ClkOutStatExt != MCG_S_CLKST_VAL)
{
}
/* Wait for fll stable time. */
if (fllStableDelay)
{
fllStableDelay();
}
return kStatus_Success;
}
void APP_BootToFeeExample(void)
{
/* Boot to Fee mode */
CLOCK_BootToFeeMode(kMCG_OscselOsc, g_frdivValue, kMCG_Dmx32Default, kMCG_DrsLow, APP_FllStableDelay);
assert(kMCG_ModeFEE == CLOCK_GetMode());
}
void APP_BootToPeeExample(void)
{
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &g_pllConfig);
assert(kMCG_ModePEE == CLOCK_GetMode());
}
status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
{
mcg_mode_t next_mode;
status_t status = kStatus_Success;
/* If need to change external clock, MCG_C7[OSCSEL]. */
if (MCG_C7_OSCSEL_VAL != config->oscsel)
{
/* If external clock is in use, change to FEI first. */
if (!(MCG->S & MCG_S_IRCST_MASK))
{
CLOCK_ExternalModeToFbeModeQuick();
CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0);
}
CLOCK_SetExternalRefClkConfig(config->oscsel);
}
/* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt)
{
MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
{
CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
}
}
/* Configure MCGIRCLK. */
CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv);
next_mode = CLOCK_GetMode();
do
{
next_mode = mcgModeMatrix[next_mode][config->mcgMode];
switch (next_mode)
{
case kMCG_ModeFEI:
status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay);
break;
case kMCG_ModeFEE:
status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay);
break;
case kMCG_ModeFBI:
status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0);
break;
case kMCG_ModeFBE:
status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0);
break;
case kMCG_ModeBLPI:
status = CLOCK_SetBlpiMode();
break;
case kMCG_ModeBLPE:
status = CLOCK_SetBlpeMode();
break;
default:
break;
}
if (kStatus_Success != status)
{
return status;
}
} while (next_mode != config->mcgMode);
return kStatus_Success;
}
