/** * Read a PCIe config space register indirectly. This is used for * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???. * * @pcie_port: PCIe port to read from * @cfg_offset: Address to read * * Returns Value read */ static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset) { union cvmx_pescx_cfg_rd pescx_cfg_rd; pescx_cfg_rd.u64 = 0; pescx_cfg_rd.s.addr = cfg_offset; cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64); pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port)); return pescx_cfg_rd.s.data; }
/** * Read a PCIe config space register indirectly. This is used for * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???. * * @pcie_port: PCIe port to read from * @cfg_offset: Address to read * * Returns Value read */ static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset) { if (octeon_has_feature(OCTEON_FEATURE_NPEI)) { union cvmx_pescx_cfg_rd pescx_cfg_rd; pescx_cfg_rd.u64 = 0; pescx_cfg_rd.s.addr = cfg_offset; cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64); pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port)); return pescx_cfg_rd.s.data; } else { union cvmx_pemx_cfg_rd pemx_cfg_rd; pemx_cfg_rd.u64 = 0; pemx_cfg_rd.s.addr = cfg_offset; cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64); pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port)); return pemx_cfg_rd.s.data; } }