static void CYCONFIGCPYCODE8(void *dest, const void *src, uint32 count)
{
CYCONFIGCPY8(dest, src, count);
}
void cyfitter_cfg(void)
{
#ifdef CYGlobalIntDisable
/* Disable interrupts by default. Let user enable if/when they want. */
CYGlobalIntDisable
#endif
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x00u : 0x01u));
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Set Flash Cycles based on newly configured 24.00MHz Bus Clock. */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x80u : 0x81u));
/* Disable DMA channels so they can be configured for chip initialization */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_PHUB_CH0_BASIC_CFG), 0x00u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_PHUB_CH1_BASIC_CFG), 0x00u);
/* Enable analog pulldown switches */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_ANAIF_CFG_MISC_CR0), 0x01u);
/* Enable/Disable Debug functionality based on settings from System DWR */
CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DBG_DBE, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DBG_DBE) | 0x01u));
{
typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYREG_I2C_XCFG), 20u},
{(void CYFAR *)(CYREG_PRT0_DR), 16u},
{(void CYFAR *)(CYREG_PRT4_DR), 48u},
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT0_BASE), 7u);
CYCONFIGCPY8((void CYFAR *)(CYDEV_PRTDSI_PRT1_BASE), (const void CYFAR *)(BS_IOPORT_1_VAL), 7u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT2_BASE), 7u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT3_BASE), 7u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT4_BASE), 7u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT5_BASE), 7u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT6_BASE), 7u);
CYCONFIGCPY8((void CYFAR *)(CYDEV_PRTDSI_PRT12_BASE), (const void CYFAR *)(BS_IOPORT_7_VAL), 6u);
CYMEMZERO8((void CYFAR *)(CYDEV_PRTDSI_PRT15_BASE), 7u);
/* Enable digital routing */
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
CYCONFIGCPY8((void CYFAR *)(CYREG_PRT12_DR), (const void CYFAR *)(BS_IOPINS0_7_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT15_DR), (const void CYFAR *)(BS_IOPINS0_8_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT1_DR), (const void CYFAR *)(BS_IOPINS0_1_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DR), (const void CYFAR *)(BS_IOPINS0_2_VAL), 10u);
CYCONFIGCPY((void CYFAR *)(CYREG_PRT3_DR), (const void CYFAR *)(BS_IOPINS0_3_VAL), 10u);
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
/* Configure alternate active mode */
CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 12u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_STBY_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_STBY_CFG0) & (uint8)~0x02u); /* Disable CPU */
}
