Пример #1
0
#include CYGHWR_MEMORY_LAYOUT_H

// Functions defined in this module
void _csb281_fs6377_init(int mode);
static void _csb281_i2c_init(void);

// The memory map is weakly defined, allowing the application to redefine
// it if necessary. The regions defined below are the minimum requirements.
CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
    // Mapping for the Cogent CSB281 development boards
    CYGARC_MEMDESC_NOCACHE( 0x70000000, 0x10000000 ), // FLASH region, LCD, PS/2
    CYGARC_MEMDESC_NOCACHE( 0xf0000000, 0x10000000 ), // PCI space, LEDS, control
    CYGARC_MEMDESC_CACHE(   CYGMEM_REGION_ram, CYGMEM_REGION_ram_SIZE ), // Main memory
// Main memory, mapped non-cacheable for PCI use
    CYGARC_MEMDESC_NOCACHE_PA(CYGMEM_SECTION_pci_window, 
                              CYGARC_PHYSICAL_ADDRESS(CYGMEM_SECTION_pci_window), 
                              CYGMEM_SECTION_pci_window_SIZE),

    CYGARC_MEMDESC_TABLE_END
};

//--------------------------------------------------------------------------
// Platform init code.
void
hal_platform_init(void)
{
    cyg_uint32 bcsr, gcr, frr, eicr, iack;
    int vec;

    // Initialize I/O interfaces
    hal_if_init();
Пример #2
0
#define XINTC_PPC_ALL       0xFFFFFFFF
#define XINTC_PPC_ISR       (UPBHWR_INTC_0_BASEADDR + XIN_ISR_OFFSET) // Status       
#define XINTC_PPC_IPR       (UPBHWR_INTC_0_BASEADDR + XIN_IPR_OFFSET) // Pending
#define XINTC_PPC_IER       (UPBHWR_INTC_0_BASEADDR + XIN_IER_OFFSET) // Enable
#define XINTC_PPC_IAR       (UPBHWR_INTC_0_BASEADDR + XIN_IAR_OFFSET) // Acknowledge
#define XINTC_PPC_SIE       (UPBHWR_INTC_0_BASEADDR + XIN_SIE_OFFSET) // Set
#define XINTC_PPC_CIE       (UPBHWR_INTC_0_BASEADDR + XIN_CIE_OFFSET) // Clear
#define XINTC_PPC_IVR       (UPBHWR_INTC_0_BASEADDR + XIN_IVR_OFFSET) // Interrupt Vector Register */       
#define XINTC_PPC_MER       (UPBHWR_INTC_0_BASEADDR + XIN_MER_OFFSET) // Master Enable
//-----------------------------------------------------------------------------

// The memory map is weakly defined, allowing the application to redefine
// it if necessary. The regions defined below are the minimum requirements.
CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
    // Mapping for the Xilinx VIRTEX4 development boards
    CYGARC_MEMDESC_NOCACHE_PA( 0x80000000, 0x00000000, CYGMEM_REGION_ram_SIZE ), // Uncached version of RAM
    CYGARC_MEMDESC_CACHE(   CYGMEM_REGION_ram, CYGMEM_REGION_ram_SIZE ), // Main memory
    CYGARC_MEMDESC_TABLE_END
};

//--------------------------------------------------------------------------
// Platform init code.

void
_virtex4_assert(char *file, int line)
{
    cyg_uint32 old;

    HAL_DISABLE_INTERRUPTS(old);
    diag_printf("VIRTEX4 firmware failure - file: %s, line: %d\n",
                file, line);