/* Setup external memories */
STATIC void SystemSetupMemory(void)
{
/* Setup EMC Delays */
/* Move all clock delays together */
LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
/* Setup EMC Clock Divider for divide by 2 - this is done in both the CCU (clocking)
and CREG. For frequencies over 120MHz, a divider of 2 must be used. For frequencies
less than 120MHz, a divider of 1 or 2 is ok. */
Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
LPC_CREG->CREG6 |= (1 << 16);
/* Enable EMC clock */
Chip_Clock_Enable(CLK_MX_EMC);
/* Init EMC Controller -Enable-LE mode */
Chip_EMC_Init(1, 0);
/* Init EMC Dynamic Controller */
Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_T *) &MT48LC4M32_config);
/* Init EMC Static Controller CS0 */
Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &S29GL64N90_config);
/* Enable Buffer for External Flash */
LPC_EMC->STATICCONFIG0 |= 1 << 19;
}
// ---------------------------------------------------------------------------
// Load image on slave core
int IPC_Load(uint32_t image_addr)
{
// Make sure the alignment is OK
if (image_addr & 0xFFF) {
return -1;
}
#if 0
// Check the validity of images
if (CheckImages(image_addr, &__M4Signature) != 0) {
return -1;
}
// Make sure the M0 core is being held in reset via the RGU
Chip_RGU_TriggerReset(RGU_M0APP_RST);
Chip_Clock_Enable(CLK_M4_M0APP);
// Keep in mind the M0 image must be aligned on a 4K boundary
Chip_CREG_SetM0AppMemMap(image_addr);
Chip_RGU_ClearReset(RGU_M0APP_RST);
#endif
return 0;
}
/* Initialize the SSP */
void Chip_SSP_Init(LPC_SSP_T *pSSP)
{
Chip_Clock_Enable(Chip_SSP_GetClockIndex(pSSP));
Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
Chip_SSP_SetFormat(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0);
Chip_SSP_SetBitRate(pSSP, 100000);
}
/* Initialize for I2S */
void Chip_I2S_Init(LPC_I2S_Type *pI2S)
{
if (clksEnabled == 0) {
Chip_Clock_Enable(CLK_APB1_I2S);
}
clksEnabled++;
IP_I2S_Init(pI2S);
}
/* Initialize the High speed ADC */
void Chip_HSADC_Init(LPC_HSADC_T *pHSADC)
{
/* Enable HSADC register clock */
Chip_Clock_EnableOpts(CLK_MX_ADCHS, true, true, 1);
/* Enable HSADC sample clock */
Chip_Clock_Enable(CLK_ADCHS);
/* Reset HSADC, will auto-clear */
Chip_RGU_TriggerReset(RGU_ADCHS_RST);
}
/* Setup external memories */
STATIC void SystemSetupMemory(void)
{
/* Setup EMC Delays */
/* Move all clock delays together */
LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
/* Setup EMC Clock Divider for divide by 2 */
Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
LPC_CREG->CREG6 |= (1 << 16);
Chip_Clock_Enable(CLK_MX_EMC);
/* Init EMC Controller -Enable-LE mode- clock ratio 1:1 */
Chip_EMC_Init(1, 0, 0);
/* Init EMC Dynamic Controller */
Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_Type *) &IS42S16400_config);
/* Init EMC Static Controller CS2 */
Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &IS62WV25616_config);
/* Init EMC Static Controller CS0 */
Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_Type *) &SST39VF320_config);
/* Enable Buffer for External Flash */
LPC_EMC->STATICCONFIG0 |= 1 << 19;
}
/* M0 Boot loader */
int M0Image_Boot(uint32_t m0_image_addr)
{
/* Make sure the alignment is OK */
if (m0_image_addr & 0xFFF) {
return -1;
}
/* Check the validity of images */
if (CheckImages(m0_image_addr, &__M4Signature) != 0) {
return -1;
}
/* Make sure the M0 core is being held in reset via the RGU */
Chip_RGU_TriggerReset(RGU_M0APP_RST);
Chip_Clock_Enable(CLK_M4_M0APP);
/* Keep in mind the M0 image must be aligned on a 4K boundary */
Chip_CREG_SetM0AppMemMap(m0_image_addr);
Chip_RGU_ClearReset(RGU_M0APP_RST);
return 0;
}
/* Initialize the I2S interface */
void Chip_I2S_Init(LPC_I2S_T *pI2S)
{
Chip_Clock_Enable(CLK_APB1_I2S);
}
/* Initialize a timer */
void Chip_TIMER_Init(LPC_TIMER_T *pTMR)
{
Chip_Clock_Enable(Chip_Timer_GetClock(pTMR));
}
