/* Phy status update state machine */
uint32_t lpcPHYStsPoll(void)
{
switch (phyustate) {
default:
case 0:
/* Read BMSR to clear faults */
Chip_ENET_StartMIIRead(LPC_ETHERNET, DP8_PHY_STAT_REG);
physts &= ~PHY_LINK_CHANGED;
physts = physts | PHY_LINK_BUSY;
phyustate = 1;
break;
case 1:
/* Wait for read status state */
if (!Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
/* Update PHY status */
physts &= ~PHY_LINK_BUSY;
lpc_update_phy_sts(Chip_ENET_ReadMIIData(LPC_ETHERNET));
phyustate = 0;
}
break;
}
return physts;
}
/* Phy status update state machine */
uint32_t lpcPHYStsPoll(void)
{
static uint16_t sts;
switch (phyustate) {
default:
case 0:
/* Read BMSR to clear faults */
Chip_ENET_StartMIIRead(LPC_ETHERNET, LAN8_BSR_REG);
physts &= ~PHY_LINK_CHANGED;
physts = physts | PHY_LINK_BUSY;
phyustate = 1;
break;
case 1:
/* Wait for read status state */
if (!Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
/* Get PHY status with link state */
sts = Chip_ENET_ReadMIIData(LPC_ETHERNET);
Chip_ENET_StartMIIRead(LPC_ETHERNET, LAN8_PHYSPLCTL_REG);
phyustate = 2;
}
break;
case 2:
/* Wait for read status state */
if (!Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
/* Update PHY status */
physts &= ~PHY_LINK_BUSY;
smsc_update_phy_sts(sts, Chip_ENET_ReadMIIData(LPC_ETHERNET));
phyustate = 0;
}
break;
}
return physts;
}
/* Read from the PHY. Will block for delays based on the pDelayMs function. Returns
true on success, or false on failure */
static Status lpc_mii_read(uint8_t reg, uint16_t *data)
{
Status sts = ERROR;
int32_t mst = 250;
/* Start register read */
Chip_ENET_StartMIIRead(LPC_ETHERNET, reg);
/* Wait for unbusy status */
while (mst > 0) {
if (!Chip_ENET_IsMIIBusy(LPC_ETHERNET)) {
mst = 0;
*data = Chip_ENET_ReadMIIData(LPC_ETHERNET);
sts = SUCCESS;
}
else {
mst--;
pDelayMs(1);
}
}
return sts;
}