/* Setup system clocking */
STATIC void SystemSetupClocking(void)
{
volatile int i;
/* Powerup main oscillator */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
/* Wait 200us for OSC to be stablized, no status
indication, dummy wait. */
for (i = 0; i < 0x100; i++) {}
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
/* Set USB PLL input to main oscillator */
Chip_Clock_SetUSBPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* Setup USB PLL (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupUSBPLL(3, 1);
/* Powerup USB PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_USBPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsUSBPLLLocked()) {}
}
/* Clock and PLL initialization based on the external oscillator */
void Chip_SetupXtalClocking(void)
{
volatile int i;
#if defined(USE_ROM_API)
uint32_t cmd[4], resp[2];
#endif
/* Powerup main oscillator */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
/* Wait for at least 580uS for osc to stabilize */
for (i = 0; i < 2500; i++) {}
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* Setup FLASH access to 2 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_2CLK_CPU);
#if defined(USE_ROM_API)
/* Use ROM API for setting up PLL */
cmd[0] = Chip_Clock_GetMainOscRate() / 1000; /* in KHz */
cmd[1] = 48000000 / 1000; /* 48MHz system clock rate */
cmd[2] = CPU_FREQ_EQU;
cmd[3] = 48000000 / 10000; /* Timeout */
LPC_PWRD_API->set_pll(cmd, resp);
/* Dead loop on fail */
while (resp[0] != PLL_CMD_SUCCESS) {}
#else
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
#endif
}
/* common clock initialisation function
* This brings up enough clocks to allow the processor to run quickly while initialising memory.
* Other platform specific clock init can be done in init_platform() or init_host_mcu()
*/
WEAK void platform_init_system_clocks( void )
{
/* CPU clock source starts with IRC */
Chip_Clock_SetMainPllSource( SYSCTL_PLLCLKSRC_IRC );
Chip_Clock_SetCPUClockSource( SYSCTL_CCLKSRC_SYSCLK );
/* Enable main oscillator used for PLLs */
LPC_SYSCTL->SCS = SYSCTL_OSCEC;
while ( ( LPC_SYSCTL->SCS & SYSCTL_OSCSTAT ) == 0 )
{
}
/* PLL0 clock source is 12MHz oscillator, PLL1 can only be the
main oscillator */
Chip_Clock_SetMainPllSource( SYSCTL_PLLCLKSRC_MAINOSC );
/* Setup PLL0 for a 480MHz clock. It is divided by CPU Clock Divider to create CPU Clock.
Input clock rate (FIN) is main oscillator = 12MHz
FCCO is selected for PLL Output and it must be between 275 MHz to 550 MHz.
FCCO = (2 * M * FIN) / N = integer multiplier of CPU Clock (120MHz) = 480MHz
N = 1, M = 480 * 1/(2*12) = 20 */
Chip_Clock_SetupPLL( SYSCTL_MAIN_PLL, PLL_M_CONSTANT - 1, PLL_N_CONSTANT - 1 );/* Multiply by PLL_M_CONSTANT, Divide by PLL_N_CONSTANT */
/* Enable PLL0 */
Chip_Clock_EnablePLL( SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE );
/* Change the CPU Clock Divider setting for the operation with PLL0.
Divide value = (480/120) = 4 */
Chip_Clock_SetCPUClockDiv( 3 ); /* pre-minus 1 */
while ( !Chip_Clock_IsMainPLLLocked( ) )
{
}
/* Connect PLL0 */
Chip_Clock_EnablePLL( SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE | SYSCTL_PLL_CONNECT );
/* Wait for PLL0 to be connected */
while ( !Chip_Clock_IsMainPLLConnected( ) )
{
}
/* Setup FLASH access to 5 clocks (120MHz clock) */
Chip_FMC_SetFLASHAccess( FLASHTIM_120MHZ_CPU );
/* Enable peripheral base clocks*/
Chip_Clock_SetPCLKDiv( SYSCTL_PCLK_SPI, SYSCTL_CLKDIV_1 );
Chip_RTC_Enable( LPC_RTC, ENABLE );
Chip_Clock_SetCLKOUTSource( SYSCTL_CLKOUTSRC_RTC, 1 );
Chip_Clock_EnableCLKOUT( );
}
STATIC void Board_SetupIRCClocking(void)
{
/* Wait State setting TBD */
/* Setup FLASH access to 2 clocks (up to 20MHz) */
Chip_FMC_SetFLASHAccess(FLASHTIM_20MHZ_CPU);
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Set main clock source to the system PLL. This will drive 24MHz
for the main clock and 24MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_IRC);
}
/* Set up and initialize hardware prior to call to main */
void Chip_SystemInit(void)
{
#ifdef SUPPORT_NXP_MAIN_OSC
volatile uint32_t i;
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSOSC_PD);
Chip_Clock_SetPLLBypass(0, 0);
for (i = 0; i < 200; i++) __NOP();
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
#else
/* IRC should be powered up */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRCOUT_PD);
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
#endif
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
#ifdef SUPPORT_NXP_MAIN_OSC
Chip_Clock_SetupSystemPLL(3, 2);
#else
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
#endif
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
/* Enable IOCON clock */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
}
/* Clock and PLL initialization based on the internal oscillator */
void Chip_SetupIrcClocking(void)
{
#if defined(USE_ROM_API)
uint32_t cmd[4], resp[2];
#endif
/* Turn on the IRC by clearing the power down bit */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
/* Select the PLL input in the IRC */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* Setup FLASH access */
Chip_FMC_SetFLASHAccess(FLASHTIM_2CLK_CPU);
#if defined(USE_ROM_API)
/* Use ROM API for setting up PLL */
cmd[0] = Chip_Clock_GetIntOscRate() / 1000; /* in KHz */
cmd[1] = 48000000 / 1000; /* 48MHz system clock rate */
cmd[2] = CPU_FREQ_EQU;
cmd[3] = 48000000 / 10000; /* Timeout */
LPC_PWRD_API->set_pll(cmd, resp);
/* Dead loop on fail */
while (resp[0] != PLL_CMD_SUCCESS) {}
#else
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Configure the PLL M and P dividers */
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Turn on the PLL by clearing the power down bit */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Set main clock source to the system PLL. This will drive 24MHz
for the main clock and 24MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
#endif
}
/* Clock and PLL initialization based on the internal oscillator */
void Chip_SetupIrcClocking(void)
{
volatile int i;
/* Powerup main IRC (likely already powered up) */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRCOUT_PD);
/* Set system PLL input to IRC */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 6 = 72MHz
MSEL = 5 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 6 = 72MHz
FCCO = FCLKOUT * 2 * P = 72MHz * 2 * 2 = 288MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(5, 2);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access timing for 72MHz */
Chip_FMC_SetFLASHAccess(SYSCTL_FLASHTIM_72MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 72MHz
for the main clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_SYSPLLOUT);
}
