/* Setup (common) HSADC power and speed settings */
void Chip_HSADC_SetPowerSpeed(LPC_HSADC_T *pHSADC, bool comp2)
{
uint32_t rate, val, orBits;
int i, idx;
/* Get current clock rate for HSADC */
rate = Chip_HSADC_GetBaseClockRate(pHSADC);
/* Determine optimal CRS and DCEG settings based on clock rate */
idx = 0;
while (rate > powerSets[idx].minRate) {
idx++;
}
/* Add CRS selection based on clock speed */
orBits = powerSets[idx].crs;
/* Enable 2's complement data format? */
if (comp2) {
orBits |= (1 << 16);
}
/* Update DCEG settings for all channels based on current CRS */
for (i = 0; i < 6; i++) {
Chip_HSADC_SetSpeed(pHSADC, i, powerSets[idx].dgec);
}
/* Get current power control register value and mask off bits that
may change */
val = pHSADC->POWER_CONTROL & ~((1 << 16) | 0xF);
/* Update with new power and data format settings */
pHSADC->POWER_CONTROL = val | orBits;
}
void adc_g_v_Init(void) {
clock_g_vInit();
// clock_g_vSetupAdchsClock(HSADC_CLOCK_RATE);
uint32_t fg_ui32FreqHSADC =0;
fg_ui32FreqHSADC = Chip_Clock_GetRate(CLK_MX_TIMER1);
//clock_g_vSetupAdchsClock(HSADC_CLOCK_RATE);
//Chip_USB0_Init(); /* Initialize the USB0 PLL to 480 MHz */
// Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 2); /* Source DIV_A from USB0PLL, and set divider to 2 (Max div value supported is 4) [IN 480 MHz; OUT 240 MHz */
// Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IDIVA, 3); /* Source DIV_B from DIV_A, [IN 240 MHz; OUT 80 MHz */
// Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVB, true, false); /* Source ADHCS base clock from DIV_B */
// Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 3); /* Setup divider A for main PLL rate divided by 3 */
// Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVA, true, false); /* HSADC base clock = divider A input */
// Chip_Clock_EnableOpts(CLK_ADCHS, true, true, 1); /* Enable the clock */
/* Initialize HSADC */
Chip_HSADC_Init(LPC_ADCHS);
/* Setup FIFO trip points for interrupt/DMA to 16 samples, no packing */
Chip_HSADC_SetupFIFO(LPC_ADCHS, 8, false);
fg_ui32FreqHSADC = Chip_HSADC_GetBaseClockRate(LPC_ADCHS);
/* Software trigger only, 0x90 recovery clocks, add channel IF to FIFO entry */
Chip_HSADC_ConfigureTrigger(LPC_ADCHS, HSADC_CONFIG_TRIGGER_SW,
HSADC_CONFIG_TRIGGER_RISEEXT, HSADC_CONFIG_TRIGGER_NOEXTSYNC,
HSADC_CHANNEL_ID_EN_NONE, 0x90);
/* Select both positive and negative DC biasing for input 3 */
//Chip_HSADC_SetACDCBias(LPC_ADCHS, 3, HSADC_CHANNEL_DCBIAS, HSADC_CHANNEL_DCBIAS);
Chip_HSADC_SetACDCBias(LPC_ADCHS, 0, HSADC_CHANNEL_DCBIAS,
HSADC_CHANNEL_DCBIAS);
Chip_HSADC_SetACDCBias(LPC_ADCHS, 1, HSADC_CHANNEL_DCBIAS,
HSADC_CHANNEL_DCBIAS);
/* Setup data format for 2's complement and update clock settings. This function
should be called whenever a clock change is made to the HSADC */
Chip_HSADC_SetPowerSpeed(LPC_ADCHS, false);
/* Enable HSADC power */
Chip_HSADC_EnablePower(LPC_ADCHS);
/* Update Descriptor Table for use with channel 0 and 1 in loop*/
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 0, (HSADC_DESC_CH(0) |
HSADC_DESC_BRANCH_FIRST| /*HSADC_DESC_MATCH(1)*/ HSADC_DESC_MATCH(ADC_DEF_CLK_DIV) | HSADC_DESC_THRESH_NONE |
HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 1, (HSADC_DESC_CH(5) |
HSADC_DESC_BRANCH_FIRST| HSADC_DESC_HALT | HSADC_DESC_MATCH(1) | HSADC_DESC_THRESH_NONE|
HSADC_DESC_RESET_TIMER));
/* Update descriptor tables - needed after updating any descriptors */
Chip_HSADC_UpdateDescTable(LPC_ADCHS, 0);
Chip_HSADC_UpdateDescTable(LPC_ADCHS, 1);
}
