CY_CFG_SECTION
static void ClockSetup(void)
{
/* Enable HALF_EN before trimming for the flash accelerator. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));
/* Trim IMO BG based on desired frequency. */
SetIMOBGTrims(24u);
/* Going less than or equal to 24MHz, so update the clock speed then adjust trim value. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM2), (25u));
CyDelayCycles(5u);
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM1), (CY_GET_REG8((void *)CYREG_SFLASH_IMO_TRIM21)));
CyDelayUs(5u);
/* Disable HALF_EN since it is not required at this IMO frequency. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu));
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT12), 0x00000010u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000033u);
}
static void ClockSetup(void)
{
/* Configure ILO based on settings from Clock DWR */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x02u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_CR), 0x08u);
/* Configure IMO based on settings from Clock DWR */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x03u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)));
/* Configure PLL based on settings from Clock DWR */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0008u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1051u);
/* Wait 250us for the PLL to lock */
CyDelayCycles(250u * 12u); /* Delay 250us based on 12MHz clock */
/* Configure Bus/Master Clock based on settings from Clock DWR */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x03u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR1), 0x01u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);
}
/*******************************************************************************
* Function Name: CySysPmFreezeIo
********************************************************************************
*
* Summary:
* Freezes IO-Cells directly to save IO-Cell state on wake up from Hibernate or
* Stop state. It is not required to call this function before entering
* Stop mode, since CySysPmStop() function freezes IO-Cells implicitly.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CySysPmFreezeIo(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
/* Check FREEZE state to avoid recurrent IO-Cells freeze attempt,
* since the second call to this function will cause accidental switch
* to the STOP mode (the system will enter STOP mode immediately after
* writing to STOP bit since both UNLOCK and FREEZE have been set correctly
* in a previous call to this function).
*/
if (0u == (CY_PM_PWR_STOP_REG & CY_PM_PWR_STOP_FREEZE))
{
/* Preserve last reset reason and disable overrides the next freeze command by peripherals */
CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_STOP | CY_PM_PWR_STOP_FREEZE | CY_PM_PWR_STOP_UNLOCK |
(CY_PM_PWR_STOP_REG & (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY));
/* PWR_STOP read after write must be delayed for 6 clock cycles to let internal nodes to settle */
CyDelayCycles(6u);
/* The second write causes the freeze of IO-Cells to save IO-Cell state */
CY_PM_PWR_STOP_REG &= ~CY_PM_PWR_STOP_STOP;
}
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: USBUART_Resume
********************************************************************************
*
* Summary:
* This function enables the USBFS block after power down mode.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* USBUART_backup - checked.
*
* Reentrant:
* No.
*
*******************************************************************************/
void USBUART_Resume(void)
{
uint8 enableInterrupts;
enableInterrupts = CyEnterCriticalSection();
if(USBUART_backup.enableState != 0u)
{
#if(USBUART_DP_ISR_REMOVE == 0u)
CyIntDisable(USBUART_DP_INTC_VECT_NUM);
#endif /* USBUART_DP_ISR_REMOVE */
/* Enable USB block */
USBUART_PM_ACT_CFG_REG |= USBUART_PM_ACT_EN_FSUSB;
/* Enable USB block for Standby Power Mode */
USBUART_PM_STBY_CFG_REG |= USBUART_PM_STBY_EN_FSUSB;
/* Enable core clock */
USBUART_USB_CLK_EN_REG |= USBUART_USB_CLK_ENABLE;
/* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/
USBUART_PM_USB_CR0_REG |= USBUART_PM_USB_CR0_REF_EN;
/* The reference will be available ~40us after power restored */
CyDelayUs(40u);
/* Return VRegulator*/
USBUART_CR1_REG |= USBUART_backup.mode;
CyDelayUs(0u); /*~50ns delay */
/* Enable USBIO */
USBUART_PM_USB_CR0_REG |= USBUART_PM_USB_CR0_PD_N;
CyDelayUs(2u);
/* Set the USBIO pull-up enable */
USBUART_PM_USB_CR0_REG |= USBUART_PM_USB_CR0_PD_PULLUP_N;
/* Re-init Arbiter configuration for DMA transfers */
#if(USBUART_EP_MM != USBUART__EP_MANUAL)
/* Usb arb interrupt enable */
USBUART_ARB_INT_EN_REG = USBUART_ARB_INT_MASK;
#if(USBUART_EP_MM == USBUART__EP_DMAMANUAL)
USBUART_ARB_CFG_REG = USBUART_ARB_CFG_MANUAL_DMA;
#endif /* USBUART_EP_MM == USBUART__EP_DMAMANUAL */
#if(USBUART_EP_MM == USBUART__EP_DMAAUTO)
/*Set cfg cmplt this rises DMA request when the full configuration is done */
USBUART_ARB_CFG_REG = USBUART_ARB_CFG_AUTO_DMA | USBUART_ARB_CFG_AUTO_MEM;
#endif /* USBUART_EP_MM == USBUART__EP_DMAAUTO */
#endif /* USBUART_EP_MM != USBUART__EP_MANUAL */
/* STALL_IN_OUT */
CY_SET_REG8(USBUART_EP0_CR_PTR, USBUART_MODE_STALL_IN_OUT);
/* Enable the SIE with a last address */
USBUART_CR0_REG |= USBUART_CR0_ENABLE;
CyDelayCycles(1u);
/* Finally, Enable d+ pullup and select iomode to USB mode*/
CY_SET_REG8(USBUART_USBIO_CR1_PTR, USBUART_USBIO_CR1_USBPUEN);
/* Restore USB register settings */
USBUART_RestoreConfig();
}
CyExitCriticalSection(enableInterrupts);
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
/* Start the WCO */
CySysClkWcoStart();
CyDelayCycles(12000000u); /* WCO may take up to 500ms to start */
(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM); /* Switch to the low power mode */
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(48u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
/* Enable fast start mode for XO */
CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
/*Set XTAL(ECO) divider*/
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG), 0x00000000u);
/* Disable Crystal Stable Interrupt before enabling ECO */
CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
/* Start the ECO and do not check status since it is not needed for HFCLK */
(void)CySysClkEcoStart(2000u);
CyDelayUs(1500u); /* Wait to stabalize */
/* Setup phase aligned clocks */
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00BB7F00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x0001A000u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);
/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000041u);
/* CYDEV_PERI_PCLK_CTL2 Starting address: CYDEV_PERI_PCLK_CTL2 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL2), 0x00000040u);
(void)CyIntSetVector(8u, &CySysWdtIsr);
CyIntEnable(8u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_MATCH), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000005u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000008u);
while ((CY_GET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL)) & 0x00000008u) != 0u) { }
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000001u);
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
/* Trim IMO BG based on desired frequency. */
SetIMOBGTrims(12u);
/* Going less than or equal to 24MHz, so update the clock speed then adjust trim value. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM2), (12u));
CyDelayCycles(5u);
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM1), (CY_GET_REG8((void *)CYREG_SFLASH_IMO_TRIM09)));
CyDelayUs(5u);
/* Start the WCO */
CySysClkWcoStart();
CyDelay(500u); /* WCO may take up to 500ms to start */
(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM); /* Switch to the low power mode */
/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00002D6Au);
/* Disable Crystal Stable Interrupt before enabling ECO */
CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
/* Start the ECO and do not check status since it is not needed for HFCLK */
(void)CySysClkEcoStart(2000u);
CyDelayUs(1500u); /* Wait to stabalize */
/* Setup phase aligned clocks */
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL02, 0x00000B00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF42u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL00, 0x0000FE00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL01, 0x0000FE00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_PERI_PCLK_CTL11 Starting address: CYDEV_PERI_PCLK_CTL11 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL11), 0x00000042u);
/* CYDEV_PERI_PCLK_CTL05 Starting address: CYDEV_PERI_PCLK_CTL05 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL05), 0x00000040u);
/* CYDEV_PERI_PCLK_CTL04 Starting address: CYDEV_PERI_PCLK_CTL04 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL04), 0x00000041u);
/* Set Flash Cycles based on newly configured 12.00MHz HFCLK. */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0000u));
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
/* Start the WCO */
CySysClkWcoStart();
CyDelayCycles(12000000u); /* WCO may take up to 500ms to start */
(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM); /* Switch to the low power mode */
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(12u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
/* Enable fast start mode for XO */
CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00002D6Au);
/* Disable Crystal Stable Interrupt before enabling ECO */
CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
/* Start the ECO and do not check status since it is not needed for HFCLK */
(void)CySysClkEcoStart(2000u);
CyDelayUs(1500u); /* Wait to stabalize */
/* Setup phase aligned clocks */
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00000300u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0xA6000000u);
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00000000u);
/* CYDEV_PERI_PCLK_CTL6 Starting address: CYDEV_PERI_PCLK_CTL6 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL6), 0x00000040u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
/* Set Flash Cycles based on newly configured 12.00MHz HFCLK. */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0000u));
}
/*******************************************************************************
* Function Name: CySysPmUnfreezeIo
********************************************************************************
*
* Summary:
* The IO-Cells remain frozen after awake from Hibernate or Stop mode until
* the firmware unfreezes them after booting. The call of this function
* unfreezes IO-Cells explicitly.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CySysPmUnfreezeIo(void)
{
uint8 interruptState;
interruptState = CyEnterCriticalSection();
/* Preserve last reset reason and wakeup polarity. Then, unfreeze I/O:
* write PWR_STOP.FREEZE=0, .UNLOCK=0x3A, .STOP=0, .TOKEN
*/
CY_PM_PWR_STOP_REG = CY_PM_PWR_STOP_UNLOCK |
(CY_PM_PWR_STOP_REG & (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY));
/* PWR_STOP read after write must be delayed for 6 clock cycles to let internal nodes to settle */
CyDelayCycles(6u);
/* Lock STOP mode: write PWR_STOP.FREEZE=0, UNLOCK=0x00, STOP=0, .TOKEN */
CY_PM_PWR_STOP_REG &= (CY_PM_PWR_STOP_TOKEN_MASK | CY_PM_PWR_STOP_POLARITY);
CyExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: EzI2C_Stop
********************************************************************************
*
* Summary:
* Disables I2C hardware and component interrupt. The I2C bus is released if it
* was locked up by the component.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void EzI2C_Stop(void)
{
uint8 intState;
uint16 blockResetCycles;
EzI2C_DisableInt();
/* Store registers effected by block disable */
EzI2C_backup.adr = EzI2C_ADDR_REG;
EzI2C_backup.clkDiv1 = EzI2C_CLKDIV1_REG;
EzI2C_backup.clkDiv2 = EzI2C_CLKDIV2_REG;
/* Calculate number of cycles to reset block */
blockResetCycles = ((uint16) ((uint16) EzI2C_CLKDIV2_REG << 8u) | EzI2C_CLKDIV1_REG) + 1u;
/* Disable block */
EzI2C_CFG_REG &= (uint8) ~EzI2C_CFG_EN_SLAVE;
/* Wait for block reset before disable power */
CyDelayCycles((uint32) blockResetCycles);
/* Disable power to block */
intState = CyEnterCriticalSection();
EzI2C_PM_ACT_CFG_REG &= (uint8) ~EzI2C_ACT_PWR_EN;
EzI2C_PM_STBY_CFG_REG &= (uint8) ~EzI2C_STBY_PWR_EN;
CyExitCriticalSection(intState);
/* Enable block */
EzI2C_CFG_REG |= (uint8) EzI2C_CFG_EN_SLAVE;
/* Restore registers effected by block disable. Ticket ID#198004 */
EzI2C_ADDR_REG = EzI2C_backup.adr;
EzI2C_ADDR_REG = EzI2C_backup.adr;
EzI2C_CLKDIV1_REG = EzI2C_backup.clkDiv1;
EzI2C_CLKDIV2_REG = EzI2C_backup.clkDiv2;
EzI2C_ClearPendingInt();
/* Reset state and status to default */
EzI2C_curState = EzI2C_SM_IDLE;
EzI2C_curStatus = 0u;
}
/*******************************************************************************
* Function Name: I2C_Stop
********************************************************************************
*
* Summary:
* Disables I2C hardware and disables I2C interrupt. Disables Active mode power
* template bits or clock gating as appropriate.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void I2C_Stop(void)
{
I2C_DisableInt();
#if (I2C_TIMEOUT_ENABLED)
I2C_TimeoutStop();
#endif /* End (I2C_TIMEOUT_ENABLED) */
#if (I2C_FF_IMPLEMENTED)
{
uint8 intState;
uint16 blockResetCycles;
/* Store registers effected by block disable */
I2C_backup.addr = I2C_ADDR_REG;
I2C_backup.clkDiv1 = I2C_CLKDIV1_REG;
I2C_backup.clkDiv2 = I2C_CLKDIV2_REG;
/* Calculate number of cycles to reset block */
blockResetCycles = ((uint16) ((uint16) I2C_CLKDIV2_REG << 8u) | I2C_CLKDIV1_REG) + 1u;
/* Disable block */
I2C_CFG_REG &= (uint8) ~I2C_CFG_EN_SLAVE;
/* Wait for block reset before disable power */
CyDelayCycles((uint32) blockResetCycles);
/* Disable power to block */
intState = CyEnterCriticalSection();
I2C_ACT_PWRMGR_REG &= (uint8) ~I2C_ACT_PWR_EN;
I2C_STBY_PWRMGR_REG &= (uint8) ~I2C_STBY_PWR_EN;
CyExitCriticalSection(intState);
/* Enable block */
I2C_CFG_REG |= (uint8) I2C_ENABLE_MS;
/* Restore registers effected by block disable. Ticket ID#198004 */
I2C_ADDR_REG = I2C_backup.addr;
I2C_ADDR_REG = I2C_backup.addr;
I2C_CLKDIV1_REG = I2C_backup.clkDiv1;
I2C_CLKDIV2_REG = I2C_backup.clkDiv2;
}
#else
/* Disable slave or master bits */
I2C_CFG_REG &= (uint8) ~I2C_ENABLE_MS;
#if (I2C_MODE_SLAVE_ENABLED)
{
/* Disable bit counter */
uint8 intState = CyEnterCriticalSection();
I2C_COUNTER_AUX_CTL_REG &= (uint8) ~I2C_CNT7_ENABLE;
CyExitCriticalSection(intState);
}
#endif /* (I2C_MODE_SLAVE_ENABLED) */
/* Clear interrupt source register */
(void) I2C_CSR_REG;
#endif /* (I2C_FF_IMPLEMENTED) */
/* Disable interrupt on stop (enabled by write transaction) */
I2C_DISABLE_INT_ON_STOP;
I2C_ClearPendingInt();
/* Reset FSM to default state */
I2C_state = I2C_SM_IDLE;
/* Clear busy statuses */
#if (I2C_MODE_SLAVE_ENABLED)
I2C_slStatus &= (uint8) ~(I2C_SSTAT_RD_BUSY | I2C_SSTAT_WR_BUSY);
#endif /* (I2C_MODE_SLAVE_ENABLED) */
}
/*******************************************************************************
* Function Name: USBFS_1_InitComponent
********************************************************************************
*
* Summary:
* Initialize the component, except for the HW which is done one time in
* the Start function. This function pulls up D+.
*
* Parameters:
* device: Contains the device number of the desired device descriptor.
* The device number can be found in the Device Descriptor Tab of
* "Configure" dialog, under the settings of desired Device Descriptor,
* in the "Device Number" field.
* mode: The operating voltage. This determines whether the voltage regulator
* is enabled for 5V operation or if pass through mode is used for 3.3V
* operation. Symbolic names and their associated values are given in the
* following table.
* USBFS_1_3V_OPERATION - Disable voltage regulator and pass-thru
* Vcc for pull-up
* USBFS_1_5V_OPERATION - Enable voltage regulator and use
* regulator for pull-up
* USBFS_1_DWR_VDDD_OPERATION - Enable or Disable voltage
* regulator depend on Vddd Voltage configuration in DWR.
*
* Return:
* None.
*
* Global variables:
* USBFS_1_device: Contains the device number of the desired device
* descriptor. The device number can be found in the Device Descriptor Tab
* of "Configure" dialog, under the settings of desired Device Descriptor,
* in the "Device Number" field.
* USBFS_1_transferState: This variable used by the communication
* functions to handle current transfer state. Initialized to
* TRANS_STATE_IDLE in this API.
* USBFS_1_configuration: Contains current configuration number
* which is set by the Host using SET_CONFIGURATION request.
* Initialized to zero in this API.
* USBFS_1_deviceAddress: Contains current device address. This
* variable is initialized to zero in this API. Host starts to communicate
* to device with address 0 and then set it to whatever value using
* SET_ADDRESS request.
* USBFS_1_deviceStatus: initialized to 0.
* This is two bit variable which contain power status in first bit
* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote
* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.
* USBFS_1_lastPacketSize initialized to 0;
*
* Reentrant:
* No.
*
*******************************************************************************/
void USBFS_1_InitComponent(uint8 device, uint8 mode)
{
/* Initialize _hidProtocol variable to comply with
* HID 7.2.6 Set_Protocol Request:
* "When initialized, all devices default to report protocol."
*/
#if defined(USBFS_1_ENABLE_HID_CLASS)
uint8 i;
for (i = 0u; i < USBFS_1_MAX_INTERFACES_NUMBER; i++)
{
USBFS_1_hidProtocol[i] = USBFS_1_PROTOCOL_REPORT;
}
#endif /* USBFS_1_ENABLE_HID_CLASS */
/* Enable Interrupts. */
CyIntEnable(USBFS_1_BUS_RESET_VECT_NUM);
CyIntEnable(USBFS_1_EP_0_VECT_NUM);
#if(USBFS_1_EP1_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_1_VECT_NUM);
#endif /* End USBFS_1_EP1_ISR_REMOVE */
#if(USBFS_1_EP2_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_2_VECT_NUM);
#endif /* End USBFS_1_EP2_ISR_REMOVE */
#if(USBFS_1_EP3_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_3_VECT_NUM);
#endif /* End USBFS_1_EP3_ISR_REMOVE */
#if(USBFS_1_EP4_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_4_VECT_NUM);
#endif /* End USBFS_1_EP4_ISR_REMOVE */
#if(USBFS_1_EP5_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_5_VECT_NUM);
#endif /* End USBFS_1_EP5_ISR_REMOVE */
#if(USBFS_1_EP6_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_6_VECT_NUM);
#endif /* End USBFS_1_EP6_ISR_REMOVE */
#if(USBFS_1_EP7_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_7_VECT_NUM);
#endif /* End USBFS_1_EP7_ISR_REMOVE */
#if(USBFS_1_EP8_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_8_VECT_NUM);
#endif /* End USBFS_1_EP8_ISR_REMOVE */
#if((USBFS_1_EP_MM != USBFS_1__EP_MANUAL) && (USBFS_1_ARB_ISR_REMOVE == 0u))
/* usb arb interrupt enable */
USBFS_1_ARB_INT_EN_REG = USBFS_1_ARB_INT_MASK;
CyIntEnable(USBFS_1_ARB_VECT_NUM);
#endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */
/* Arbiter configuration for DMA transfers */
#if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)
#if(USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL)
USBFS_1_ARB_CFG_REG = USBFS_1_ARB_CFG_MANUAL_DMA;
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL */
#if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)
/*Set cfg cmplt this rises DMA request when the full configuration is done */
USBFS_1_ARB_CFG_REG = USBFS_1_ARB_CFG_AUTO_DMA | USBFS_1_ARB_CFG_AUTO_MEM;
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */
#endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */
USBFS_1_transferState = USBFS_1_TRANS_STATE_IDLE;
/* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/
switch(mode)
{
case USBFS_1_3V_OPERATION:
USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK;
break;
case USBFS_1_5V_OPERATION:
USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK | USBFS_1_CR1_REG_ENABLE;
break;
default: /*USBFS_1_DWR_VDDD_OPERATION */
#if(USBFS_1_VDDD_MV < USBFS_1_3500MV)
USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK;
#else
USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK | USBFS_1_CR1_REG_ENABLE;
#endif /* End USBFS_1_VDDD_MV < USBFS_1_3500MV */
break;
}
/* Record the descriptor selection */
USBFS_1_device = device;
/* Clear all of the component data */
USBFS_1_configuration = 0u;
USBFS_1_interfaceNumber = 0u;
USBFS_1_configurationChanged = 0u;
USBFS_1_deviceAddress = 0u;
USBFS_1_deviceStatus = 0u;
USBFS_1_lastPacketSize = 0u;
/* ACK Setup, Stall IN/OUT */
CY_SET_REG8(USBFS_1_EP0_CR_PTR, USBFS_1_MODE_STALL_IN_OUT);
/* Enable the SIE with an address 0 */
CY_SET_REG8(USBFS_1_CR0_PTR, USBFS_1_CR0_ENABLE);
/* Workaround for PSOC5LP */
CyDelayCycles(1u);
/* Finally, Enable d+ pullup and select iomode to USB mode*/
CY_SET_REG8(USBFS_1_USBIO_CR1_PTR, USBFS_1_USBIO_CR1_USBPUEN);
}
/*******************************************************************************
* Function Name: USBUART_Resume
****************************************************************************//**
*
* This function prepares the USBFS component for active mode operation after
* exit low power mode. It restores the component active mode configuration such
* as device address assigned previously by the host, endpoints buffer and disables
* interrupt on Dp pin.
* The supported low power modes are Deep Sleep (PSoC 4200L) and Sleep
* (PSoC 3/ PSoC 5LP).
*
* *Note* For PSoC 4200L devices, this function should not be called after
* exiting Sleep.
*
* *Note* To resume communication with the host, the data endpoints must be
* managed: the OUT endpoints must be enabled and IN endpoints must be loaded
* with data. For DMA with Automatic Buffer Management, all endpoints buffers
* must be initialized again before making them available to the host.
*
*
* \globalvars
* USBUART_backup - checked.
*
* \reentrant
* No.
*
*******************************************************************************/
void USBUART_Resume(void)
{
uint8 enableInterrupts;
enableInterrupts = CyEnterCriticalSection();
if (0u != USBUART_backup.enableState)
{
#if (USBUART_DP_ISR_ACTIVE)
CyIntDisable(USBUART_DP_INTC_VECT_NUM);
#endif /* (USBUART_DP_ISR_ACTIVE) */
#if (CY_PSOC4)
/* Enable clock to USB IP. */
USBUART_USB_CLK_EN_REG |= USBUART_USB_CLK_CSR_CLK_EN;
/* Restore arbiter configuration for DMA transfers. */
#if (USBUART_EP_MANAGEMENT_DMA)
#if (USBUART_ARB_ISR_ACTIVE)
/* Enable ARB EP interrupt sources. */
USBUART_ARB_INT_EN_REG = USBUART_DEFAULT_ARB_INT_EN;
#endif /* (USBUART_EP_MANAGEMENT_DMA) */
/* Configure arbiter for Manual or Auto DMA operation and clear
* configuration completion.
*/
USBUART_ARB_CFG_REG = USBUART_DEFAULT_ARB_CFG;
#endif /* (USBUART_EP_MANAGEMENT_DMA) */
/* Restore level (hi, lo, med) for each interrupt source. */
USBUART_INTR_LVL_SEL_REG = USBUART_DEFAULT_INTR_LVL_SEL;
/* Store SIE interrupt sources. */
USBUART_INTR_SIE_MASK_REG = (uint32) USBUART_backup.intrSeiMask;
/* Set EP0.CR: ACK Setup, NAK IN/OUT. */
USBUART_EP0_CR_REG = USBUART_MODE_NAK_IN_OUT;
/* Restore data EP1-8 configuration. */
USBUART_RestoreConfig();
/* Restore state of USB regulator and wait until it supples stable power. */
USBUART_CR1_REG |= USBUART_backup.mode;
CyDelayUs(USBUART_WAIT_VREF_STABILITY);
/* Suspend exit sequence. */
USBUART_POWER_CTRL_REG &= (uint32) ~USBUART_POWER_CTRL_SUSPEND;
CyDelayUs(USBUART_WAIT_SUSPEND_DEL_DISABLE);
USBUART_POWER_CTRL_REG &= (uint32) ~USBUART_POWER_CTRL_SUSPEND_DEL;
#else
/* Set power active and standby mode templates: enable USB block. */
USBUART_PM_ACT_CFG_REG |= USBUART_PM_ACT_EN_FSUSB;
USBUART_PM_STBY_CFG_REG |= USBUART_PM_STBY_EN_FSUSB;
/* Enable core clock. */
USBUART_USB_CLK_EN_REG |= USBUART_USB_CLK_ENABLE;
/* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/
USBUART_PM_USB_CR0_REG |= USBUART_PM_USB_CR0_REF_EN;
/* The reference is available ~40us after power restored. */
CyDelayUs(USBUART_WAIT_VREF_RESTORE);
/* Restore state of USB regulator and wait until it supples stable power. */
USBUART_CR1_REG |= USBUART_backup.mode;
CyDelayUs(USBUART_WAIT_VREF_STABILITY); /*~50ns delay. */
/* Enable USBIO. */
USBUART_PM_USB_CR0_REG |= USBUART_PM_USB_CR0_PD_N;
CyDelayUs(USBUART_WAIT_PD_PULLUP_N_ENABLE);
/* Set the USBIO pull-up enable. */
USBUART_PM_USB_CR0_REG |= USBUART_PM_USB_CR0_PD_PULLUP_N;
/* Restore arbiter configuration for DMA transfers. */
#if (USBUART_EP_MANAGEMENT_DMA)
#if (USBUART_ARB_ISR_ACTIVE)
/* Enable ARB EP interrupt sources. */
USBUART_ARB_INT_EN_REG = USBUART_DEFAULT_ARB_INT_EN;
#endif /* (USBUART_EP_MANAGEMENT_DMA) */
/* Configure arbiter for Manual or Auto DMA operation and clear
* configuration completion.
*/
USBUART_ARB_CFG_REG = USBUART_DEFAULT_ARB_CFG;
#endif /* (USBUART_EP_MANAGEMENT_DMA) */
/* Set EP0.CR: ACK Setup, STALL IN/OUT. */
USBUART_EP0_CR_REG = USBUART_MODE_STALL_IN_OUT;
/* Enable the USB IP to respond to USB traffic with the last address. */
USBUART_CR0_REG |= USBUART_CR0_ENABLE;
CyDelayCycles(USBUART_WAIT_CR0_REG_STABILITY);
/* Enable D+ pull-up and keep USB control on IO. */
USBUART_USBIO_CR1_REG = USBUART_USBIO_CR1_USBPUEN;
/* Restore data EP1-8 configuration. */
USBUART_RestoreConfig();
#endif /* (CY_PSOC4) */
}
CyExitCriticalSection(enableInterrupts);
}
