/*******************************************************************************
* Function Name: emFile_SPI0_EnableInt
********************************************************************************
*
* Summary:
* Enable internal interrupt generation.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Theory:
* Enable the internal interrupt output -or- the interrupt component itself.
*
*******************************************************************************/
void emFile_SPI0_EnableInt(void)
{
#if(emFile_SPI0_InternalTxInterruptEnabled)
CyIntEnable(emFile_SPI0_TX_ISR_NUMBER);
#endif /* emFile_SPI0_InternalTxInterruptEnabled */
#if(emFile_SPI0_InternalRxInterruptEnabled)
CyIntEnable(emFile_SPI0_RX_ISR_NUMBER);
#endif /* emFile_SPI0_InternalRxInterruptEnabled */
}
/*******************************************************************************
* Function Name: SPIM_EnableInt
********************************************************************************
*
* Summary:
* Enable internal interrupt generation.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Theory:
* Enable the internal interrupt output -or- the interrupt component itself.
*
*******************************************************************************/
void SPIM_EnableInt(void)
{
#if(SPIM_InternalTxInterruptEnabled)
CyIntEnable(SPIM_TX_ISR_NUMBER);
#endif /* SPIM_InternalTxInterruptEnabled */
#if(SPIM_InternalRxInterruptEnabled)
CyIntEnable(SPIM_RX_ISR_NUMBER);
#endif /* SPIM_InternalRxInterruptEnabled */
}
/*****************************************************************************
* Function Name: _Watchdog_Init()
******************************************************************************
* Summary:
* Initialize the watchdog.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Note:
*
*****************************************************************************/
void _Watchdog_Init(void)
{
// Unlock the WDT registers for modification.
CySysWdtUnlock();
// Write Mode for Counters as Interrupt on Match.
CySysWdtWriteMode(CY_SYS_WDT_COUNTER0, CY_SYS_WDT_MODE_INT);
CySysWdtWriteMode(CY_SYS_WDT_COUNTER1, CY_SYS_WDT_MODE_INT);
// Set Clear on Match for Counters.
CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER0, TRUE);
CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER1, TRUE);
// Set Watchdog interrupt to lower priority.
CyIntSetPriority(WATCHDOG_INT_VEC_NUM, WATCHDOG_INT_VEC_PRIORITY);
// Enable Watchdog Interrupt using Interrupt number.
CyIntEnable(WATCHDOG_INT_VEC_NUM);
// Write the match value in Counters.
CySysWdtWriteMatch(CY_SYS_WDT_COUNTER0, WATCHDOG_COUNTER0_PERIOD);
CySysWdtWriteMatch(CY_SYS_WDT_COUNTER1, WATCHDOG_COUNTER1_PERIOD);
// Enable Counters.
CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK);
CySysWdtEnable(CY_SYS_WDT_COUNTER1_MASK);
// Lock Watchdog to prevent further changes.
CySysWdtLock();
// Set the Watchdog Interrupt vector to the address of Interrupt routine
// _Watchdog_Handler.
CyIntSetVector(WATCHDOG_INT_VEC_NUM, &_Watchdog_Handler);
}
/*******************************************************************************
* Function Name: quaddec_right_SetCounter
********************************************************************************
*
* Summary:
* Sets the current value of the counter.
*
* Parameters:
* value: The new value. Parameter type is signed and per the counter size
* setting.
*
* Return:
* None.
*
* Global variables:
* quaddec_right_count32SoftPart - modified to set hi 16 bit for current value
* of the 32-bit counter, when Counter size equal 32-bit.
*
* Reentrant:
* No.
*
*******************************************************************************/
void quaddec_right_SetCounter(int32 value)
{
#if ((quaddec_right_COUNTER_SIZE == 8u) || (quaddec_right_COUNTER_SIZE == 16u))
uint16 count;
#endif /* (quaddec_right_COUNTER_SIZE == 8u) || (quaddec_right_COUNTER_SIZE == 16u) */
#if (quaddec_right_COUNTER_SIZE == 8u)
count = (value ^ 0x80u);
quaddec_right_Cnt8_WriteCounter(count);
#endif /* quaddec_right_COUNTER_SIZE == 8u */
#if (quaddec_right_COUNTER_SIZE == 16u)
count = (value ^ 0x8000u);
quaddec_right_Cnt16_WriteCounter(count);
#endif /* quaddec_right_COUNTER_SIZE == 16u */
#if (quaddec_right_COUNTER_SIZE == 32u)
CyIntDisable(quaddec_right_ISR_NUMBER);
quaddec_right_Cnt16_WriteCounter(0x8000u);
quaddec_right_count32SoftPart = value;
CyIntEnable(quaddec_right_ISR_NUMBER);
#endif /* quaddec_right_COUNTER_SIZE == 32u */
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Enable HALF_EN before trimming for the flash accelerator. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(24u);
/* Disable HALF_EN since it is not required at this IMO frequency. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu));
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT03), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT08), 0x00000010u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000001u);
/* CYDEV_CLK_DIVIDER_B00 Starting address: CYDEV_CLK_DIVIDER_B00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_B00), 0x800000CFu);
(void)CyIntSetVector(9u, &CySysWdtIsr);
CyIntEnable(9u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(48u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* Setup phase aligned clocks */
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00002200u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00002200u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);
/* CYDEV_PERI_PCLK_CTL5 Starting address: CYDEV_PERI_PCLK_CTL5 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL5), 0x00000040u);
/* CYDEV_PERI_PCLK_CTL3 Starting address: CYDEV_PERI_PCLK_CTL3 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL3), 0x00000041u);
(void)CyIntSetVector(7u, &CySysWdtIsr);
CyIntEnable(7u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
/* Start the WCO */
CySysClkWcoStart();
(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM); /* Switch to the low power mode */
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(24u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* Enable fast start mode for XO */
CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
/* Disable Crystal Stable Interrupt before enabling ECO */
CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
/* Start the ECO and do not check status since it is not needed for HFCLK */
(void)CySysClkEcoStart(2000u);
CyDelayUs(1500u); /* Wait to stabalize */
/* Setup phase aligned clocks */
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL2, 0x0001DF00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF42u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00000E00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00001000u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_PERI_PCLK_CTL11 Starting address: CYDEV_PERI_PCLK_CTL11 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL11), 0x00000042u);
/* CYDEV_PERI_PCLK_CTL8 Starting address: CYDEV_PERI_PCLK_CTL8 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL8), 0x00000042u);
/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000042u);
/* CYDEV_PERI_PCLK_CTL2 Starting address: CYDEV_PERI_PCLK_CTL2 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL2), 0x00000040u);
/* CYDEV_PERI_PCLK_CTL1 Starting address: CYDEV_PERI_PCLK_CTL1 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL1), 0x00000041u);
(void)CyIntSetVector(8u, &CySysWdtIsr);
CyIntEnable(8u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
/* Set Flash Cycles based on newly configured 24.00MHz HFCLK. */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0011u));
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
/* Start the WCO */
CySysClkWcoStart();
CyDelayCycles(12000000u); /* WCO may take up to 500ms to start */
(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM); /* Switch to the low power mode */
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(48u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
/* Enable fast start mode for XO */
CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
/*Set XTAL(ECO) divider*/
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG), 0x00000000u);
/* Disable Crystal Stable Interrupt before enabling ECO */
CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
/* Start the ECO and do not check status since it is not needed for HFCLK */
(void)CySysClkEcoStart(2000u);
CyDelayUs(1500u); /* Wait to stabalize */
/* Setup phase aligned clocks */
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00BB7F00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x0001A000u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);
/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000041u);
/* CYDEV_PERI_PCLK_CTL2 Starting address: CYDEV_PERI_PCLK_CTL2 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL2), 0x00000040u);
(void)CyIntSetVector(8u, &CySysWdtIsr);
CyIntEnable(8u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_MATCH), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000005u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000008u);
while ((CY_GET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL)) & 0x00000008u) != 0u) { }
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONTROL), 0x00000001u);
}
/*******************************************************************************
* Function Name: USBUART_Suspend
********************************************************************************
*
* Summary:
* This function disables the USBFS block and prepares for power down mode.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Global variables:
* USBUART_backup.enable: modified.
*
* Reentrant:
* No.
*
*******************************************************************************/
void USBUART_Suspend(void)
{
uint8 enableInterrupts;
enableInterrupts = CyEnterCriticalSection();
if((CY_GET_REG8(USBUART_CR0_PTR) & USBUART_CR0_ENABLE) != 0u)
{ /* USB block is enabled */
USBUART_backup.enableState = 1u;
#if(USBUART_EP_MM != USBUART__EP_MANUAL)
USBUART_Stop_DMA(USBUART_MAX_EP); /* Stop all DMAs */
#endif /* USBUART_EP_MM != USBUART__EP_MANUAL */
/* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
USBUART_USBIO_CR0_REG &= (uint8)~USBUART_USBIO_CR0_TEN;
CyDelayUs(0u); /*~50ns delay */
/* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */
USBUART_PM_USB_CR0_REG &=
(uint8)~(USBUART_PM_USB_CR0_PD_N | USBUART_PM_USB_CR0_PD_PULLUP_N);
/* Disable the SIE */
USBUART_CR0_REG &= (uint8)~USBUART_CR0_ENABLE;
CyDelayUs(0u); /* ~50ns delay */
/* Store mode and Disable VRegulator*/
USBUART_backup.mode = USBUART_CR1_REG & USBUART_CR1_REG_ENABLE;
USBUART_CR1_REG &= (uint8)~USBUART_CR1_REG_ENABLE;
CyDelayUs(1u); /* 0.5 us min delay */
/* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/
USBUART_PM_USB_CR0_REG &= (uint8)~USBUART_PM_USB_CR0_REF_EN;
/* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/
USBUART_USBIO_CR1_REG |= USBUART_USBIO_CR1_IOMODE;
/* Disable USB in ACT PM */
USBUART_PM_ACT_CFG_REG &= (uint8)~USBUART_PM_ACT_EN_FSUSB;
/* Disable USB block for Standby Power Mode */
USBUART_PM_STBY_CFG_REG &= (uint8)~USBUART_PM_STBY_EN_FSUSB;
CyDelayUs(1u); /* min 0.5us delay required */
}
else
{
USBUART_backup.enableState = 0u;
}
CyExitCriticalSection(enableInterrupts);
/* Set the DP Interrupt for wake-up from sleep mode. */
#if(USBUART_DP_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBUART_DP_INTC_VECT_NUM, &USBUART_DP_ISR);
CyIntSetPriority(USBUART_DP_INTC_VECT_NUM, USBUART_DP_INTC_PRIOR);
CyIntClearPending(USBUART_DP_INTC_VECT_NUM);
CyIntEnable(USBUART_DP_INTC_VECT_NUM);
#endif /* (USBUART_DP_ISR_REMOVE == 0u) */
}
/*******************************************************************************
* Function Name: emFile_SPI0_Enable
********************************************************************************
*
* Summary:
* Enable SPIM component.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void emFile_SPI0_Enable(void)
{
uint8 enableInterrupts = 0u;
enableInterrupts = CyEnterCriticalSection();
emFile_SPI0_COUNTER_CONTROL_REG |= emFile_SPI0_CNTR_ENABLE;
emFile_SPI0_TX_STATUS_ACTL_REG |= emFile_SPI0_INT_ENABLE;
emFile_SPI0_RX_STATUS_ACTL_REG |= emFile_SPI0_INT_ENABLE;
CyExitCriticalSection(enableInterrupts);
#if(emFile_SPI0_InternalClockUsed)
emFile_SPI0_IntClock_Enable();
#endif /* emFile_SPI0_InternalClockUsed */
#if(emFile_SPI0_InternalTxInterruptEnabled)
CyIntEnable(emFile_SPI0_TX_ISR_NUMBER);
#endif /* emFile_SPI0_InternalTxInterruptEnabled */
#if(emFile_SPI0_InternalRxInterruptEnabled)
CyIntEnable(emFile_SPI0_RX_ISR_NUMBER);
#endif /* emFile_SPI0_InternalRxInterruptEnabled */
}
/*******************************************************************************
* Function Name: SPIM_Enable
********************************************************************************
*
* Summary:
* Enable SPIM component.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void SPIM_Enable(void)
{
uint8 enableInterrupts = 0u;
enableInterrupts = CyEnterCriticalSection();
SPIM_COUNTER_CONTROL_REG |= SPIM_CNTR_ENABLE;
SPIM_TX_STATUS_ACTL_REG |= SPIM_INT_ENABLE;
SPIM_RX_STATUS_ACTL_REG |= SPIM_INT_ENABLE;
CyExitCriticalSection(enableInterrupts);
#if(SPIM_InternalClockUsed)
SPIM_IntClock_Enable();
#endif /* SPIM_InternalClockUsed */
#if(SPIM_InternalTxInterruptEnabled)
CyIntEnable(SPIM_TX_ISR_NUMBER);
#endif /* SPIM_InternalTxInterruptEnabled */
#if(SPIM_InternalRxInterruptEnabled)
CyIntEnable(SPIM_RX_ISR_NUMBER);
#endif /* SPIM_InternalRxInterruptEnabled */
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
if (!enable)
CY_SET_REG8(obj->inttypeReg, 0x0);
else if (event == IRQ_RISE)
CY_SET_REG8(obj->inttypeReg, 0x01);
else if (event == IRQ_FALL)
CY_SET_REG8(obj->inttypeReg, 0x02);
else if (event == (IRQ_FALL | IRQ_RISE))
CY_SET_REG8(obj->inttypeReg, 0x03);
else
debug("Did not set any interrupt handler type!\r\n");
obj->intTypeValue = CY_GET_REG8(obj->inttypeReg);
CyIntSetVector(obj->irqLine, handle_interrupt_in);
CyIntEnable(obj->irqLine);
}
/*******************************************************************************
* Function Name: quaddec_right_Enable
********************************************************************************
*
* Summary:
* This function enable interrupts from Component and also enable Component's
* isr for 32-bit counter.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
void quaddec_right_Enable(void)
{
uint8 enableInterrupts = 0u;
quaddec_right_SetInterruptMask(quaddec_right_INIT_INT_MASK);
enableInterrupts = CyEnterCriticalSection();
/* Enable interrupts from Statusi register */
quaddec_right_SR_AUX_CONTROL |= quaddec_right_INTERRUPTS_ENABLE;
CyExitCriticalSection(enableInterrupts);
#if (quaddec_right_COUNTER_SIZE == 32u)
/* Enable Component interrupts */
CyIntEnable(quaddec_right_ISR_NUMBER);
#endif /* quaddec_right_COUNTER_SIZE == 32u */
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0011u));
/* Update IMO to new clock speed. */
CySysClkWriteImoFreq(24u);
/* Setup phase aligned clocks */
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00000004u);
(void)CyIntSetVector(4u, &CySysWdtIsr);
CyIntEnable(4u);
/* Set Flash Cycles based on newly configured 12.00MHz HFCLK. */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0000u));
}
/*******************************************************************************
* Function Name: quaddec_right_GetCounter
********************************************************************************
*
* Summary:
* Reports the current value of the counter.
*
* Parameters:
* None.
*
* Return:
* The counter value. Return type is signed and per
* the counter size setting. A positive value indicates
* clockwise movement (B before A).
*
* Global variables:
* quaddec_right_count32SoftPart - used to get hi 16 bit for current value
* of the 32-bit counter, when Counter size equal 32-bit.
*
*******************************************************************************/
int32 quaddec_right_GetCounter(void)
{
int32 count;
uint16 tmpCnt;
#if (quaddec_right_COUNTER_SIZE == 32u)
int16 hwCount;
#endif /* quaddec_right_COUNTER_SIZE == 32u */
#if (quaddec_right_COUNTER_SIZE == 8u)
tmpCnt = quaddec_right_Cnt8_ReadCounter();
count = tmpCnt ^ 0x80u;
#endif /* quaddec_right_COUNTER_SIZE == 8u */
#if (quaddec_right_COUNTER_SIZE == 16u)
tmpCnt = quaddec_right_Cnt16_ReadCounter();
count = tmpCnt ^ 0x8000u;
#endif /* quaddec_right_COUNTER_SIZE == 16u */
#if (quaddec_right_COUNTER_SIZE == 32u)
CyIntDisable(quaddec_right_ISR_NUMBER);
tmpCnt = quaddec_right_Cnt16_ReadCounter();
hwCount = tmpCnt ^ 0x8000u;
count = quaddec_right_count32SoftPart + hwCount;
CyIntEnable(quaddec_right_ISR_NUMBER);
#endif /* quaddec_right_COUNTER_SIZE == 32u */
return(count);
}
/*****************************************************************************
* Function Name: WatchdogTimer_Sync()
******************************************************************************
* Summary:
* Synchronizes the watchdog timestamp to the current system time.
*
* Parameters:
* None
*
* Return:
* None
*
* Theory:
* Updates the watchdog timestamp to the current value.
*
* Side Effects:
* None
*
* Note:
*
*****************************************************************************/
void WatchdogTimer_Sync(void)
{
uint32 wdtIntState;
uint16 wdtCounter;
uint16 wdtPreviousMatch;
uint16 wdtCurrentMatch;
uint16 ticksElapsed;
/* Capture the WDT interrupt enable and disable the WDT interrupt. */
wdtIntState = CyIntGetState(WDT_INTERRUPT_NUM);
CyIntDisable(WDT_INTERRUPT_NUM);
wdtCounter = CY_GET_REG32(CYREG_WDT_CTRLOW);
wdtCurrentMatch = CY_GET_REG32(CYREG_WDT_MATCH);
/* Find time elapsed since last WDT interrupt */
wdtPreviousMatch = wdtCurrentMatch - nextTicks;
ticksElapsed = wdtCounter - wdtPreviousMatch;
watchdogTimestamp += ticksElapsed / WATCHDOG_TICKS_PER_MS;
/* Add slow timer period to match register for next interrupt */
WatchdogTimer_Unlock();
UPDATE_WDT_MATCH((uint16)(wdtCounter + nextTicks -
(ticksElapsed % WATCHDOG_TICKS_PER_MS)));
/* Clear pending WDT interrupt */
CY_SET_REG32(CYREG_WDT_CONTROL, CY_GET_REG32(CYREG_WDT_CONTROL) | WDT_CONTROL_WDT_INT0);
CyIntClearPending(WDT_INTERRUPT_NUM);
WatchdogTimer_Lock();
/* Restore WDT interrupt enable */
if(wdtIntState)
{
CyIntEnable(WDT_INTERRUPT_NUM);
}
}
//firmware initialization
void initialize(void)
{
//debug pin toggle
P4_0_Debug_Write(0xff);
//debug pin toggle
P4_0_Debug_Write(0x00);
//debug pin toggle
P4_0_Debug_Write(0xff);
//debug pin toggle
P4_0_Debug_Write(0x00);
//enable interrupts
CyGlobalIntEnable; /* Uncomment this line to enable global interrupts. */
//start watchdog
/* Setup WDT ISR */
CyIntSetVector(9, isr_wdt);
CyIntEnable(9);
/* Setup first WDT counter to generate interrupt on match 0x4FFF */
CySysWdtWriteMode(CY_SYS_WDT_COUNTER0,CY_SYS_WDT_MODE_INT);
CySysWdtWriteMatch(CY_SYS_WDT_COUNTER0,0x4FFF);
CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER0, 1u);
/* Enable WDT timers 0 and 1 cascade */
CySysWdtWriteCascade(CY_SYS_WDT_CASCADE_01);
/* Set WDT reset after counter 1 reach 0x0002 */
CySysWdtWriteMatch(CY_SYS_WDT_COUNTER1,0x0002);
CySysWdtWriteMode(CY_SYS_WDT_COUNTER1,CY_SYS_WDT_MODE_RESET);
CySysWdtWriteClearOnMatch(CY_SYS_WDT_COUNTER1, 1u);
/* Enable WDT counters 0 and 1 */
//#if(WATCHDOG_ENABLED)
CySysWdtEnable(CY_SYS_WDT_COUNTER0_MASK | CY_SYS_WDT_COUNTER1_MASK);
//#endif
//start components
sensors_Start();
motors_Start();
control_Start();
}
/*****************************************************************************
* Function Name: WatchdogTimer_Start()
******************************************************************************
* Summary:
* Initializes the watchdog timer.
*
* Parameters:
* wdtPeriodMs - The watchdog timer period to set, in milliseconds.
*
* Return:
* None
*
* Theory:
* Writes to the SRSS registers to start the low frequency clock and configure
* the watchdog timer. The watchdog timer is configured for 16-bit timing,
* and to generate an interrupt on match, plus an overflow on the third
* unserviced interrupt. The interrupt vector is pointed to a custom ISR in
* this file.
*
* Side Effects:
* None
*
* Note:
*
*****************************************************************************/
void WatchdogTimer_Start(uint32 wdtPeriodMs)
{
watchdogTimestamp = 0;
CyIntSetVector(WDT_INTERRUPT_NUM, &WatchdogTimer_Isr);
WatchdogTimer_Unlock();
/* Set the WDT period */
watchdogPeriodMs = wdtPeriodMs;
nextTicks = watchdogPeriodMs * WATCHDOG_TICKS_PER_MS;
UPDATE_WDT_MATCH(nextTicks);
#if (CY_PSOC4_4200)
/* For PSoC4A - Start ILO */
CY_SET_REG32(CYREG_CLK_ILO_CONFIG, CY_GET_REG32(CYREG_CLK_ILO_CONFIG) | CLK_ILO_CONFIG_ILO_ENABLE);
#elif (CY_PSOC4_4200BL)
/*
* For PSoC 4 BLE - Assume that WCO is started as part of CyBoot
* since WCO is selected as LFCLK source in the CYDWR.
*/
#endif /* #if (CY_PSOC4_4200) */
/* Enable WDT interrupt for the NVIC */
CyIntEnable(WDT_INTERRUPT_NUM);
/* Set WDT_CONFIG register */
CY_SET_REG32(CYREG_WDT_CONFIG, CY_GET_REG32(CYREG_WDT_CONFIG) | WDT_CONFIG_WDT_MODE0_INT);
/* Set WDT_CONTROL register */
CY_SET_REG32(CYREG_WDT_CONTROL, WDT_CONTROL_WDT_ENABLE0);
/* Wait for the WDT enable to complete */
while((CY_GET_REG32(CYREG_WDT_CONTROL) & WDT_CONTROL_WDT_ENABLED0) == 0);
WatchdogTimer_Lock();
}
/*******************************************************************************
* Function Name: main
********************************************************************************
*
* Summary:
* At the beginning of the main function, the GPIO interrupt is set up and
* enabled. After that, initial priority for the GPIO interrupt is changed from
* 1 to 3 (DEFAULT_PRIORITY). The custom interrupt (nested) is configured
* (sets up, sets priority) and enabled. In GPIOIsrHandler, the isr_GPIO
* pending interrupt clears, the green LED turns on, the nested software
* interrupt causes after approximately 1 second delay, green LED turns off.
*
* Parameters:
* None.
*
* Return:
* None.
*
*******************************************************************************/
int main()
{
/* Set initial state (off) for LED */
LED_Isr_Write(LIGHT_OFF);
LED_Nested_Write(LIGHT_OFF);
/* Sets up the GPIO interrupt and enables it */
isr_GPIO_StartEx(GPIOIsrHandler);
/* Changes initial priority for the GPIO interrupt */
isr_GPIO_SetPriority(DEFAULT_PRIORITY);
/* Sets up the nested interrupt, sets priority and enables it */
CyIntSetVector(NESTED_ISR,NestedIsrHandler);
CyIntSetPriority(NESTED_ISR,HIGHER_PRIORITY);
CyIntEnable(NESTED_ISR);
/* Enable global interrupts */
CyGlobalIntEnable;
for(;;)
{
}
}
/*******************************************************************************
* Function Name: emFile_1_SPI0_EnableRxInt
********************************************************************************
*
* Summary:
* Enable internal Rx interrupt generation.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Theory:
* Enable the internal Rx interrupt output -or- the interrupt component itself.
*
*******************************************************************************/
void emFile_1_SPI0_EnableRxInt(void)
{
#if(0u != emFile_1_SPI0_INTERNAL_RX_INT_ENABLED)
CyIntEnable(emFile_1_SPI0_RX_ISR_NUMBER);
#endif /* (0u != emFile_1_SPI0_INTERNAL_RX_INT_ENABLED) */
}
/*******************************************************************************
* Function Name: SPIM_1_EnableTxInt
********************************************************************************
*
* Summary:
* Enable internal Tx interrupt generation.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Theory:
* Enable the internal Tx interrupt output -or- the interrupt component itself.
*
*******************************************************************************/
void SPIM_1_EnableTxInt(void)
{
#if(0u != SPIM_1_INTERNAL_TX_INT_ENABLED)
CyIntEnable(SPIM_1_TX_ISR_NUMBER);
#endif /* (0u != SPIM_1_INTERNAL_TX_INT_ENABLED) */
}
/*******************************************************************************
* Function Name: ST7528_1_SPI_EnableTxInt
********************************************************************************
*
* Summary:
* Enable internal Tx interrupt generation.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Theory:
* Enable the internal Tx interrupt output -or- the interrupt component itself.
*
*******************************************************************************/
void ST7528_1_SPI_EnableTxInt(void)
{
#if(0u != ST7528_1_SPI_INTERNAL_TX_INT_ENABLED)
CyIntEnable(ST7528_1_SPI_TX_ISR_NUMBER);
#endif /* (0u != ST7528_1_SPI_INTERNAL_TX_INT_ENABLED) */
}
/*******************************************************************************
* Function Name: USBFS_1_InitComponent
********************************************************************************
*
* Summary:
* Initialize the component, except for the HW which is done one time in
* the Start function. This function pulls up D+.
*
* Parameters:
* device: Contains the device number of the desired device descriptor.
* The device number can be found in the Device Descriptor Tab of
* "Configure" dialog, under the settings of desired Device Descriptor,
* in the "Device Number" field.
* mode: The operating voltage. This determines whether the voltage regulator
* is enabled for 5V operation or if pass through mode is used for 3.3V
* operation. Symbolic names and their associated values are given in the
* following table.
* USBFS_1_3V_OPERATION - Disable voltage regulator and pass-thru
* Vcc for pull-up
* USBFS_1_5V_OPERATION - Enable voltage regulator and use
* regulator for pull-up
* USBFS_1_DWR_VDDD_OPERATION - Enable or Disable voltage
* regulator depend on Vddd Voltage configuration in DWR.
*
* Return:
* None.
*
* Global variables:
* USBFS_1_device: Contains the device number of the desired device
* descriptor. The device number can be found in the Device Descriptor Tab
* of "Configure" dialog, under the settings of desired Device Descriptor,
* in the "Device Number" field.
* USBFS_1_transferState: This variable used by the communication
* functions to handle current transfer state. Initialized to
* TRANS_STATE_IDLE in this API.
* USBFS_1_configuration: Contains current configuration number
* which is set by the Host using SET_CONFIGURATION request.
* Initialized to zero in this API.
* USBFS_1_deviceAddress: Contains current device address. This
* variable is initialized to zero in this API. Host starts to communicate
* to device with address 0 and then set it to whatever value using
* SET_ADDRESS request.
* USBFS_1_deviceStatus: initialized to 0.
* This is two bit variable which contain power status in first bit
* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote
* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.
* USBFS_1_lastPacketSize initialized to 0;
*
* Reentrant:
* No.
*
*******************************************************************************/
void USBFS_1_InitComponent(uint8 device, uint8 mode)
{
/* Initialize _hidProtocol variable to comply with
* HID 7.2.6 Set_Protocol Request:
* "When initialized, all devices default to report protocol."
*/
#if defined(USBFS_1_ENABLE_HID_CLASS)
uint8 i;
for (i = 0u; i < USBFS_1_MAX_INTERFACES_NUMBER; i++)
{
USBFS_1_hidProtocol[i] = USBFS_1_PROTOCOL_REPORT;
}
#endif /* USBFS_1_ENABLE_HID_CLASS */
/* Enable Interrupts. */
CyIntEnable(USBFS_1_BUS_RESET_VECT_NUM);
CyIntEnable(USBFS_1_EP_0_VECT_NUM);
#if(USBFS_1_EP1_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_1_VECT_NUM);
#endif /* End USBFS_1_EP1_ISR_REMOVE */
#if(USBFS_1_EP2_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_2_VECT_NUM);
#endif /* End USBFS_1_EP2_ISR_REMOVE */
#if(USBFS_1_EP3_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_3_VECT_NUM);
#endif /* End USBFS_1_EP3_ISR_REMOVE */
#if(USBFS_1_EP4_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_4_VECT_NUM);
#endif /* End USBFS_1_EP4_ISR_REMOVE */
#if(USBFS_1_EP5_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_5_VECT_NUM);
#endif /* End USBFS_1_EP5_ISR_REMOVE */
#if(USBFS_1_EP6_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_6_VECT_NUM);
#endif /* End USBFS_1_EP6_ISR_REMOVE */
#if(USBFS_1_EP7_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_7_VECT_NUM);
#endif /* End USBFS_1_EP7_ISR_REMOVE */
#if(USBFS_1_EP8_ISR_REMOVE == 0u)
CyIntEnable(USBFS_1_EP_8_VECT_NUM);
#endif /* End USBFS_1_EP8_ISR_REMOVE */
#if((USBFS_1_EP_MM != USBFS_1__EP_MANUAL) && (USBFS_1_ARB_ISR_REMOVE == 0u))
/* usb arb interrupt enable */
USBFS_1_ARB_INT_EN_REG = USBFS_1_ARB_INT_MASK;
CyIntEnable(USBFS_1_ARB_VECT_NUM);
#endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */
/* Arbiter configuration for DMA transfers */
#if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)
#if(USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL)
USBFS_1_ARB_CFG_REG = USBFS_1_ARB_CFG_MANUAL_DMA;
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL */
#if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)
/*Set cfg cmplt this rises DMA request when the full configuration is done */
USBFS_1_ARB_CFG_REG = USBFS_1_ARB_CFG_AUTO_DMA | USBFS_1_ARB_CFG_AUTO_MEM;
#endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */
#endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */
USBFS_1_transferState = USBFS_1_TRANS_STATE_IDLE;
/* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/
switch(mode)
{
case USBFS_1_3V_OPERATION:
USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK;
break;
case USBFS_1_5V_OPERATION:
USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK | USBFS_1_CR1_REG_ENABLE;
break;
default: /*USBFS_1_DWR_VDDD_OPERATION */
#if(USBFS_1_VDDD_MV < USBFS_1_3500MV)
USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK;
#else
USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK | USBFS_1_CR1_REG_ENABLE;
#endif /* End USBFS_1_VDDD_MV < USBFS_1_3500MV */
break;
}
/* Record the descriptor selection */
USBFS_1_device = device;
/* Clear all of the component data */
USBFS_1_configuration = 0u;
USBFS_1_interfaceNumber = 0u;
USBFS_1_configurationChanged = 0u;
USBFS_1_deviceAddress = 0u;
USBFS_1_deviceStatus = 0u;
USBFS_1_lastPacketSize = 0u;
/* ACK Setup, Stall IN/OUT */
CY_SET_REG8(USBFS_1_EP0_CR_PTR, USBFS_1_MODE_STALL_IN_OUT);
/* Enable the SIE with an address 0 */
CY_SET_REG8(USBFS_1_CR0_PTR, USBFS_1_CR0_ENABLE);
/* Workaround for PSOC5LP */
CyDelayCycles(1u);
/* Finally, Enable d+ pullup and select iomode to USB mode*/
CY_SET_REG8(USBFS_1_USBIO_CR1_PTR, USBFS_1_USBIO_CR1_USBPUEN);
}
/*******************************************************************************
* FUNCTION NAME: void UART_EnableTxInt(void)
*
* Summary:
* Enable TX interrupt generation
*
* Parameters:
* -None-
*
* Return:
* -None-
*
* Theory:
* Enable the interrupt output -or- the interrupt component itself
*
* Side Effects:
* -None-
*******************************************************************************/
void UART_EnableTxInt(void)
{
CyIntEnable(UART_TX_VECT_NUM);
}
/*******************************************************************************
* FUNCTION NAME: void UART_Start(void)
*
* Summary:
* Initialize and Enable the UART component
*
* Parameters:
* -None-
*
* Return:
* -None-
*
* Theory:
* Enable the clock input to enable operation
*
* Side Effects:
* -None-
*******************************************************************************/
void UART_Start(void)
{
if(UART_initvar == 0)
{
UART_initvar = 1;
#if(UART_RX_Enabled)
#if(UART_RX_IntInterruptEnabled && (UART_RXBUFFERSIZE > 4))
/* Set the RX Interrupt. */
CyIntSetVector(UART_RX_VECT_NUM, UART_RXISR);
CyIntSetPriority(UART_RX_VECT_NUM, UART_RX_PRIOR_NUM);
CyIntEnable(UART_RX_VECT_NUM);
#endif
#if (UART_RXHW_Address_Enabled)
UART_SetRxAddressMode(UART_RXAddressMode);
UART_SetRxAddress1(UART_RXHWADDRESS1);
UART_SetRxAddress2(UART_RXHWADDRESS2);
#endif
/* Configure the Initial RX interrupt mask */
UART_RXSTATUS_MASK = UART_INIT_RX_INTERRUPTS_MASK;
UART_RXSTATUS_ACTL |= UART_INT_ENABLE;
#endif
#if(UART_TX_Enabled)
#if(UART_TX_IntInterruptEnabled && (UART_TXBUFFERSIZE > 4))
/* Set the TX Interrupt. */
CyIntSetVector(UART_TX_VECT_NUM, UART_TXISR);
CyIntSetPriority(UART_TX_VECT_NUM, UART_TX_PRIOR_NUM);
CyIntEnable(UART_TX_VECT_NUM);
#endif
//Write Counter Value for TX Bit Clk Generator
#if(UART_TXCLKGEN_DP)
UART_TXBITCLKGEN_CTR = UART_BIT_CENTER;
UART_TXBITCLKTX_COMPLETE = (UART_NUMBER_OF_DATA_BITS +
UART_NUMBER_OF_START_BIT) *
UART_OverSampleCount;
#endif
/* Configure the Initial TX interrupt mask */
#if(UART_TX_IntInterruptEnabled && (UART_TXBUFFERSIZE > 4))
UART_TXSTATUS_MASK = UART_TX_STS_FIFO_EMPTY;
#else
UART_TXSTATUS_MASK = UART_INIT_TX_INTERRUPTS_MASK;
#endif
UART_TXSTATUS_ACTL |= UART_INT_ENABLE;
#endif
}
/*Write Bit Counter Enable */
#if(UART_RX_Enabled)
UART_RXBITCTR_CONTROL |= UART_CNTR_ENABLE;
#endif
#if(UART_TX_Enabled)
#if(UART_TXCLKGEN_DP)
/* TODO: Start DP*/
#else
UART_TXBITCTR_CONTROL |= UART_CNTR_ENABLE;
#endif
#endif
#if(UART_InternalClockUsed)
/* Set the bit to enable the clock. */
*UART_IntClock_CLKEN |= UART_IntClock_CLKEN_MASK;
#else
#endif
}
/*******************************************************************************
* FUNCTION NAME: void UART_EnableRxInt(void)
*
* Summary:
* Enable RX interrupt generation
*
* Parameters:
* -None-
*
* Return:
* -None-
*
* Theory:
* Enable the interrupt output -or- the interrupt component itself
*
* Side Effects:
* -None-
*******************************************************************************/
void UART_EnableRxInt(void)
{
CyIntEnable(UART_RX_VECT_NUM);
}
/*******************************************************************************
* Function Name: SPI_EnableRxInt
********************************************************************************
*
* Summary:
* Enable internal Rx interrupt generation.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Theory:
* Enable the internal Rx interrupt output -or- the interrupt component itself.
*
*******************************************************************************/
void SPI_EnableRxInt(void)
{
#if(0u != SPI_INTERNAL_RX_INT_ENABLED)
CyIntEnable(SPI_RX_ISR_NUMBER);
#endif /* (0u != SPI_INTERNAL_RX_INT_ENABLED) */
}
/*******************************************************************************
* Function Name: USBUART_Suspend
****************************************************************************//**
*
* This function prepares the USBFS component to enter low power mode. The
* interrupt on falling edge on Dp pin is configured to wakeup device when the
* host drives resume condition. The pull-up is enabled on the Dp line while
* device is in low power mode. The supported low power modes are Deep Sleep
* (PSoC 4200L) and Sleep (PSoC 3/ PSoC 5LP).
*
* *Note* For PSoC 4200L devices, this function should not be called before
* entering Sleep.
*
* *Note* After enter low power mode, the data which is left in the IN or OUT
* endpoint buffers is not restored after wakeup and lost. Therefore it should
* be stored in the SRAM for OUT endpoint or read by the host for IN endpoint
* before enter low power mode.
*
* \globalvars
* USBUART_backup.enable: modified.
*
* \reentrant
* No.
*
*******************************************************************************/
void USBUART_Suspend(void)
{
uint8 enableInterrupts;
enableInterrupts = CyEnterCriticalSection();
if (0u != (USBUART_CR0_REG & USBUART_CR0_ENABLE))
{
/* USB block is enabled. */
USBUART_backup.enableState = 1u;
#if (USBUART_EP_MANAGEMENT_DMA)
USBUART_Stop_DMA(USBUART_MAX_EP);
#endif /* (USBUART_EP_MANAGEMENT_DMA) */
#if (CY_PSOC4)
/* Suspend enter sequence. */
USBUART_POWER_CTRL_REG |= (USBUART_POWER_CTRL_SUSPEND |
USBUART_POWER_CTRL_SUSPEND_DEL);
/* Store state of USB regulator and disable it. */
USBUART_backup.mode = (uint8) (USBUART_CR1_REG & USBUART_CR1_REG_ENABLE);
USBUART_CR1_REG &= (uint32) ~USBUART_CR1_REG_ENABLE;
/* Store SIE interrupt sources. Valid bits are 0 - 4. */
USBUART_backup.intrSeiMask = (uint8) USBUART_INTR_SIE_MASK_REG;
#else
/* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */
USBUART_USBIO_CR0_REG &= (uint8) ~USBUART_USBIO_CR0_TEN;
CyDelayUs(USBUART_WAIT_REG_STABILITY_50NS); /*~50ns delay. */
/* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */
USBUART_PM_USB_CR0_REG &= (uint8) ~(USBUART_PM_USB_CR0_PD_N |
USBUART_PM_USB_CR0_PD_PULLUP_N);
/* Disable the SIE. */
USBUART_CR0_REG &= (uint8) ~USBUART_CR0_ENABLE;
CyDelayUs(USBUART_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */
/* Store mode and disable VRegulator. */
USBUART_backup.mode = (uint8) (USBUART_CR1_REG & USBUART_CR1_REG_ENABLE);
USBUART_CR1_REG &= (uint8) ~USBUART_CR1_REG_ENABLE;
CyDelayUs(USBUART_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */
/* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/
USBUART_PM_USB_CR0_REG &= (uint8) ~USBUART_PM_USB_CR0_REF_EN;
/* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pull-up. */
USBUART_USBIO_CR1_REG |= USBUART_USBIO_CR1_IOMODE;
/* Disable USBFS block. */
/* Clear power active and standby mode templates: disable USB block. */
USBUART_PM_ACT_CFG_REG &= (uint8) ~USBUART_PM_ACT_EN_FSUSB;
USBUART_PM_STBY_CFG_REG &= (uint8) ~USBUART_PM_STBY_EN_FSUSB;
CyDelayUs(USBUART_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */
#endif /* (CY_PSOC4) */
}
else
{
USBUART_backup.enableState = 0u;
}
CyExitCriticalSection(enableInterrupts);
#if (USBUART_DP_ISR_ACTIVE)
/* Clear active mode Dp interrupt source history. */
(void) USBUART_Dp_ClearInterrupt();
CyIntClearPending(USBUART_DP_INTC_VECT_NUM);
CyIntEnable (USBUART_DP_INTC_VECT_NUM);
#endif /* (USBUART_DP_ISR_ACTIVE). */
}
/*****************************************************************************
* Function Name: _Watchdog_Resume()
******************************************************************************
* Summary:
* Enable the watchdog interrupt.
*
* Parameters:
* None.
*
* Return:
* None.
*
* Note:
*
*****************************************************************************/
void _Watchdog_ResumeInt(void)
{
CyIntEnable(WATCHDOG_INT_VEC_NUM);
}
