offs_t rsp_dasm_one(char *buffer, offs_t pc, UINT32 op)
{
int rs = (op >> 21) & 31;
int rt = (op >> 16) & 31;
int rd = (op >> 11) & 31;
int shift = (op >> 6) & 31;
UINT32 flags = 0;
output = buffer;
switch (op >> 26)
{
case 0x00: // SPECIAL
{
switch (op & 0x3f)
{
case 0x00:
{
if (op == 0)
{
print("nop");
}
else
{
print("sll %s, %s, %d", reg[rd], reg[rt], shift);
}
break;
}
case 0x02: print("srl %s, %s, %d", reg[rd], reg[rt], shift); break;
case 0x03: print("sra %s, %s, %d", reg[rd], reg[rt], shift); break;
case 0x04: print("sllv %s, %s, %s", reg[rd], reg[rt], reg[rs]); break;
case 0x06: print("srlv %s, %s, %s", reg[rd], reg[rt], reg[rs]); break;
case 0x07: print("srav %s, %s, %s", reg[rd], reg[rt], reg[rs]); break;
case 0x08: print("jr %s", reg[rs]); if (rs == 31) flags = DASMFLAG_STEP_OUT; break;
case 0x09:
{
if (rd == 31)
{
print("jalr %s", reg[rs]);
}
else
{
print("jalr %s, %s", reg[rs], reg[rd]);
}
flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1);
break;
}
case 0x0d: print("break"); flags = DASMFLAG_STEP_OVER; break;
case 0x20: print("add %s, %s, %s", reg[rd], reg[rs], reg[rt]); break;
case 0x21: print("addu %s, %s, %s", reg[rd], reg[rs], reg[rt]); break;
case 0x22: print("sub %s, %s, %s", reg[rd], reg[rs], reg[rt]); break;
case 0x23: print("subu %s, %s, %s", reg[rd], reg[rs], reg[rt]); break;
case 0x24: print("and %s, %s, %s", reg[rd], reg[rs], reg[rt]); break;
case 0x25: print("or %s, %s, %s", reg[rd], reg[rs], reg[rt]); break;
case 0x26: print("xor %s, %s, %s", reg[rd], reg[rs], reg[rt]); break;
case 0x27: print("nor %s, %s, %s", reg[rd], reg[rs], reg[rt]); break;
case 0x2a: print("slt %s, %s, %s", reg[rd], reg[rs], reg[rt]); break;
case 0x2b: print("sltu %s, %s, %s", reg[rd], reg[rs], reg[rt]); break;
default: print("???"); break;
}
break;
}
case 0x01: // REGIMM
{
switch ((op >> 16) & 0x1f)
{
case 0x00: print("bltz %s, $%08X", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x01: print("bgez %s, $%08X", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x10: print("bltzal %s, $%08X", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x11: print("bgezal %s, $%08X", reg[rs], pc + 4 + ((INT16)op << 2)); break;
default: print("???"); break;
}
break;
}
case 0x02: print("j $%08X", (op & 0x03ffffff) << 2); break;
case 0x03: print("jal $%08X", (op & 0x03ffffff) << 2); break;
case 0x04: print("beq %s, %s, $%08X", reg[rs], reg[rt], pc + 4 + ((INT16)(op) << 2)); break;
case 0x05: print("bne %s, %s, $%08X", reg[rs], reg[rt], pc + 4 + ((INT16)(op) << 2)); break;
case 0x06: print("blez %s, $%08X", reg[rs], pc + 4 + ((INT16)(op) << 2)); break;
case 0x07: print("bgtz %s, $%08X", reg[rs], pc + 4 + ((INT16)(op) << 2)); break;
case 0x08: print("addi %s, %s, %s", reg[rt], reg[rs], signed_imm16(op)); break;
case 0x09: print("addiu %s, %s, %s", reg[rt], reg[rs], signed_imm16(op)); break;
case 0x0a: print("slti %s, %s, %s", reg[rt], reg[rs], signed_imm16(op)); break;
case 0x0b: print("sltiu %s, %s, %s", reg[rt], reg[rs], signed_imm16(op)); break;
case 0x0c: print("andi %s, %s, $%04X", reg[rt], reg[rs], (UINT16)(op)); break;
case 0x0d: print("ori %s, %s, $%04X", reg[rt], reg[rs], (UINT16)(op)); break;
case 0x0e: print("xori %s, %s, $%04X", reg[rt], reg[rs], (UINT16)(op)); break;
case 0x0f: print("lui %s, %s, $%04X", reg[rt], reg[rs], (UINT16)(op)); break;
case 0x10: disasm_cop0(op); break;
case 0x12: disasm_cop2(op); break;
case 0x20: print("lb %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break;
case 0x21: print("lh %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break;
case 0x23: print("lw %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break;
case 0x24: print("lbu %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break;
case 0x25: print("lhu %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break;
case 0x28: print("sb %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break;
case 0x29: print("sh %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break;
case 0x2b: print("sw %s, %s(%s)", reg[rt], signed_imm16(op), reg[rs]); break;
case 0x32: disasm_lwc2(op); break;
case 0x3a: disasm_swc2(op); break;
default: print("???"); break;
}
return 4 | flags | DASMFLAG_SUPPORTED;
}
unsigned dasmmips3(char *buffer, unsigned pc, UINT32 op)
{
int rs = (op >> 21) & 31;
int rt = (op >> 16) & 31;
int rd = (op >> 11) & 31;
int shift = (op >> 6) & 31;
UINT32 flags = 0;
switch (op >> 26)
{
case 0x00: /* SPECIAL */
switch (op & 63)
{
case 0x00: if (op == 0)
sprintf(buffer, "nop");
else
sprintf(buffer, "sll %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x01: sprintf(buffer, "mov%c %s,%s,%d", ((op >> 16) & 1) ? 't' : 'f', reg[rd], reg[rs], (op >> 18) & 7); break;
case 0x02: sprintf(buffer, "srl %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x03: sprintf(buffer, "sra %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x04: sprintf(buffer, "sllv %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x06: sprintf(buffer, "srlv %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x07: sprintf(buffer, "srav %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x08: sprintf(buffer, "jr %s", reg[rs]); if (rs == 31) flags = DASMFLAG_STEP_OUT; break;
case 0x09: if (rd == 31)
sprintf(buffer, "jalr %s", reg[rs]);
else
sprintf(buffer, "jalr %s,%s", reg[rs], reg[rd]); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
case 0x0a: sprintf(buffer, "movz %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x0b: sprintf(buffer, "movn %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x0c: sprintf(buffer, "syscall"); flags = DASMFLAG_STEP_OVER; break;
case 0x0d: sprintf(buffer, "break"); flags = DASMFLAG_STEP_OVER; break;
case 0x0f: sprintf(buffer, "sync"); break;
case 0x10: sprintf(buffer, "mfhi %s", reg[rd]); break;
case 0x11: sprintf(buffer, "mthi %s", reg[rs]); break;
case 0x12: sprintf(buffer, "mflo %s", reg[rd]); break;
case 0x13: sprintf(buffer, "mtlo %s", reg[rs]); break;
case 0x14: sprintf(buffer, "dsllv %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x16: sprintf(buffer, "dsrlv %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x17: sprintf(buffer, "dsrav %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x18: sprintf(buffer, "mult %s,%s", reg[rs], reg[rt]); break;
case 0x19: sprintf(buffer, "multu %s,%s", reg[rs], reg[rt]); break;
case 0x1a: sprintf(buffer, "div %s,%s", reg[rs], reg[rt]); break;
case 0x1b: sprintf(buffer, "divu %s,%s", reg[rs], reg[rt]); break;
case 0x1c: sprintf(buffer, "dmult %s,%s", reg[rs], reg[rt]); break;
case 0x1d: sprintf(buffer, "dmultu %s,%s", reg[rs], reg[rt]); break;
case 0x1e: sprintf(buffer, "ddiv %s,%s", reg[rs], reg[rt]); break;
case 0x1f: sprintf(buffer, "ddivu %s,%s", reg[rs], reg[rt]); break;
case 0x20: sprintf(buffer, "add %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x21: sprintf(buffer, "addu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x22: sprintf(buffer, "sub %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x23: sprintf(buffer, "subu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x24: sprintf(buffer, "and %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x25: sprintf(buffer, "or %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x26: sprintf(buffer, "xor %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x27: sprintf(buffer, "nor %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2a: sprintf(buffer, "slt %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2b: sprintf(buffer, "sltu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2c: sprintf(buffer, "dadd %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2d: sprintf(buffer, "daddu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2e: sprintf(buffer, "dsub %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2f: sprintf(buffer, "dsubu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x30: sprintf(buffer, "tge %s,%s", reg[rs], reg[rt]); flags = DASMFLAG_STEP_OVER; break;
case 0x31: sprintf(buffer, "tgeu %s,%s", reg[rs], reg[rt]); flags = DASMFLAG_STEP_OVER; break;
case 0x32: sprintf(buffer, "tlt %s,%s", reg[rs], reg[rt]); flags = DASMFLAG_STEP_OVER; break;
case 0x33: sprintf(buffer, "tltu %s,%s", reg[rs], reg[rt]); flags = DASMFLAG_STEP_OVER; break;
case 0x34: sprintf(buffer, "teq %s,%s", reg[rs], reg[rt]); flags = DASMFLAG_STEP_OVER; break;
case 0x36: sprintf(buffer, "tne %s,%s", reg[rs], reg[rt]) ;flags = DASMFLAG_STEP_OVER; break;
case 0x38: sprintf(buffer, "dsll %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x3a: sprintf(buffer, "dsrl %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x3b: sprintf(buffer, "dsra %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x3c: sprintf(buffer, "dsll %s,%s,%d", reg[rd], reg[rt], shift+32); break;
case 0x3e: sprintf(buffer, "dsrl %s,%s,%d", reg[rd], reg[rt], shift+32); break;
case 0x3f: sprintf(buffer, "dsra %s,%s,%d", reg[rd], reg[rt], shift+32); break;
default: sprintf(buffer, "dc.l $%08x [invalid]", op); break;
}
break;
case 0x01: /* REGIMM */
switch ((op >> 16) & 31)
{
case 0x00: sprintf(buffer, "bltz %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x01: sprintf(buffer, "bgez %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x02: sprintf(buffer, "bltzl %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x03: sprintf(buffer, "bgezl %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x08: sprintf(buffer, "tgei %s,%s", reg[rs], signed_16bit(op)); flags = DASMFLAG_STEP_OVER; break;
case 0x09: sprintf(buffer, "tgeiu %s,%s", reg[rs], signed_16bit(op)); flags = DASMFLAG_STEP_OVER; break;
case 0x0a: sprintf(buffer, "tlti %s,%s", reg[rs], signed_16bit(op)); flags = DASMFLAG_STEP_OVER; break;
case 0x0b: sprintf(buffer, "tltiu %s,%s", reg[rs], signed_16bit(op)); flags = DASMFLAG_STEP_OVER; break;
case 0x0c: sprintf(buffer, "teqi %s,%s", reg[rs], signed_16bit(op)); flags = DASMFLAG_STEP_OVER; break;
case 0x0e: sprintf(buffer, "tnei %s,%s", reg[rs], signed_16bit(op)); flags = DASMFLAG_STEP_OVER; break;
case 0x10: sprintf(buffer, "bltzal %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
case 0x11: sprintf(buffer, "bgezal %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
case 0x12: sprintf(buffer, "bltzall %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
case 0x13: sprintf(buffer, "bgezall %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
default: sprintf(buffer, "dc.l $%08x [invalid]", op); break;
}
break;
case 0x02: sprintf(buffer, "j $%08x", (pc & 0xf0000000) | ((op & 0x03ffffff) << 2)); break;
case 0x03: sprintf(buffer, "jal $%08x", (pc & 0xf0000000) | ((op & 0x03ffffff) << 2)); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
case 0x04: if (rs == 0 && rt == 0)
sprintf(buffer, "b $%08x", pc + 4 + ((INT16)op << 2));
else
sprintf(buffer, "beq %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x05: sprintf(buffer, "bne %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x06: sprintf(buffer, "blez %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x07: sprintf(buffer, "bgtz %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x08: sprintf(buffer, "addi %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x09: sprintf(buffer, "addiu %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x0a: sprintf(buffer, "slti %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x0b: sprintf(buffer, "sltiu %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x0c: sprintf(buffer, "andi %s,%s,$%04x", reg[rt], reg[rs], (UINT16)op); break;
case 0x0d: sprintf(buffer, "ori %s,%s,$%04x", reg[rt], reg[rs], (UINT16)op); break;
case 0x0e: sprintf(buffer, "xori %s,%s,$%04x", reg[rt], reg[rs], (UINT16)op); break;
case 0x0f: sprintf(buffer, "lui %s,$%04x", reg[rt], (UINT16)op); break;
case 0x10: flags = dasm_cop0(pc, op, buffer); break;
case 0x11: flags = dasm_cop1(pc, op, buffer); break;
case 0x12: flags = dasm_cop2(pc, op, buffer); break;
case 0x13: flags = dasm_cop1x(pc, op, buffer); break;
case 0x14: sprintf(buffer, "beql %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x15: sprintf(buffer, "bnel %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x16: sprintf(buffer, "blezl %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x17: sprintf(buffer, "bgtzl %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x18: sprintf(buffer, "daddi %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x19: sprintf(buffer, "daddiu %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x1a: sprintf(buffer, "ldl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x1b: sprintf(buffer, "ldr %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x1c: /* IDT-specific opcodes: mad/madu/mul on R4640/4650, msub on RC32364 */
switch (op & 0x1f)
{
case 0: sprintf(buffer, "mad %s,%s", reg[rs], reg[rt]); break;
case 1: sprintf(buffer, "madu %s,%s", reg[rs], reg[rt]); break;
case 2: sprintf(buffer, "mul %s,%s,%s", reg[rs], reg[rt], reg[rd]); break;
case 4: sprintf(buffer, "msub %s,%s", reg[rs], reg[rt]); break;
default:sprintf(buffer, "dc.l $%08x [invalid]", op); break;
}
break;
case 0x20: sprintf(buffer, "lb %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x21: sprintf(buffer, "lh %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x22: sprintf(buffer, "lwl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x23: sprintf(buffer, "lw %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x24: sprintf(buffer, "lbu %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x25: sprintf(buffer, "lhu %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x26: sprintf(buffer, "lwr %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x27: sprintf(buffer, "lwu %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x28: sprintf(buffer, "sb %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x29: sprintf(buffer, "sh %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2a: sprintf(buffer, "swl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2b: sprintf(buffer, "sw %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2c: sprintf(buffer, "sdl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2d: sprintf(buffer, "sdr %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2e: sprintf(buffer, "swr %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2f: sprintf(buffer, "cache %s(%s)", reg[rs], signed_16bit(op)); break;
case 0x30: sprintf(buffer, "ll %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x31: sprintf(buffer, "lwc1 %s,%s(%s)", cpreg[1][rt], signed_16bit(op), reg[rs]); break;
case 0x32: sprintf(buffer, "lwc2 %s,%s(%s)", cpreg[2][rt], signed_16bit(op), reg[rs]); break;
case 0x33: sprintf(buffer, "pref $%x,%s(%s)", rt, signed_16bit(op), reg[rs]); break;
case 0x34: sprintf(buffer, "lld %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x35: sprintf(buffer, "ldc1 %s,%s(%s)", cpreg[1][rt], signed_16bit(op), reg[rs]); break;
case 0x36: sprintf(buffer, "ldc2 %s,%s(%s)", cpreg[2][rt], signed_16bit(op), reg[rs]); break;
case 0x37: sprintf(buffer, "ld %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x38: sprintf(buffer, "sc %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x39: sprintf(buffer, "swc1 %s,%s(%s)", cpreg[1][rt], signed_16bit(op), reg[rs]); break;
case 0x3a: sprintf(buffer, "swc2 %s,%s(%s)", cpreg[2][rt], signed_16bit(op), reg[rs]); break;
case 0x3c: sprintf(buffer, "scd %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x3d: sprintf(buffer, "sdc1 %s,%s(%s)", cpreg[1][rt], signed_16bit(op), reg[rs]); break;
case 0x3e: sprintf(buffer, "sdc2 %s,%s(%s)", cpreg[2][rt], signed_16bit(op), reg[rs]); break;
case 0x3f: sprintf(buffer, "sd %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
default: sprintf(buffer, "dc.l $%08x [invalid]", op); break;
}
return 4 | flags | DASMFLAG_SUPPORTED;
}
unsigned DasmPSXCPU( psxcpu_state *state, char *buffer, UINT32 pc, const UINT8 *opram )
{
UINT32 op;
const UINT8 *oldopram;
UINT32 flags = 0;
oldopram = opram;
op = fetch_op( opram );
opram += 4;
sprintf( buffer, "dw $%08x", op );
switch( INS_OP( op ) )
{
case OP_SPECIAL:
switch( INS_FUNCT( op ) )
{
case FUNCT_SLL:
if( op == 0 )
{
/* the standard nop is "sll zero,zero,$0000" */
sprintf( buffer, "nop" );
}
else
{
sprintf( buffer, "sll %s,%s,$%02x", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], INS_SHAMT( op ) );
}
break;
case FUNCT_SRL:
sprintf( buffer, "srl %s,%s,$%02x", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], INS_SHAMT( op ) );
break;
case FUNCT_SRA:
sprintf( buffer, "sra %s,%s,$%02x", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], INS_SHAMT( op ) );
break;
case FUNCT_SLLV:
sprintf( buffer, "sllv %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ] );
break;
case FUNCT_SRLV:
sprintf( buffer, "srlv %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ] );
break;
case FUNCT_SRAV:
sprintf( buffer, "srav %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ] );
break;
case FUNCT_JR:
sprintf( buffer, "jr %s", s_cpugenreg[ INS_RS( op ) ] );
if( INS_RS( op ) == 31 )
{
flags = DASMFLAG_STEP_OUT;
}
break;
case FUNCT_JALR:
sprintf( buffer, "jalr %s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ] );
flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA( 1 );
break;
case FUNCT_SYSCALL:
sprintf( buffer, "syscall $%05x", INS_CODE( op ) );
flags = DASMFLAG_STEP_OVER;
break;
case FUNCT_BREAK:
sprintf( buffer, "break $%05x", INS_CODE( op ) );
flags = DASMFLAG_STEP_OVER;
break;
case FUNCT_MFHI:
sprintf( buffer, "mfhi %s", s_cpugenreg[ INS_RD( op ) ] );
break;
case FUNCT_MTHI:
sprintf( buffer, "mthi %s", s_cpugenreg[ INS_RS( op ) ] );
break;
case FUNCT_MFLO:
sprintf( buffer, "mflo %s", s_cpugenreg[ INS_RD( op ) ] );
break;
case FUNCT_MTLO:
sprintf( buffer, "mtlo %s", s_cpugenreg[ INS_RS( op ) ] );
break;
case FUNCT_MULT:
sprintf( buffer, "mult %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_MULTU:
sprintf( buffer, "multu %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_DIV:
sprintf( buffer, "div %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_DIVU:
sprintf( buffer, "divu %s,%s", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_ADD:
sprintf( buffer, "add %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_ADDU:
sprintf( buffer, "addu %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_SUB:
sprintf( buffer, "sub %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_SUBU:
sprintf( buffer, "subu %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_AND:
sprintf( buffer, "and %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_OR:
sprintf( buffer, "or %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_XOR:
sprintf( buffer, "xor %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_NOR:
sprintf( buffer, "nor %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_SLT:
sprintf( buffer, "slt %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
case FUNCT_SLTU:
sprintf( buffer, "sltu %s,%s,%s", s_cpugenreg[ INS_RD( op ) ], s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ] );
break;
}
break;
case OP_REGIMM:
switch( INS_RT_REGIMM( op ) )
{
case RT_BLTZ:
if( INS_RT( op ) == RT_BLTZAL )
{
sprintf( buffer, "bltzal %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( state, pc, op ) );
flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA( 1 );
}
else
{
sprintf( buffer, "bltz %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( state, pc, op ) );
}
break;
case RT_BGEZ:
if( INS_RT( op ) == RT_BGEZAL )
{
sprintf( buffer, "bgezal %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( state, pc, op ) );
flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA( 1 );
}
else
{
sprintf( buffer, "bgez %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( state, pc, op ) );
}
break;
}
break;
case OP_J:
sprintf( buffer, "j $%08x", jump_address( state, pc, op ) );
break;
case OP_JAL:
sprintf( buffer, "jal $%08x", jump_address( state, pc, op ) );
flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA( 1 );
break;
case OP_BEQ:
sprintf( buffer, "beq %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( state, pc, op ) );
break;
case OP_BNE:
sprintf( buffer, "bne %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( state, pc, op ) );
break;
case OP_BLEZ:
sprintf( buffer, "blez %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( state, pc, op ) );
break;
case OP_BGTZ:
sprintf( buffer, "bgtz %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( state, pc, op ) );
break;
case OP_ADDI:
sprintf( buffer, "addi %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
break;
case OP_ADDIU:
sprintf( buffer, "addiu %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
break;
case OP_SLTI:
sprintf( buffer, "slti %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
break;
case OP_SLTIU:
sprintf( buffer, "sltiu %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
break;
case OP_ANDI:
sprintf( buffer, "andi %s,%s,$%04x", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], INS_IMMEDIATE( op ) );
break;
case OP_ORI:
sprintf( buffer, "ori %s,%s,$%04x", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], INS_IMMEDIATE( op ) );
break;
case OP_XORI:
sprintf( buffer, "xori %s,%s,$%04x", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], INS_IMMEDIATE( op ) );
break;
case OP_LUI:
sprintf( buffer, "lui %s,%s", s_cpugenreg[ INS_RT( op ) ], upper_address( op, opram ) );
break;
case OP_COP0:
switch( INS_RS( op ) )
{
case RS_MFC:
sprintf( buffer, "mfc0 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp0genreg[ INS_RD( op ) ] );
break;
case RS_CFC:
sprintf( buffer, "!cfc0 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp0ctlreg[ INS_RD( op ) ] );
break;
case RS_MTC:
sprintf( buffer, "mtc0 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp0genreg[ INS_RD( op ) ] );
break;
case RS_CTC:
sprintf( buffer, "!ctc0 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp0ctlreg[ INS_RD( op ) ] );
break;
case RS_BC:
case RS_BC_ALT:
switch( INS_BC( op ) )
{
case BC_BCF:
sprintf( buffer, "bc0f $%08x", relative_address( state, pc, op ) );
break;
case BC_BCT:
sprintf( buffer, "bc0t $%08x", relative_address( state, pc, op ) );
break;
}
break;
default:
switch( INS_CO( op ) )
{
case 1:
sprintf( buffer, "cop0 $%07x", INS_COFUN( op ) );
switch( INS_CF( op ) )
{
case CF_TLBR:
sprintf( buffer, "!tlbr" );
break;
case CF_TLBWI:
sprintf( buffer, "!tlbwi" );
break;
case CF_TLBWR:
sprintf( buffer, "!tlbwr" );
break;
case CF_TLBP:
sprintf( buffer, "!tlbp" );
break;
case CF_RFE:
sprintf( buffer, "rfe" );
break;
}
break;
}
break;
}
break;
case OP_COP1:
switch( INS_RS( op ) )
{
case RS_MFC:
sprintf( buffer, "mfc1 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp1genreg[ INS_RD( op ) ] );
break;
case RS_CFC:
sprintf( buffer, "cfc1 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp1ctlreg[ INS_RD( op ) ] );
break;
case RS_MTC:
sprintf( buffer, "mtc1 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp1genreg[ INS_RD( op ) ] );
break;
case RS_CTC:
sprintf( buffer, "ctc1 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp1ctlreg[ INS_RD( op ) ] );
break;
case RS_BC:
case RS_BC_ALT:
switch( INS_BC( op ) )
{
case BC_BCF:
sprintf( buffer, "bc1f $%08x", relative_address( state, pc, op ) );
break;
case BC_BCT:
sprintf( buffer, "bc1t $%08x", relative_address( state, pc, op ) );
break;
}
break;
default:
switch( INS_CO( op ) )
{
case 1:
sprintf( buffer, "cop1 $%07x", INS_COFUN( op ) );
break;
}
break;
}
break;
case OP_COP2:
switch( INS_RS( op ) )
{
case RS_MFC:
sprintf( buffer, "mfc2 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp2genreg[ INS_RD( op ) ] );
break;
case RS_CFC:
sprintf( buffer, "cfc2 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp2ctlreg[ INS_RD( op ) ] );
break;
case RS_MTC:
sprintf( buffer, "mtc2 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp2genreg[ INS_RD( op ) ] );
break;
case RS_CTC:
sprintf( buffer, "ctc2 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp2ctlreg[ INS_RD( op ) ] );
break;
case RS_BC:
case RS_BC_ALT:
switch( INS_BC( op ) )
{
case BC_BCF:
sprintf( buffer, "bc2f $%08x", relative_address( state, pc, op ) );
break;
case BC_BCT:
sprintf( buffer, "bc2t $%08x", relative_address( state, pc, op ) );
break;
}
break;
default:
switch( INS_CO( op ) )
{
case 1:
sprintf( buffer, "cop2 $%07x", INS_COFUN( op ) );
switch( GTE_FUNCT( op ) )
{
case 0x00: // drop through to RTPS
case 0x01:
sprintf( buffer, "rtps%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x06:
sprintf( buffer, "nclip" );
break;
case 0x0c:
sprintf( buffer, "op%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x10:
sprintf( buffer, "dpcs%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x11:
sprintf( buffer, "intpl%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x12:
sprintf( buffer, "mvmva%s%s %s + %s * %s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ],
s_gtecv[ GTE_CV( op ) ], s_gtemx[ GTE_MX( op ) ], s_gtev[ GTE_V( op ) ] );
break;
case 0x13:
sprintf( buffer, "ncds%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x14:
sprintf( buffer, "cdp%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x16:
sprintf( buffer, "ncdt%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x1b:
sprintf( buffer, "nccs%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x1c:
sprintf( buffer, "cc%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x1e:
sprintf( buffer, "ncs%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x20:
sprintf( buffer, "nct%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x28:
sprintf( buffer, "sqr%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x1a: // end of NCDT
case 0x29:
sprintf( buffer, "dpcl%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x2a:
sprintf( buffer, "dpct%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x2d:
sprintf( buffer, "avsz3" );
break;
case 0x2e:
sprintf( buffer, "avsz4" );
break;
case 0x30:
sprintf( buffer, "rtpt%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x3d:
sprintf( buffer, "gpf%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x3e:
sprintf( buffer, "gpl%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
case 0x3f:
sprintf( buffer, "ncct%s%s", s_gtesf[ GTE_SF( op ) ], s_gtelm[ GTE_LM( op ) ] );
break;
}
}
break;
}
break;
case OP_COP3:
switch( INS_RS( op ) )
{
case RS_MFC:
sprintf( buffer, "mfc3 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp3genreg[ INS_RD( op ) ] );
break;
case RS_CFC:
sprintf( buffer, "cfc3 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp3ctlreg[ INS_RD( op ) ] );
break;
case RS_MTC:
sprintf( buffer, "mtc3 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp3genreg[ INS_RD( op ) ] );
break;
case RS_CTC:
sprintf( buffer, "ctc3 %s,%s", s_cpugenreg[ INS_RT( op ) ], s_cp3ctlreg[ INS_RD( op ) ] );
break;
case RS_BC:
case RS_BC_ALT:
switch( INS_BC( op ) )
{
case BC_BCF:
sprintf( buffer, "bc3f $%08x", relative_address( state, pc, op ) );
break;
case BC_BCT:
sprintf( buffer, "bc3t $%08x", relative_address( state, pc, op ) );
break;
}
break;
default:
switch( INS_CO( op ) )
{
case 1:
sprintf( buffer, "cop3 $%07x", INS_COFUN( op ) );
break;
}
break;
}
break;
case OP_LB:
sprintf( buffer, "lb %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_LH:
sprintf( buffer, "lh %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_LWL:
sprintf( buffer, "lwl %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_LW:
sprintf( buffer, "lw %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_LBU:
sprintf( buffer, "lbu %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_LHU:
sprintf( buffer, "lhu %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_LWR:
sprintf( buffer, "lwr %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_SB:
sprintf( buffer, "sb %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_SH:
sprintf( buffer, "sh %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_SWL:
sprintf( buffer, "swl %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_SW:
sprintf( buffer, "sw %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_SWR:
sprintf( buffer, "swr %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_LWC0:
sprintf( buffer, "lwc0 %s,%s", s_cp0genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_LWC1:
sprintf( buffer, "lwc1 %s,%s", s_cp1genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_LWC2:
sprintf( buffer, "lwc2 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_LWC3:
sprintf( buffer, "lwc3 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_SWC0:
sprintf( buffer, "swc0 %s,%s", s_cp0genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_SWC1:
sprintf( buffer, "swc1 %s,%s", s_cp1genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_SWC2:
sprintf( buffer, "swc2 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
case OP_SWC3:
sprintf( buffer, "swc3 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
break;
}
return ( opram - oldopram ) | flags | DASMFLAG_SUPPORTED;
}
static UINT32 dasm_cop1(UINT32 pc, UINT32 op, char *buffer)
{
static const char *const format_table[] =
{
"?","?","?","?","?","?","?","?","?","?","?","?","?","?","?","?",
"s","d","?","?","w","l","?","?","?","?","?","?","?","?","?","?"
};
const char *fmt = format_table[(op >> 21) & 31];
int ft = (op >> 16) & 31;
int fs = (op >> 11) & 31;
int fd = (op >> 6) & 31;
int rt = (op >> 16) & 31;
int rd = (op >> 11) & 31;
UINT32 flags = 0;
switch ((op >> 21) & 31)
{
case 0x00: sprintf(buffer, "mfc1 %s,%s", reg[rt], cpreg[1][rd]); break;
case 0x01: sprintf(buffer, "dmfc1 %s,%s", reg[rt], cpreg[1][rd]); break;
case 0x02: sprintf(buffer, "cfc1 %s,%s", reg[rt], ccreg[1][rd]); break;
case 0x04: sprintf(buffer, "mtc1 %s,%s", reg[rt], cpreg[1][rd]); break;
case 0x05: sprintf(buffer, "dmtc1 %s,%s", reg[rt], cpreg[1][rd]); break;
case 0x06: sprintf(buffer, "ctc1 %s,%s", reg[rt], ccreg[1][rd]); break;
case 0x08: /* BC */
switch (rt & 3)
{
case 0x00: sprintf(buffer, "bc1f $%08x,%d", pc + 4 + ((INT16)op << 2), (op >> 18) & 7); break;
case 0x01: sprintf(buffer, "bc1t $%08x,%d", pc + 4 + ((INT16)op << 2), (op >> 18) & 7); break;
case 0x02: sprintf(buffer, "bc1fl $%08x,%d", pc + 4 + ((INT16)op << 2), (op >> 18) & 7); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
case 0x03: sprintf(buffer, "bc1tl $%08x,%d", pc + 4 + ((INT16)op << 2), (op >> 18) & 7); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
}
break;
default: /* COP */
switch (op & 0x3f)
{
case 0x00: sprintf(buffer, "add.%s %s,%s,%s", fmt, cpreg[1][fd], cpreg[1][fs], cpreg[1][ft]); break;
case 0x01: sprintf(buffer, "sub.%s %s,%s,%s", fmt, cpreg[1][fd], cpreg[1][fs], cpreg[1][ft]); break;
case 0x02: sprintf(buffer, "mul.%s %s,%s,%s", fmt, cpreg[1][fd], cpreg[1][fs], cpreg[1][ft]); break;
case 0x03: sprintf(buffer, "div.%s %s,%s,%s", fmt, cpreg[1][fd], cpreg[1][fs], cpreg[1][ft]); break;
case 0x04: sprintf(buffer, "sqrt.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x05: sprintf(buffer, "abs.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x06: sprintf(buffer, "mov.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x07: sprintf(buffer, "neg.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x08: sprintf(buffer, "round.l.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x09: sprintf(buffer, "trunc.l.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x0a: sprintf(buffer, "ceil.l.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x0b: sprintf(buffer, "floor.l.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x0c: sprintf(buffer, "round.w.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x0d: sprintf(buffer, "trunc.w.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x0e: sprintf(buffer, "ceil.w.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x0f: sprintf(buffer, "floor.w.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x11: sprintf(buffer, "mov%c.%s %s,%s,%d", ((op >> 16) & 1) ? 't' : 'f', fmt, cpreg[1][fd], cpreg[1][fs], (op >> 18) & 7); break;
case 0x12: sprintf(buffer, "movz.%s %s,%s,%s", fmt, cpreg[1][fd], cpreg[1][fs], reg[rt]); break;
case 0x13: sprintf(buffer, "movn.%s %s,%s,%s", fmt, cpreg[1][fd], cpreg[1][fs], reg[rt]); break;
case 0x15: sprintf(buffer, "recip.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x16: sprintf(buffer, "rsqrt.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x20: sprintf(buffer, "cvt.s.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x21: sprintf(buffer, "cvt.d.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x24: sprintf(buffer, "cvt.w.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x25: sprintf(buffer, "cvt.l.%s %s,%s", fmt, cpreg[1][fd], cpreg[1][fs]); break;
case 0x30: sprintf(buffer, "c.f.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x31: sprintf(buffer, "c.un.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x32: sprintf(buffer, "c.eq.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x33: sprintf(buffer, "c.ueq.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x34: sprintf(buffer, "c.olt.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x35: sprintf(buffer, "c.ult.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x36: sprintf(buffer, "c.ole.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x37: sprintf(buffer, "c.ule.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x38: sprintf(buffer, "c.sf.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x39: sprintf(buffer, "c.ngle.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7);break;
case 0x3a: sprintf(buffer, "c.seq.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x3b: sprintf(buffer, "c.ngl.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x3c: sprintf(buffer, "c.lt.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x3d: sprintf(buffer, "c.nge.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x3e: sprintf(buffer, "c.le.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
case 0x3f: sprintf(buffer, "c.ngt.%s %s,%s,%d", fmt, cpreg[1][fs], cpreg[1][ft], (op >> 8) & 7); break;
default: sprintf(buffer, "cop1 $%07x", op & 0x01ffffff); break;
}
break;
}
return flags;
}
static unsigned dasmr3k(char *buffer, unsigned pc, UINT32 op)
{
int rs = (op >> 21) & 31;
int rt = (op >> 16) & 31;
int rd = (op >> 11) & 31;
int shift = (op >> 6) & 31;
UINT32 flags = 0;
switch (op >> 26)
{
case 0x00: /* SPECIAL */
switch (op & 63)
{
case 0x00: if (op == 0)
sprintf(buffer, "nop");
else
sprintf(buffer, "sll %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x02: sprintf(buffer, "srl %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x03: sprintf(buffer, "sra %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x04: sprintf(buffer, "sllv %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x06: sprintf(buffer, "srlv %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x07: sprintf(buffer, "srav %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x08: sprintf(buffer, "jr %s", reg[rs]); if (rs == 31) flags = DASMFLAG_STEP_OUT; break;
case 0x09: if (rd == 31)
sprintf(buffer, "jalr %s", reg[rs]);
else
sprintf(buffer, "jalr %s,%s", reg[rs], reg[rd]); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
case 0x0c: sprintf(buffer, "syscall"); flags = DASMFLAG_STEP_OVER; break;
case 0x0d: sprintf(buffer, "break"); flags = DASMFLAG_STEP_OVER; break;
case 0x0f: sprintf(buffer, "sync [invalid]"); break;
case 0x10: sprintf(buffer, "mfhi %s", reg[rd]); break;
case 0x11: sprintf(buffer, "mthi %s", reg[rs]); break;
case 0x12: sprintf(buffer, "mflo %s", reg[rd]); break;
case 0x13: sprintf(buffer, "mtlo %s", reg[rs]); break;
case 0x18: sprintf(buffer, "mult %s,%s", reg[rs], reg[rt]); break;
case 0x19: sprintf(buffer, "multu %s,%s", reg[rs], reg[rt]); break;
case 0x1a: sprintf(buffer, "div %s,%s", reg[rs], reg[rt]); break;
case 0x1b: sprintf(buffer, "divu %s,%s", reg[rs], reg[rt]); break;
case 0x20: sprintf(buffer, "add %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x21: sprintf(buffer, "addu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x22: sprintf(buffer, "sub %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x23: sprintf(buffer, "subu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x24: sprintf(buffer, "and %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x25: sprintf(buffer, "or %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x26: sprintf(buffer, "xor %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x27: sprintf(buffer, "nor %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2a: sprintf(buffer, "slt %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2b: sprintf(buffer, "sltu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x30: sprintf(buffer, "teq [invalid]"); break;
case 0x31: sprintf(buffer, "tgeu [invalid]"); break;
case 0x32: sprintf(buffer, "tlt [invalid]"); break;
case 0x33: sprintf(buffer, "tltu [invalid]"); break;
case 0x34: sprintf(buffer, "tge [invalid]"); break;
case 0x36: sprintf(buffer, "tne [invalid]"); break;
default: sprintf(buffer, "dc.l $%08x [invalid]", op); break;
}
break;
case 0x01: /* REGIMM */
switch ((op >> 16) & 31)
{
case 0x00: sprintf(buffer, "bltz %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x01: sprintf(buffer, "bgez %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x02: sprintf(buffer, "bltzl [invalid]"); break;
case 0x03: sprintf(buffer, "bgezl [invalid]"); break;
case 0x08: sprintf(buffer, "tgei [invalid]"); break;
case 0x09: sprintf(buffer, "tgeiu [invalid]"); break;
case 0x0a: sprintf(buffer, "tlti [invalid]"); break;
case 0x0b: sprintf(buffer, "tltiu [invalid]"); break;
case 0x0c: sprintf(buffer, "teqi [invalid]"); break;
case 0x0e: sprintf(buffer, "tnei [invalid]"); break;
case 0x10: sprintf(buffer, "bltzal %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
case 0x11: sprintf(buffer, "bgezal %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
case 0x12: sprintf(buffer, "bltzall [invalid]"); break;
case 0x13: sprintf(buffer, "bgezall [invalid]"); break;
default: sprintf(buffer, "dc.l $%08x [invalid]", op); break;
}
break;
case 0x02: sprintf(buffer, "j $%08x", (pc & 0xf0000000) | ((op & 0x0fffffff) << 2)); break;
case 0x03: sprintf(buffer, "jal $%08x", (pc & 0xf0000000) | ((op & 0x0fffffff) << 2)); flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1); break;
case 0x04: if (rs == 0 && rt == 0)
sprintf(buffer, "b $%08x", pc + 4 + ((INT16)op << 2));
else
sprintf(buffer, "beq %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x05: sprintf(buffer, "bne %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x06: sprintf(buffer, "blez %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x07: sprintf(buffer, "bgtz %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x08: sprintf(buffer, "addi %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x09: sprintf(buffer, "addiu %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x0a: sprintf(buffer, "slti %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x0b: sprintf(buffer, "sltiu %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x0c: sprintf(buffer, "andi %s,%s,$%04x", reg[rt], reg[rs], (UINT16)op); break;
case 0x0d: sprintf(buffer, "ori %s,%s,$%04x", reg[rt], reg[rs], (UINT16)op); break;
case 0x0e: sprintf(buffer, "xori %s,%s,$%04x", reg[rt], reg[rs], (UINT16)op); break;
case 0x0f: sprintf(buffer, "lui %s,$%04x", reg[rt], (UINT16)op); break;
case 0x10: flags = dasm_cop(pc, 0, op, buffer); break;
case 0x11: flags = dasm_cop1(pc, op, buffer); break;
case 0x12: flags = dasm_cop(pc, 2, op, buffer); break;
case 0x13: flags = dasm_cop(pc, 3, op, buffer); break;
case 0x14: sprintf(buffer, "beql [invalid]"); break;
case 0x15: sprintf(buffer, "bnel [invalid]"); break;
case 0x16: sprintf(buffer, "blezl [invalid]"); break;
case 0x17: sprintf(buffer, "bgtzl [invalid]"); break;
case 0x20: sprintf(buffer, "lb %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x21: sprintf(buffer, "lh %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x22: sprintf(buffer, "lwl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x23: sprintf(buffer, "lw %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x24: sprintf(buffer, "lbu %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x25: sprintf(buffer, "lhu %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x26: sprintf(buffer, "lwr %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x28: sprintf(buffer, "sb %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x29: sprintf(buffer, "sh %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2a: sprintf(buffer, "swl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2b: sprintf(buffer, "sw %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2e: sprintf(buffer, "swr %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2f: sprintf(buffer, "cache [invalid]"); break;
case 0x30: sprintf(buffer, "ll [invalid]"); break;
case 0x31: sprintf(buffer, "lwc1 %s,%s(%s)", cpreg[1][rt], signed_16bit(op), reg[rs]); break;
case 0x32: sprintf(buffer, "lwc2 %s,%s(%s)", cpreg[2][rt], signed_16bit(op), reg[rs]); break;
case 0x33: sprintf(buffer, "lwc3 %s,%s(%s)", cpreg[3][rt], signed_16bit(op), reg[rs]); break;
case 0x34: sprintf(buffer, "ldc0 [invalid]"); break;
case 0x35: sprintf(buffer, "ldc1 [invalid]"); break;
case 0x36: sprintf(buffer, "ldc2 [invalid]"); break;
case 0x37: sprintf(buffer, "ldc3 [invalid]"); break;
case 0x38: sprintf(buffer, "sc [invalid]"); break;
case 0x39: sprintf(buffer, "swc1 %s,%s(%s)", cpreg[1][rt], signed_16bit(op), reg[rs]); break;
case 0x3a: sprintf(buffer, "swc2 %s,%s(%s)", cpreg[2][rt], signed_16bit(op), reg[rs]); break;
case 0x3b: sprintf(buffer, "swc3 %s,%s(%s)", cpreg[3][rt], signed_16bit(op), reg[rs]); break;
case 0x3c: sprintf(buffer, "sdc0 [invalid]"); break;
case 0x3d: sprintf(buffer, "sdc1 [invalid]"); break;
case 0x3e: sprintf(buffer, "sdc2 [invalid]"); break;
case 0x3f: sprintf(buffer, "sdc3 [invalid]"); break;
default: sprintf(buffer, "dc.l $%08x [invalid]", op); break;
}
return 4 | flags | DASMFLAG_SUPPORTED;
}
static UINT32 op1011(char *buffer, UINT32 pc, UINT16 opcode)
{
sprintf(buffer, "BSR $%08X", SIGNX12(opcode & 0xfff) * 2 + pc + 2);
return DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1);
}
static UINT32 op0100(char *buffer, UINT32 pc, UINT16 opcode)
{
UINT32 flags = 0;
switch(opcode & 0x3F)
{
case 0x00:
sprintf(buffer, "SHLL %s", regname[Rn]);
break;
case 0x01:
sprintf(buffer, "SHLR %s", regname[Rn]);
break;
case 0x02:
sprintf(buffer, "STS.L MACH,@-%s", regname[Rn]);
break;
case 0x03:
sprintf(buffer, "STC.L SR,@-%s", regname[Rn]);
break;
case 0x04:
sprintf(buffer, "ROTL %s", regname[Rn]);
break;
case 0x05:
sprintf(buffer, "ROTR %s", regname[Rn]);
break;
case 0x06:
sprintf(buffer, "LDS.L @%s+,MACH", regname[Rn]);
break;
case 0x07:
sprintf(buffer, "LDC.L @%s+,SR", regname[Rn]);
break;
case 0x08:
sprintf(buffer, "SHLL2 %s", regname[Rn]);
break;
case 0x09:
sprintf(buffer, "SHLR2 %s", regname[Rn]);
break;
case 0x0a:
sprintf(buffer, "LDS %s,MACH", regname[Rn]);
break;
case 0x0b:
sprintf(buffer, "JSR %s", regname[Rn]);
flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1);
break;
case 0x0e:
sprintf(buffer, "LDC %s,SR", regname[Rn]);
break;
case 0x10:
sprintf(buffer, "DT %s", regname[Rn]);
break;
case 0x11:
sprintf(buffer, "CMP/PZ %s", regname[Rn]);
break;
case 0x12:
sprintf(buffer, "STS.L MACL,@-%s", regname[Rn]);
break;
case 0x13:
sprintf(buffer, "STC.L GBR,@-%s", regname[Rn]);
break;
case 0x15:
sprintf(buffer, "CMP/PL %s", regname[Rn]);
break;
case 0x16:
sprintf(buffer, "LDS.L @%s+,MACL", regname[Rn]);
break;
case 0x17:
sprintf(buffer, "LDC.L @%s+,GBR", regname[Rn]);
break;
case 0x18:
sprintf(buffer, "SHLL8 %s", regname[Rn]);
break;
case 0x19:
sprintf(buffer, "SHLR8 %s", regname[Rn]);
break;
case 0x1a:
sprintf(buffer, "LDS %s,MACL", regname[Rn]);
break;
case 0x1b:
sprintf(buffer, "TAS %s", regname[Rn]);
break;
case 0x1e:
sprintf(buffer, "LDC %s,GBR", regname[Rn]);
break;
case 0x20:
sprintf(buffer, "SHAL %s", regname[Rn]);
break;
case 0x21:
sprintf(buffer, "SHAR %s", regname[Rn]);
break;
case 0x22:
sprintf(buffer, "STS.L PR,@-%s", regname[Rn]);
break;
case 0x23:
sprintf(buffer, "STC.L VBR,@-%s", regname[Rn]);
break;
case 0x24:
sprintf(buffer, "ROTCL %s", regname[Rn]);
break;
case 0x25:
sprintf(buffer, "ROTCR %s", regname[Rn]);
break;
case 0x26:
sprintf(buffer, "LDS.L @%s+,PR", regname[Rn]);
break;
case 0x27:
sprintf(buffer, "LDC.L @%s+,VBR", regname[Rn]);
break;
case 0x28:
sprintf(buffer, "SHLL16 %s", regname[Rn]);
break;
case 0x29:
sprintf(buffer, "SHLR16 %s", regname[Rn]);
break;
case 0x2a:
sprintf(buffer, "LDS %s,PR", regname[Rn]);
break;
case 0x2b:
sprintf(buffer, "JMP %s", regname[Rn]);
break;
case 0x2e:
sprintf(buffer, "LDC %s,VBR", regname[Rn]);
break;
default:
if ((opcode & 15) == 15)
sprintf(buffer, "MAC.W @%s+,@%s+", regname[Rm], regname[Rn]);
else
sprintf(buffer, "?????? $%04X", opcode);
}
return flags;
}
static UINT32 op0100(char *buffer, UINT32 pc, UINT16 opcode)
{
UINT32 flags = 0;
switch (opcode & 0xF)
{
case 0x0:
switch (opcode & 0x30)
{
case 0x00:
sprintf(buffer, "SHLL %s", regname[Rn]); break;
case 0x10:
sprintf(buffer, "DT %s", regname[Rn]); break;
case 0x20:
sprintf(buffer, "SHAL %s", regname[Rn]); break;
}
break;
case 0x1:
switch (opcode & 0x30)
{
case 0x00:
sprintf(buffer, "SHLR %s", regname[Rn]); break;
case 0x10:
sprintf(buffer, "CMP/PZ %s", regname[Rn]); break;
case 0x20:
sprintf(buffer, "SHAR %s", regname[Rn]); break;
}
break;
case 0x2:
switch (opcode & 0xF0)
{
case 0x00:
sprintf(buffer, "STS.L MACH,@-%s", regname[Rn]); break;
case 0x10:
sprintf(buffer, "STS.L MACL,@-%s", regname[Rn]); break;
case 0x20:
sprintf(buffer, "STS.L PR,@-%s", regname[Rn]); break;
case 0x30:
sprintf(buffer, "STC.L SGR,@-%s", regname[Rn]); break;
case 0x50:
sprintf(buffer, "STS.L FPUL,@-%s", regname[Rn]); break;
case 0x60:
sprintf(buffer, "STS.L FPSCR,@-%s", regname[Rn]); break;
case 0xF0:
sprintf(buffer, "STC.L DBR,@-%s", regname[Rn]); break;
}
break;
case 0x3:
if (opcode & 0x80) {
sprintf(buffer, "STC.L %s_BANK,@-%s", regname[(Rm) & 7],regname[Rn]);
return flags;
}
switch (opcode & 0x70)
{
case 0x00:
sprintf(buffer, "STC.L SR,@-%s", regname[Rn]); break;
case 0x10:
sprintf(buffer, "STC.L GBR,@-%s", regname[Rn]); break;
case 0x20:
sprintf(buffer, "STC.L VBR,@-%s", regname[Rn]); break;
case 0x30:
sprintf(buffer, "STC.L SSR,@-%s", regname[Rn]); break;
case 0x40:
sprintf(buffer, "STC.L SPC,@-%s", regname[Rn]); break;
}
break;
case 0x4:
switch (opcode & 0x30)
{
case 0x00:
sprintf(buffer, "ROTL %s", regname[Rn]); break;
case 0x20:
sprintf(buffer, "ROTCL %s", regname[Rn]); break;
}
break;
case 0x5:
switch (opcode & 0x30)
{
case 0x00:
sprintf(buffer, "ROTR %s", regname[Rn]); break;
case 0x10:
sprintf(buffer, "CMP/PL %s", regname[Rn]); break;
case 0x20:
sprintf(buffer, "ROTCR %s", regname[Rn]); break;
}
break;
case 0x6:
switch (opcode & 0xF0)
{
case 0x00:
sprintf(buffer, "LDS.L @%s+,MACH", regname[Rn]); break;
case 0x10:
sprintf(buffer, "LDS.L @%s+,MACL", regname[Rn]); break;
case 0x20:
sprintf(buffer, "LDS.L @%s+,PR", regname[Rn]); break;
case 0x50:
sprintf(buffer, "LDS.L @%s+,FPUL", regname[Rn]); break;
case 0x60:
sprintf(buffer, "LDS.L @%s+,FPSCR", regname[Rn]); break;
case 0xF0:
sprintf(buffer, "LDC.L @%s+,DBR", regname[Rn]); break;
}
break;
case 0x7:
if (opcode & 0x80) {
sprintf(buffer, "LDC.L @%s+,%s_BANK", regname[Rn],regname[(Rm) & 7]);
return flags;
}
switch (opcode & 0x70)
{
case 0x00:
sprintf(buffer, "LDC.L @%s+,SR", regname[Rn]); break;
case 0x10:
sprintf(buffer, "LDC.L @%s+,GBR", regname[Rn]); break;
case 0x20:
sprintf(buffer, "LDC.L @%s+,VBR", regname[Rn]); break;
case 0x30:
sprintf(buffer, "LDC.L @%s+,SSR", regname[Rn]); break;
case 0x40:
sprintf(buffer, "LDC.L @%s+,SPC", regname[Rn]); break;
}
break;
case 0x8:
switch (opcode & 0x30)
{
case 0x00:
sprintf(buffer, "SHLL2 %s", regname[Rn]); break;
case 0x10:
sprintf(buffer, "SHLL8 %s", regname[Rn]); break;
case 0x20:
sprintf(buffer, "SHLL16 %s", regname[Rn]); break;
}
break;
case 0x9:
switch (opcode & 0x30)
{
case 0x00:
sprintf(buffer, "SHLR2 %s", regname[Rn]); break;
case 0x10:
sprintf(buffer, "SHLR8 %s", regname[Rn]); break;
case 0x20:
sprintf(buffer, "SHLR16 %s", regname[Rn]); break;
}
break;
case 0xA:
switch (opcode & 0xF0)
{
case 0x00:
sprintf(buffer, "LDS %s,MACH", regname[Rn]); break;
case 0x10:
sprintf(buffer, "LDS %s,MACL", regname[Rn]); break;
case 0x20:
sprintf(buffer, "LDS %s,PR", regname[Rn]); break;
case 0x50:
sprintf(buffer, "LDS %s,FPUL", regname[Rn]); break;
case 0x60:
sprintf(buffer, "LDS %s,FPSCR", regname[Rn]); break;
case 0xF0:
sprintf(buffer, "LDC %s,DBR", regname[Rn]); break;
}
break;
case 0xB:
switch (opcode & 0x30)
{
case 0x00:
sprintf(buffer, "JSR %s", regname[Rn]);
flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA(1);
break;
case 0x10:
sprintf(buffer, "TAS %s", regname[Rn]); break;
case 0x20:
sprintf(buffer, "JMP %s", regname[Rn]); break;
}
break;
case 0xC:
sprintf(buffer, "SHAD %s,%s", regname[Rm], regname[Rn]); break;
case 0xD:
sprintf(buffer, "SHLD %s,%s", regname[Rm], regname[Rn]); break;
case 0xE:
if (opcode & 0x80) {
sprintf(buffer, "LDC %s,%s_BANK", regname[Rn],regname[(Rm) & 7]);
return flags;
}
switch (opcode & 0x70)
{
case 0x00:
sprintf(buffer, "LDC %s,SR", regname[Rn]); break;
case 0x10:
sprintf(buffer, "LDC %s,GBR", regname[Rn]); break;
case 0x20:
sprintf(buffer, "LDC %s,VBR", regname[Rn]); break;
case 0x30:
sprintf(buffer, "LDC %s,SSR", regname[Rn]); break;
case 0x40:
sprintf(buffer, "LDC %s,SPC", regname[Rn]); break;
}
break;
case 0xF:
sprintf(buffer, "MAC.W @%s+,@%s+", regname[Rm], regname[Rn]); break;
}
return flags;
}
