pagesize = 0;
s->mem_oob = 0;
}
} else {
pagesize += 1 << s->page_shift;
}
if (pagesize) {
s->storage = (uint8_t *) memset(g_malloc(s->pages * pagesize),
0xff, s->pages * pagesize);
}
/* Give s->ioaddr a sane value in case we save state before it is used. */
s->ioaddr = s->io;
}
static Property nand_properties[] = {
DEFINE_PROP_UINT8("manufacturer_id", NANDFlashState, manf_id, 0),
DEFINE_PROP_UINT8("chip_id", NANDFlashState, chip_id, 0),
DEFINE_PROP_DRIVE("drive", NANDFlashState, bdrv),
DEFINE_PROP_END_OF_LIST(),
};
static void nand_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = nand_realize;
dc->reset = nand_reset;
dc->vmsd = &vmstate_nand;
dc->props = nand_properties;
}
static PCIDeviceInfo xio3130_downstream_info = {
.qdev.name = "xio3130-downstream",
.qdev.desc = "TI X3130 Downstream Port of PCI Express Switch",
.qdev.size = sizeof(PCIESlot),
.qdev.reset = xio3130_downstream_reset,
.qdev.vmsd = &vmstate_xio3130_downstream,
.is_express = 1,
.is_bridge = 1,
.config_write = xio3130_downstream_write_config,
.init = xio3130_downstream_initfn,
.exit = xio3130_downstream_exitfn,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
/* TODO: AER */
DEFINE_PROP_END_OF_LIST(),
}
};
static void xio3130_downstream_register(void)
{
pci_qdev_register(&xio3130_downstream_info);
}
device_init(xio3130_downstream_register);
/*
}
static const VMStateDescription vmstate_xilinx_spi = {
.name = "xilinx_spi",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_FIFO8(tx_fifo, XilinxSPI),
VMSTATE_FIFO8(rx_fifo, XilinxSPI),
VMSTATE_UINT32_ARRAY(regs, XilinxSPI, R_MAX),
VMSTATE_END_OF_LIST()
}
};
static Property xilinx_spi_properties[] = {
DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
DEFINE_PROP_END_OF_LIST(),
};
static void xilinx_spi_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = xilinx_spi_init;
dc->reset = xlx_spi_reset;
dc->props = xilinx_spi_properties;
dc->vmsd = &vmstate_xilinx_spi;
}
static const TypeInfo xilinx_spi_info = {
static const VMStateDescription vmstate_xio3130_upstream = {
.name = "xio3130-express-upstream-port",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_PCIE_DEVICE(br.dev, PCIEPort),
VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log,
PCIEAERLog),
VMSTATE_END_OF_LIST()
}
};
static Property xio3130_upstream_properties[] = {
DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max,
PCIE_AER_LOG_MAX_DEFAULT),
DEFINE_PROP_END_OF_LIST(),
};
static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->is_express = 1;
k->is_bridge = 1;
k->config_write = xio3130_upstream_write_config;
k->init = xio3130_upstream_initfn;
k->exit = xio3130_upstream_exitfn;
static const VMStateDescription vmstate_dp8393x = {
.name = "dp8393x",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField []) {
VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
VMSTATE_END_OF_LIST()
}
};
static Property dp8393x_properties[] = {
DEFINE_NIC_PROPERTIES(dp8393xState, conf),
DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr),
DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void dp8393x_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
dc->realize = dp8393x_realize;
dc->reset = dp8393x_reset;
dc->vmsd = &vmstate_dp8393x;
dc->props = dp8393x_properties;
/* Reason: dma_mr property can't be set */
dc->cannot_instantiate_with_device_add_yet = true;
}
}
static const VMStateDescription vmstate_mb_cpu = {
.name = "cpu",
.unmigratable = 1,
};
static Property mb_properties[] = {
DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
false),
/* If use-fpu > 0 - FPU is enabled
* If use-fpu = 2 - Floating point conversion and square root instructions
* are enabled
*/
DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
/* If use-hw-mul > 0 - Multiplier is enabled
* If use-hw-mul = 2 - 64-bit multiplier is enabled
*/
DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
false),
DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
DEFINE_PROP_END_OF_LIST(),
pci_conf[PCI_INTERRUPT_PIN] = 1;
memory_region_init_io(&d->mmio, NULL, &xen_pv_mmio_ops, d,
"mmio", d->size);
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
&d->mmio);
return 0;
}
static Property xen_pv_props[] = {
DEFINE_PROP_UINT16("vendor-id", XenPVDevice, vendor_id, PCI_VENDOR_ID_XEN),
DEFINE_PROP_UINT16("device-id", XenPVDevice, device_id, 0xffff),
DEFINE_PROP_UINT8("revision", XenPVDevice, revision, 0x01),
DEFINE_PROP_UINT32("size", XenPVDevice, size, 0x400000),
DEFINE_PROP_END_OF_LIST()
};
static void xen_pv_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = xen_pv_init;
k->class_id = PCI_CLASS_SYSTEM_OTHER;
dc->desc = "Xen PV Device";
dc->props = xen_pv_props;
}
msi_write_config(d, address, val, len);
}
shpc_cap_write_config(d, address, val, len);
}
static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
{
PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
pci_bridge_reset(qdev);
shpc_reset(dev);
}
static Property pci_bridge_dev_properties[] = {
/* Note: 0 is not a legal chassis number. */
DEFINE_PROP_UINT8("chassis_nr", PCIBridgeDev, chassis_nr, 0),
DEFINE_PROP_BIT("msi", PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_MSI_REQ, true),
DEFINE_PROP_END_OF_LIST(),
};
static const VMStateDescription pci_bridge_dev_vmstate = {
.name = "pci_bridge",
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(bridge.dev, PCIBridgeDev),
SHPC_VMSTATE(bridge.dev.shpc, PCIBridgeDev),
VMSTATE_END_OF_LIST()
}
};
static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
{
the bios filename. */
if (pflash_drv == NULL) {
pc_fw_add_pflash_drv();
pflash_drv = drive_get(IF_PFLASH, 0, 0);
}
if (pflash_drv != NULL) {
pc_system_flash_init(rom_memory, pflash_drv);
} else {
fprintf(stderr, "qemu: PC system firmware (pflash) not available\n");
exit(1);
}
}
static Property pcsysfw_properties[] = {
DEFINE_PROP_UINT8("rom_only", PcSysFwDevice, rom_only, 0),
DEFINE_PROP_END_OF_LIST(),
};
static int pcsysfw_init(DeviceState *dev)
{
return 0;
}
static void pcsysfw_class_init (ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS (klass);
dc->desc = "PC System Firmware";
dc->init = pcsysfw_init;
dc->props = pcsysfw_properties;
}
static Property m2sxxx_soc_properties[] = {
/*
* part name specifies the type of SmartFusion2 device variant(this
* property is for information purpose only.
*/
DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type),
DEFINE_PROP_STRING("part-name", MSF2State, part_name),
DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE),
DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
MSF2_ESRAM_MAX_SIZE),
/* Libero GUI shows 100Mhz as default for clocks */
DEFINE_PROP_UINT32("m3clk", MSF2State, m3clk, 100 * 1000000),
/* default divisors in Libero GUI */
DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2),
DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2),
DEFINE_PROP_END_OF_LIST(),
};
static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = m2sxxx_soc_realize;
dc->props = m2sxxx_soc_properties;
}
static const TypeInfo m2sxxx_soc_info = {
.name = TYPE_MSF2_SOC,
.parent = TYPE_SYS_BUS_DEVICE,
}
}
static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
{
PCIDevice *dev = PCI_DEVICE(qdev);
pci_bridge_reset(qdev);
if (shpc_present(dev)) {
shpc_reset(dev);
}
}
static Property pci_bridge_dev_properties[] = {
/* Note: 0 is not a legal chassis number. */
DEFINE_PROP_UINT8(PCI_BRIDGE_DEV_PROP_CHASSIS_NR, PCIBridgeDev, chassis_nr,
0),
DEFINE_PROP_ON_OFF_AUTO(PCI_BRIDGE_DEV_PROP_MSI, PCIBridgeDev, msi,
ON_OFF_AUTO_AUTO),
DEFINE_PROP_BIT(PCI_BRIDGE_DEV_PROP_SHPC, PCIBridgeDev, flags,
PCI_BRIDGE_DEV_F_SHPC_REQ, true),
DEFINE_PROP_END_OF_LIST(),
};
static bool pci_device_shpc_present(void *opaque, int version_id)
{
PCIDevice *dev = opaque;
return shpc_present(dev);
}
static const VMStateDescription pci_bridge_dev_vmstate = {
DriveInfo *di_sd;
DriveInfo *di_mmc;
di_sd = drive_get_by_index(IF_SD , s->drive_index);
di_mmc = drive_get_by_index(IF_SD, (s->drive_index + 2));
s->sd_card = sd_init(di_sd ? blk_by_legacy_dinfo(di_sd) : NULL, false);
s->mmc_card = mmc_init(di_mmc ? blk_by_legacy_dinfo(di_mmc) : NULL);
dc_parent->realize(dev, errp);
qdev_init_gpio_in_named(dev, ronaldo_sdhci_slottype_handler, "SLOTTYPE", 1);
}
static Property ronaldo_sdhci_properties[] = {
DEFINE_PROP_UINT8("drive-index", RonaldoSDHCIState, drive_index, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void ronaldo_sdhci_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ronaldo_sdhci_realize;
dc->props = ronaldo_sdhci_properties;
dc->reset = ronaldo_sdhci_reset;
}
static const TypeInfo ronaldo_sdhci_info = {
.name = TYPE_RONALDO_SDHCI,
.parent = TYPE_SYSBUS_SDHCI,
VMSTATE_INT32(count_shift, APICCommonState),
VMSTATE_UINT32(initial_count, APICCommonState),
VMSTATE_INT64(initial_count_load_time, APICCommonState),
VMSTATE_INT64(next_time, APICCommonState),
VMSTATE_INT64(timer_expiry,
APICCommonState), /* open-coded timer state */
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription*[]) {
&vmstate_apic_common_sipi,
NULL
}
};
static Property apic_properties_common[] = {
DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
true),
DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
false),
DEFINE_PROP_END_OF_LIST(),
};
static void apic_common_get_id(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
APICCommonState *s = APIC_COMMON(obj);
uint32_t value;
value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id;
visit_type_uint32(v, name, &value, errp);
VMSTATE_INT32(count_shift, APICCommonState),
VMSTATE_UINT32(initial_count, APICCommonState),
VMSTATE_INT64(initial_count_load_time, APICCommonState),
VMSTATE_INT64(next_time, APICCommonState),
VMSTATE_INT64(timer_expiry,
APICCommonState), /* open-coded timer state */
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription*[]) {
&vmstate_apic_common_sipi,
NULL
}
};
static Property apic_properties_common[] = {
DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
true),
DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
false),
DEFINE_PROP_END_OF_LIST(),
};
static void apic_common_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = apic_reset_common;
dc->props = apic_properties_common;
dc->realize = apic_common_realize;
if (s->data_be) {
s->data = cpu_to_be64(s->data);
} else {
s->data = cpu_to_le64(s->data);
}
}
static void generic_loader_unrealize(DeviceState *dev, Error **errp)
{
qemu_unregister_reset(generic_loader_reset, dev);
}
static Property generic_loader_props[] = {
DEFINE_PROP_UINT64("addr", GenericLoaderState, addr, 0),
DEFINE_PROP_UINT64("data", GenericLoaderState, data, 0),
DEFINE_PROP_UINT8("data-len", GenericLoaderState, data_len, 0),
DEFINE_PROP_BOOL("data-be", GenericLoaderState, data_be, false),
DEFINE_PROP_UINT32("cpu-num", GenericLoaderState, cpu_num, CPU_NONE),
DEFINE_PROP_BOOL("force-raw", GenericLoaderState, force_raw, false),
DEFINE_PROP_STRING("file", GenericLoaderState, file),
DEFINE_PROP_END_OF_LIST(),
};
static void generic_loader_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
/* The reset function is not registered here and is instead registered in
* the realize function to allow this device to be added via the device_add
* command in the QEMU monitor.
* TODO: Improve the device_add functionality to allow resets to be
VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
VMSTATE_UINT32(esr, APICCommonState),
VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
VMSTATE_UINT32(divide_conf, APICCommonState),
VMSTATE_INT32(count_shift, APICCommonState),
VMSTATE_UINT32(initial_count, APICCommonState),
VMSTATE_INT64(initial_count_load_time, APICCommonState),
VMSTATE_INT64(next_time, APICCommonState),
VMSTATE_INT64(timer_expiry,
APICCommonState), /* open-coded timer state */
VMSTATE_END_OF_LIST()
}
};
static Property apic_properties_common[] = {
DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
true),
DEFINE_PROP_END_OF_LIST(),
};
static void apic_common_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_apic_common;
dc->reset = apic_reset_common;
dc->no_user = 1;
dc->props = apic_properties_common;
sc->init = apic_init_common;
if (vcon->chr) {
port->info->have_data = NULL;
qemu_chr_close(vcon->chr);
}
return 0;
}
static VirtIOSerialPortInfo virtconsole_info = {
.qdev.name = "virtconsole",
.qdev.size = sizeof(VirtConsole),
.init = virtconsole_initfn,
.exit = virtconsole_exitfn,
.qdev.props = (Property[]) {
DEFINE_PROP_UINT8("is_console", VirtConsole, port.is_console, 1),
DEFINE_PROP_UINT32("nr", VirtConsole, port.id, VIRTIO_CONSOLE_BAD_ID),
DEFINE_PROP_CHR("chardev", VirtConsole, chr),
DEFINE_PROP_STRING("name", VirtConsole, port.name),
DEFINE_PROP_END_OF_LIST(),
},
};
static void virtconsole_register(void)
{
virtio_serial_port_qdev_register(&virtconsole_info);
}
device_init(virtconsole_register)
/* Generic Virtio Serial Ports */
static int virtserialport_initfn(VirtIOSerialDevice *dev)
Flash *s = M25P80(d);
reset_memory(s);
}
static int m25p80_pre_save(void *opaque)
{
flash_sync_dirty((Flash *)opaque, -1);
return 0;
}
static Property m25p80_properties[] = {
/* This is default value for Micron flash */
DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
DEFINE_PROP_DRIVE("drive", Flash, blk),
DEFINE_PROP_END_OF_LIST(),
};
static int m25p80_pre_load(void *opaque)
{
Flash *s = (Flash *)opaque;
s->data_read_loop = false;
return 0;
}
.fields = (VMStateField[]) {
VMSTATE_I2C_SLAVE(i2c, PCA954XState),
VMSTATE_UINT8(control_reg, PCA954XState),
VMSTATE_BOOL(control_decoded, PCA954XState),
VMSTATE_UINT8(active_lanes, PCA954XState),
VMSTATE_UINT8(lanes, PCA954XState),
VMSTATE_BOOL(mux, PCA954XState),
VMSTATE_END_OF_LIST()
}
};
static Property pca954x_properties[] = {
/* These could be GPIOs, but the application is rare, just let machine model
* tie them with props
*/
DEFINE_PROP_UINT8("chip-enable", PCA954XState, chip_enable, 0),
DEFINE_PROP_END_OF_LIST(),
};
static void pca954x_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
PCA954XClass *sc = PCA954X_CLASS(klass);
k->event = pca954x_event;
k->recv = pca954x_recv;
k->send = pca954x_send;
k->decode_address = pca954x_decode_address;
dc->realize = pca954x_realize;
