__s32 Image_init(__u32 screen_id)
{
image_clk_init(screen_id);
/* when access image registers, must open MODULE CLOCK of image */
image_clk_on(screen_id, 0);
DE_BE_Reg_Init(screen_id);
Image_open(screen_id);
DE_BE_EnableINT(screen_id, DE_IMG_REG_LOAD_FINISH);
DE_BE_reg_auto_load_en(screen_id, 0);
if(screen_id == 0) {
OSAL_RegISR(gdisp.init_para.irq[DISP_MOD_BE0],0,scaler_event_proc, (void *)screen_id,0,0);
#ifndef __LINUX_OSAL__
OSAL_InterruptEnable(gdisp.init_para.irq[DISP_MOD_BE0]);
#endif
} else if(screen_id == 1) {
OSAL_RegISR(gdisp.init_para.irq[DISP_MOD_BE1],0,scaler_event_proc, (void *)screen_id,0,0);
#ifndef __LINUX_OSAL__
OSAL_InterruptEnable(gdisp.init_para.irq[DISP_MOD_BE1]);
#endif
}
return DIS_SUCCESS;
}
__s32 Image_init(__u32 sel)
{
image_clk_init(sel);
image_clk_on(sel); //when access image registers, must open MODULE CLOCK of image
DE_BE_Reg_Init(sel);
if(sel == 0)
{
BSP_disp_sprite_init(sel);
}
//DE_BE_Ready_Enable(sel, TRUE);
Image_open(sel);
if(sel == 0)
{
DE_BE_EnableINT(sel, DE_IMG_IRDY_IE);
}//DE_BE_EnableINT(sel , DE_IMG_IRDY_IE); //when sel == 1, can't process when image0 module clk close
//image_clk_off(sel); //close MODULE CLOCK of image
if(sel == 0)
{
OSAL_RegISR(INTC_IRQNO_IMAGE0,0,Image_event_proc, (void *)sel,0,0);
//OSAL_InterruptEnable(INTC_IRQNO_IMAGE0);
}
else if(sel == 1)
{
OSAL_RegISR(INTC_IRQNO_IMAGE1,0,Image_event_proc, (void *)sel,0,0);
//OSAL_InterruptEnable(INTC_IRQNO_IMAGE1);
}
return DIS_SUCCESS;
}
__s32 Image_init(__u32 sel)
{
image_clk_init(sel);
image_clk_on(sel); //when access image registers, must open MODULE CLOCK of image
DE_BE_Reg_Init(sel);
BSP_disp_sprite_init(sel);
Image_open(sel);
DE_BE_EnableINT(sel, DE_IMG_REG_LOAD_FINISH);
DE_BE_reg_auto_load_en(sel, 0);
return DIS_SUCCESS;
}
__s32 Image_init(__u32 sel)
{
image_clk_init(sel);
image_clk_on(sel); //when access image registers, must open MODULE CLOCK of image
DE_BE_Reg_Init(sel);
BSP_disp_sprite_init(sel);
BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD,gdisp.screen[sel].iep_status&DRC_USED);
Image_open(sel);
DE_BE_EnableINT(sel, DE_IMG_REG_LOAD_FINISH);
DE_BE_reg_auto_load_en(sel, 0);
return DIS_SUCCESS;
}
__s32 BSP_disp_tv_open(__u32 sel)
{
if(!(gdisp.screen[sel].status & TV_ON))
{
__disp_tv_mode_t tv_mod;
tv_mod = gdisp.screen[sel].tv_mode;
image_clk_on(sel, 0);
image_clk_on(sel, 1);
Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit
DE_BE_EnableINT(sel, DE_IMG_REG_LOAD_FINISH);
disp_clk_cfg(sel,DISP_OUTPUT_TYPE_TV, tv_mod);
tve_clk_on(sel);
lcdc_clk_on(sel, 1, 0);
lcdc_clk_on(sel, 1, 1);
Disp_lcdc_reg_isr(sel);
LCDC_init(sel);
gdisp.screen[sel].output_csc_type = DISP_OUT_CSC_TYPE_TV;
BSP_disp_set_output_csc(sel, gdisp.screen[sel].output_csc_type);
DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod));
DE_BE_Output_Select(sel, sel);
tcon1_set_tv_mode(sel,tv_mod);
TVE_set_tv_mode(sel, tv_mod);
Disp_TVEC_DacCfg(sel, tv_mod);
tcon1_open(sel);
Disp_TVEC_Open(sel);
Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod);
#ifdef __LINUX_OSAL__
{
disp_gpio_set_t gpio_info[1];
__hdle gpio_pa_shutdown;
__s32 ret;
memset(gpio_info, 0, sizeof(disp_gpio_set_t));
ret = OSAL_Script_FetchParser_Data("audio_para","audio_pa_ctrl", (int *)gpio_info, sizeof(disp_gpio_set_t)/sizeof(int));
if(ret == 0)
{
gpio_pa_shutdown = OSAL_GPIO_Request(gpio_info, 1);
if(!gpio_pa_shutdown)
{
DE_WRN("audio codec_wakeup request gpio fail!\n");
}
else
{
OSAL_GPIO_DevWRITE_ONEPIN_DATA(gpio_pa_shutdown, 0, "audio_pa_ctrl");
}
}
}
#endif
gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod);
gdisp.screen[sel].status |= TV_ON;
gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED;
gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV;
Disp_set_out_interlace(sel);
#ifdef __LINUX_OSAL__
Display_set_fb_timming(sel);
#endif
}
return DIS_SUCCESS;
}
__s32 BSP_disp_hdmi_open(__u32 sel)
{
if(!(gdisp.screen[sel].status & HDMI_ON))
{
__disp_tv_mode_t tv_mod;
tv_mod = gdisp.screen[sel].hdmi_mode;
BSP_disp_hdmi_get_hdcp_enable();
hdmi_clk_on();
if(gdisp.screen[sel].hdmi_hdcp_en)
hdcp_clk_init(tv_mod);
lcdc_clk_on(sel, 1, 0);
lcdc_clk_on(sel, 1, 1);
Disp_lcdc_reg_isr(sel);
LCDC_init(sel);
image_clk_on(sel, 0);
image_clk_on(sel, 1);
Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit
DE_BE_EnableINT(sel, DE_IMG_REG_LOAD_FINISH);
disp_clk_cfg(sel,DISP_OUTPUT_TYPE_HDMI, tv_mod);
if(gdisp.init_para.hdmi_cts_compatibility == 0)
{
DE_INF("BSP_disp_hdmi_open: disable dvi mode\n");
BSP_disp_hdmi_dvi_enable(sel, 0);
}
else if(gdisp.init_para.hdmi_cts_compatibility == 1)
{
DE_INF("BSP_disp_hdmi_open: enable dvi mode\n");
BSP_disp_hdmi_dvi_enable(sel, 1);
}
else
{
BSP_disp_hdmi_dvi_enable(sel, BSP_disp_hdmi_dvi_support(sel));
}
if(BSP_dsip_hdmi_get_input_csc(sel) == 0)
{
__inf("BSP_disp_hdmi_open: hdmi output rgb\n");
gdisp.screen[sel].output_csc_type = DISP_OUT_CSC_TYPE_HDMI_RGB;
BSP_disp_set_output_csc(sel, gdisp.screen[sel].output_csc_type);
}else
{
__inf("BSP_disp_hdmi_open: hdmi output yuv\n");
gdisp.screen[sel].output_csc_type = DISP_OUT_CSC_TYPE_HDMI_YUV;//default yuv
BSP_disp_set_output_csc(sel, gdisp.screen[sel].output_csc_type);
}
DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod));
DE_BE_Output_Select(sel, sel);
tcon1_set_hdmi_mode(sel,tv_mod);
tcon1_open(sel);
if(gdisp.init_para.hdmi_open)
{
gdisp.init_para.hdmi_open();
}
else
{
DE_WRN("hdmi_open is NULL\n");
return -1;
}
Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_HDMI, tv_mod);
gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod);
gdisp.screen[sel].status |= HDMI_ON;
gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED;
gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_HDMI;
Disp_set_out_interlace(sel);
#ifdef __LINUX_OSAL__
Display_set_fb_timming(sel);
#endif
}
return DIS_SUCCESS;
}
