/* Identify NIC type
*/
static void
identify_nic(void)
{
struct board_info *db = &dmfe_info; /* Point a board information structure */
u16 phy_reg3;
DM9000_iow(DM9000_NCR, NCR_EXT_PHY);
phy_reg3 = phy_read(3);
switch (phy_reg3 & 0xfff0) {
case 0xb900:
if (phy_read(31) == 0x4404) {
db->nic_type = HOMERUN_NIC;
program_dm9801(phy_reg3);
DM9000_DBG("found homerun NIC\n");
} else {
db->nic_type = LONGRUN_NIC;
DM9000_DBG("found longrun NIC\n");
program_dm9802();
}
break;
default:
db->nic_type = FASTETHER_NIC;
break;
}
DM9000_iow(DM9000_NCR, 0);
}
/*
Hardware start transmission.
Send a packet to media from the upper layer.
*/
int
eth_send(volatile void *packet, int length)
{
char *data_ptr;
u32 tmplen, i;
int tmo;
DM9000_DBG("eth_send: length: %d\n", length);
for (i = 0; i < length; i++) {
if (i % 8 == 0)
DM9000_DBG("\nSend: 02x: ", i);
DM9000_DBG("%02x ", ((unsigned char *) packet)[i]);
} DM9000_DBG("\n");
/* Move data to DM9000 TX RAM */
data_ptr = (char *) packet;
DM9000_outb(DM9000_MWCMD, DM9000_IO);
#ifdef CONFIG_DM9000_USE_8BIT
/* Byte mode */
for (i = 0; i < length; i++)
DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA);
#endif /* */
#ifdef CONFIG_DM9000_USE_16BIT
tmplen = (length + 1) / 2;
for (i = 0; i < tmplen; i++)
DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
#endif /* */
#ifdef CONFIG_DM9000_USE_32BIT
tmplen = (length + 3) / 4;
for (i = 0; i < tmplen; i++)
DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
#endif /* */
/* Set TX length to DM9000 */
DM9000_iow(DM9000_TXPLL, length & 0xff);
DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
/* Issue TX polling command */
DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
/* wait for end of transmission */
tmo = get_timer(0) + 5 * CFG_HZ;
while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) {
if (get_timer(0) >= tmo) {
printf("transmission timeout\n");
break;
}
}
DM9000_DBG("transmit done\n\n");
return 0;
}
static void
dump_regs(void)
{
DM9000_DBG("\n");
DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(ISR));
DM9000_DBG("\n");
}
/* General Purpose dm9000 reset routine */
static void
dm9000_reset(void)
{
DM9000_DBG("resetting\n");
DM9000_iow(DM9000_NCR, NCR_RST);
udelay(1000); /* delay 1ms */
}
// =============================================================================
// 功能：读取DM9000的ID，若读到的ID不正确，则报警，并打印信息，该函数返回false，则
// 初始化网卡失败，模块直接返回
// 参数：无
// 返回：true,成功;false,失败
// 说明：该函数返回成功，实质说明了CPU与硬件之间的通信正常
// =============================================================================
bool_t DM9000_Probe(void)
{
unsigned int id_val;
id_val = dm_reg_read(DM9000_VIDL);
id_val |= dm_reg_read(DM9000_VIDH) << 8;
id_val |= dm_reg_read(DM9000_PIDL) << 16;
id_val |= dm_reg_read(DM9000_PIDH) << 24;
if (id_val == DM9000_ID)
{
DM9000_DBG("dm9000 i/o: id: 0x%x \r\n",id_val);
return true;
}
else
{
DM9000_DBG("dm9000 not found !\r\n");
return false;
}
}
/*
Stop the interface.
The interface is stopped when it is brought.
*/
void
eth_halt(void)
{
DM9000_DBG("eth_halt\n");
/* RESET devie */
phy_write(0, 0x8000); /* PHY RESET */
DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
}
// =============================================================================
// 功能：DM9000网卡芯片复位
// 参数：无
// 返回：无
// =============================================================================
void DM9000_reset(void)
{
DM9000_DBG("resetting\n");
dm_reg_write(DM9000_NCR, NCR_RST);
Djy_DelayUs(3000); /* delay 3ms */
dm_reg_write(DM9000_NCR, 0x00);
dm_reg_write(DM9000_NCR, NCR_RST);
Djy_DelayUs(3000); /* delay 3ms */
dm_reg_write(DM9000_NCR, 0x00);
}
/*
Write a word to phyxcer
*/
static void
phy_write(int reg, u16 value)
{
/* Fill the phyxcer register into REG_0C */
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
/* Fill the written data into REG_0D & REG_0E */
DM9000_iow(DM9000_EPDRL, (value & 0xff));
DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
udelay(500); /* Wait write complete */
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
DM9000_DBG("phy_write(reg:%d, value:%d)\n", reg, value);
}
/*
Read a word from phyxcer
*/
static u16
phy_read(int reg)
{
u16 val;
/* Fill the phyxcer register into REG_0C */
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
udelay(100); /* Wait read complete */
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
/* The read data keeps on REG_0D & REG_0E */
DM9000_DBG("phy_read(%d): %d\n", reg, val);
return val;
}
// =============================================================================
// 功能：DM9000PHY芯片复位，并配置为自适应模式
// 参数：无
// 返回：无
// =============================================================================
bool_t DM9000_PhyInit(void)
{
u32 timeout = CN_PHY_INTIT_TIMEOUT;
dm_reg_write(DM9000_GPCR,1); //设置GPIO0为输出
dm_reg_write(DM9000_GPR,0); //激活内部PHY
Djy_DelayUs(3 * mS);
dm_reg_write_phy(DM9000_BMCR,0x8000);
Djy_DelayUs(30);
while(dm_reg_read_phy(DM9000_BMCR) & 0x8000)
{
Djy_DelayUs(10*mS);
timeout = timeout - 10*mS;
if(timeout == 0)
{
DM9000_DBG("phy init failed !\r\n");
return false;
}
}
DM9000_DBG("Phy Reset Success!\r\n");
dm_reg_write_phy(DM9000_BMCR,0x1200);//auto negotiation
Djy_DelayUs(30);
while(!(dm_reg_read_phy(DM9000_BMSR) & 0x20))
{
Djy_DelayUs(10*mS);
timeout = timeout - 10*mS;
if(timeout == 0)
{
DM9000_DBG("phy init failed !\r\n");
return false;
}
}
DM9000_DBG("auto negotiation completed!\r\n");
while(!(dm_reg_read_phy(DM9000_BMSR) & 0x04))
{
Djy_DelayUs(10*mS);
timeout = timeout - 10*mS;
if(timeout == 0)
{
DM9000_DBG("phy init failed !\r\n");
return false;
}
}
DM9000_DBG("phy linked!\r\n");
return true;
}
// =============================================================================
// 功能：DM9000以太网网卡硬件初始化，包括复位网卡、清发送和接收状态、配置MAC地址、
// 使能接收中断信息输出（若需产生中断，还需配置中断线）
// 参数：无
// 返回：
// =============================================================================
bool_t DM9000_HardInit(void)
{
dm_reg_write(DM9000_NCR,1); //软件复位DM9000
Djy_DelayUs(30); //延时至少20μs
dm_reg_write(DM9000_NCR,0); //清除复位位
dm_reg_write(DM9000_NCR,1); //为了确保复位正确，再次复位
Djy_DelayUs(30);
dm_reg_write(DM9000_NCR,0);
if(false == DM9000_PhyInit()) //PHY芯片初始化
return false;
dm_reg_write(DM9000_NSR,0x2c); //清TX状态
dm_reg_write(DM9000_ISR,0xf); //清中断状态
dm_reg_write(DM9000_RCR,0x39); //设置RX控制
dm_reg_write(DM9000_TCR,0); //设置TX控制
dm_reg_write(DM9000_BPTR,0x3f);
dm_reg_write(DM9000_FCTR,0x3a);
dm_reg_write(DM9000_FCR,0xff);
dm_reg_write(DM9000_SMCR,0x00);
dm_reg_write(DM9000_PAR+0,sgNetHardMac[0]); //设置MAC地址
dm_reg_write(DM9000_PAR+1,sgNetHardMac[1]);
dm_reg_write(DM9000_PAR+2,sgNetHardMac[2]);
dm_reg_write(DM9000_PAR+3,sgNetHardMac[3]);
dm_reg_write(DM9000_PAR+4,sgNetHardMac[4]);
dm_reg_write(DM9000_PAR+5,sgNetHardMac[5]);
dm_reg_write(DM9000_NSR,0x2c); //再次清TX状态
dm_reg_write(DM9000_ISR,0xf); //再次清中断状态
dm_reg_write(DM9000_IMR,0x81); //打开接受数据中断
while(!(dm_reg_read(DM9000_NSR) & NSR_LINKST));
DM9000_DBG("DM9000 Linked!\r\n");
return true;
}
/*
Received a packet and pass to upper layer
*/
int
eth_rx(void)
{
u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
u16 RxStatus, RxLen = 0;
u32 tmplen, i;
#ifdef CONFIG_DM9000_USE_32BIT
u32 tmpdata;
#endif
/* Check packet ready or not */
DM9000_ior(DM9000_MRCMDX); /* Dummy read */
rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */
if (rxbyte == 0)
return 0;
/* Status check: this byte must be 0 or 1 */
if (rxbyte > 1) {
DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
DM9000_DBG("rx status check: %d\n", rxbyte);
}
DM9000_DBG("receiving packet\n");
/* A packet ready now & Get status/length */
DM9000_outb(DM9000_MRCMD, DM9000_IO);
#ifdef CONFIG_DM9000_USE_8BIT
RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
#endif /* */
#ifdef CONFIG_DM9000_USE_16BIT
RxStatus = DM9000_inw(DM9000_DATA);
RxLen = DM9000_inw(DM9000_DATA);
#endif /* */
#ifdef CONFIG_DM9000_USE_32BIT
tmpdata = DM9000_inl(DM9000_DATA);
RxStatus = tmpdata;
RxLen = tmpdata >> 16;
#endif /* */
DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
/* Move data from DM9000 */
/* Read received packet from RX SRAM */
#ifdef CONFIG_DM9000_USE_8BIT
for (i = 0; i < RxLen; i++)
rdptr[i] = DM9000_inb(DM9000_DATA);
#endif /* */
#ifdef CONFIG_DM9000_USE_16BIT
tmplen = (RxLen + 1) / 2;
for (i = 0; i < tmplen; i++)
((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA);
#endif /* */
#ifdef CONFIG_DM9000_USE_32BIT
tmplen = (RxLen + 3) / 4;
for (i = 0; i < tmplen; i++)
((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA);
#endif /* */
if ((RxStatus & 0xbf00) || (RxLen < 0x40)
|| (RxLen > DM9000_PKT_MAX)) {
if (RxStatus & 0x100) {
printf("rx fifo error\n");
}
if (RxStatus & 0x200) {
printf("rx crc error\n");
}
if (RxStatus & 0x8000) {
printf("rx length error\n");
}
if (RxLen > DM9000_PKT_MAX) {
printf("rx length too big\n");
dm9000_reset();
}
} else {
/* Pass to upper layer */
DM9000_DBG("passing packet to upper layer\n");
NetReceive(NetRxPackets[0], RxLen);
return RxLen;
}
return 0;
}
/* Initilize dm9000 board
*/
int
eth_init(bd_t * bd)
{
int i, oft;
DM9000_DBG("eth_init()\n");
/* RESET device */
dm9000_reset();
dm9000_probe();
/* NIC Type: FASTETHER, HOMERUN, LONGRUN */
identify_nic();
/* GPIO0 on pre-activate PHY */
DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
/* Set PHY */
set_PHY_mode();
/* Program operating register */
DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */
DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */
DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
DM9000_iow(DM9000_SMCR, 0); /* Special Mode */
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
/* Set Node address */
//HJ_start /* www.embedsky.net */
char *tmp = getenv("ethaddr");
char *end;
for (i = 0; i < 6; i++)
{
bd->bi_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
if(tmp)
tmp = (*end) ? end+1 : end;
}
//HJ_end /* www.embedsky.net */
printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_iow(oft, bd->bi_enetaddr[i]);
for (i = 0, oft = 0x16; i < 8; i++, oft++)
DM9000_iow(oft, 0xff);
/* read back mac, just to be sure */
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_DBG("%02x:", DM9000_ior(oft));
DM9000_DBG("\n");
/* Activate DM9000 */
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
return 0;
}
/* Initilize dm9000 board
*/
int
eth_init(bd_t * bd)
{
int i, oft, lnk;
DM9000_DBG("eth_init()\n");
/* RESET device */
dm9000_reset();
dm9000_probe();
/* NIC Type: FASTETHER, HOMERUN, LONGRUN */
identify_nic();
/* GPIO0 on pre-activate PHY */
DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
/* Set PHY */
set_PHY_mode();
/* Program operating register */
DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */
DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */
DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
DM9000_iow(DM9000_SMCR, 0); /* Special Mode */
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
/* Set Node address */
// for (i = 0; i < 6; i++) //raymanfeng-
// ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_iow(oft, bd->bi_enetaddr[i]);
for (i = 0, oft = 0x16; i < 8; i++, oft++)
DM9000_iow(oft, 0xff);
/* read back mac, just to be sure */
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_DBG("%02x:", DM9000_ior(oft));
DM9000_DBG("\n");
/* Activate DM9000 */
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
/* //raymanfeng-
i = 0;
while (!(phy_read(1) & 0x20)) { // autonegation complete bit
udelay(1000);
i++;
if (i == 10000) {
printf("could not establish link\n");
return 0;
}
}
// see what we've got
lnk = phy_read(17) >> 12;
printf("operating at ");
switch (lnk) {
case 1:
printf("10M half duplex ");
break;
case 2:
printf("10M full duplex ");
break;
case 4:
printf("100M half duplex ");
break;
case 8:
printf("100M full duplex ");
break;
default:
printf("unknown: %d ", lnk);
break;
}
printf("mode\n");
*/
return 0;
}
