int
dmamux_configure(int mux, int source, int channel, int enable)
{
struct dmamux_softc *sc;
int reg;
sc = dmamux_sc;
MUX_WRITE1(sc, mux, DMAMUX_CHCFG(channel), 0x0);
reg = 0;
if (enable)
reg |= (CHCFG_ENBL);
reg &= ~(CHCFG_SOURCE_MASK << CHCFG_SOURCE_SHIFT);
reg |= (source << CHCFG_SOURCE_SHIFT);
MUX_WRITE1(sc, mux, DMAMUX_CHCFG(channel), reg);
return (0);
}
void DmaChannelInit(int channel, void *source_ptr, void *dest_ptr, int size, int source,
int source_inc, int dest_inc) {
// Configure mux.
// Disable channel and clear everything.
DMAMUX_CHCFG(channel) = 0x00;
// Select source.
DMAMUX_CHCFG(channel) |= DMAMUX_CHCFG_SOURCE(source);
// Configure channel.
// Set up source and dest addresses.
DMA_SADDR(channel) = (int)source_ptr;
DMA_DADDR(channel) = (int)dest_ptr;
// Set soruce and dest address increment.
DMA_SOFF(channel) = source_inc;
DMA_DOFF(channel) = dest_inc;
// Set size of transfer 0x00 = 1 byte.
DMA_ATTR(channel) = DMA_ATTR_SSIZE(0) | DMA_ATTR_DSIZE(0);
// Set bytes per minor loop.
DMA_NBYTES_MLNO(channel) = 0x01;
// Set number of minor loops.
DMA_CITER_ELINKNO(channel) = DMA_CITER_ELINKNO_CITER(size);
DMA_BITER_ELINKNO(channel) = DMA_BITER_ELINKNO_BITER(size);
// Adjustment applied after major loop finishes
DMA_SLAST(channel) = -(size * source_inc); // Source address adjustment.
DMA_DLAST_SGA(channel) = -(size * dest_inc); // Destination address adjustment.
// Set to disable on completion.
DMA_CSR(0) |= DMA_CSR_DREQ_MASK;
// Enable DMA request for channel.
DMA_ERQ |= (1 << channel);
// Enable mux.
DMAMUX_CHCFG(channel) |= DMAMUX_CHCFG_ENBL_MASK;
}
