/* Send PALL command */
dmc_config_prech(mem, exynos_drex0);
dmc_config_prech(mem, exynos_drex1);
write32(&exynos_drex0->memcontrol, mem->memcontrol);
write32(&exynos_drex1->memcontrol, mem->memcontrol);
/*
* Set DMC Concontrol: Enable auto-refresh counter, provide
* read data fetch cycles and enable DREX auto set powerdown
* for input buffer of I/O in none read memory state.
*/
write32(&exynos_drex0->concontrol, mem->concontrol |
(mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) |
DMC_CONCONTROL_IO_PD_CON(0x2));
write32(&exynos_drex1->concontrol, mem->concontrol |
(mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) |
DMC_CONCONTROL_IO_PD_CON(0x2));
/* Enable Clock Gating Control for DMC
* this saves around 25 mw dmc power as compared to the power
* consumption without these bits enabled
*/
setbits_le32(&exynos_drex0->cgcontrol, DMC_INTERNAL_CG);
setbits_le32(&exynos_drex1->cgcontrol, DMC_INTERNAL_CG);
return 0;
}
/* Send PALL command */
dmc_config_prech(mem, exynos_drex0);
dmc_config_prech(mem, exynos_drex1);
writel(mem->memcontrol, &exynos_drex0->memcontrol);
writel(mem->memcontrol, &exynos_drex1->memcontrol);
/*
* Set DMC Concontrol: Enable auto-refresh counter, provide
* read data fetch cycles and enable DREX auto set powerdown
* for input buffer of I/O in none read memory state.
*/
writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
DMC_CONCONTROL_IO_PD_CON(0x2),
&exynos_drex0->concontrol);
writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
DMC_CONCONTROL_IO_PD_CON(0x2),
&exynos_drex1->concontrol);
/* Enable Clock Gating Control for DMC
* this saves around 25 mw dmc power as compared to the power
* consumption without these bits enabled
*/
setbits_le32(&exynos_drex0->cgcontrol, DMC_INTERNAL_CG);
setbits_le32(&exynos_drex1->cgcontrol, DMC_INTERNAL_CG);
return 0;
}
