unsigned int hacc_set_key(AES_KEY_ID id, AES_KEY key)
{
unsigned int i, acon = 0;
unsigned int akey;
unsigned char *tkey;
switch (key) {
case AES_KEY_128:
acon |= HACC_AES_128;
break;
case AES_KEY_192:
acon |= HACC_AES_192;
break;
case AES_KEY_256:
acon |= HACC_AES_256;
break;
default:
return ERR_HACC_KEY_INVALID;
}
/* set aes block size */
hacc_ctx.blk_sz = key;
/* set aes key length */
DRV_ClrReg32(HACC_ACON, HACC_AES_TYPE_MASK);
DRV_SetReg32(HACC_ACON, acon);
/* clear key */
for (i = 0; i < HACC_AES_MAX_KEY_SZ; i += 4)
DRV_WriteReg32(HACC_AKEY0 + i, 0);
/* set aes key */
switch (id) {
case AES_HW_KEY:
DRV_SetReg32(HACC_ACONK, HACC_AES_BK2C);
return 0;
case AES_HW_WRAP_KEY:
tkey = &hacc_ctx.hw_key[0];
break;
case AES_SW_KEY:
default:
tkey = &hacc_ctx.sw_key[0];
break;
}
/* non hardware binding key */
DRV_ClrReg32(HACC_ACONK, HACC_AES_BK2C);
/* update key. note that don't use key directly */
for (i = 0; i < HACC_AES_MAX_KEY_SZ; i += 4) {
akey = (tkey[i] << 24) | (tkey[i + 1] << 16) | (tkey[i + 2] << 8) | (tkey[i + 3]);
DRV_WriteReg32(HACC_AKEY0 + i, akey);
}
return SEC_OK;
}
static void gpt_power_on (bool bPowerOn)
{
if(!bPowerOn){
DRV_SetReg32(AP_PERI_GLOBALCON_PDN0, 1<<13);
}else{
DRV_ClrReg32(AP_PERI_GLOBALCON_PDN0, 1<<13);
}
}
unsigned int hacc_do_aes(AES_OPS ops, unsigned char *src, unsigned char *dst, unsigned int size)
{
unsigned int i;
unsigned int *ds, *dt, *vt;
/* make sure size is aligned to aes block size */
if ((size % AES_BLK_SZ) != 0) {
SMSG("[%s] size = %d is not %d bytes alignment\n", MOD, size, AES_BLK_SZ);
return ERR_HACC_DATA_UNALIGNED;
}
vt = (unsigned int *)&hacc_ctx.cfg.config[0];
/* erase src, cfg, out register */
DRV_SetReg32(HACC_ACON2, HACC_AES_CLR);
/* set init config */
for (i = 0; i < AES_CFG_SZ; i += 4)
DRV_WriteReg32(HACC_ACFG0 + i, *vt++);
if (ops == AES_ENC)
DRV_SetReg32(HACC_ACON, HACC_AES_ENC);
else
DRV_ClrReg32(HACC_ACON, HACC_AES_ENC);
ds = (unsigned int *)src;
dt = (unsigned int *)dst;
do {
/* fill in the data */
for (i = 0; i < AES_BLK_SZ; i += 4)
DRV_WriteReg32(HACC_ASRC0 + i, *ds++);
/* start aes engine */
DRV_SetReg32(HACC_ACON2, HACC_AES_START);
/* wait for aes engine ready */
while ((DRV_Reg32(HACC_ACON2) & HACC_AES_RDY) == 0)
;
/* read out the data */
for (i = 0; i < AES_BLK_SZ; i += 4)
*dt++ = DRV_Reg32(HACC_AOUT0 + i);
if (size == 0)
goto _end;
size -= AES_BLK_SZ;
} while (size != 0);
_end:
return SEC_OK;
}
DPI_STATUS DPI1_Init_PLL(HDMI_VIDEO_RESOLUTION resolution)
{
//DPI1 PLL
DRV_SetReg32(TVDPLL_PWR_CON0, (0x1 << 0)); //PLL_PWR_ON
udelay(2);
DRV_ClrReg32(TVDPLL_PWR_CON0, (0x1 << 1)); //PLL_ISO_EN
switch(resolution)
{
case HDMI_VIDEO_720x480p_60Hz:
#ifdef MTK_MT8193_HDMI_SUPPORT
case HDMI_VIDEO_720x576p_50Hz:
#endif
{
OUTREG32(TVDPLL_CON1, 0x80109d89);
OUTREG32(TVDPLL_CON0, 0x80800081);
break;
}
case HDMI_VIDEO_1920x1080p_30Hz:
#ifdef MTK_MT8193_HDMI_SUPPORT
case HDMI_VIDEO_1280x720p_50Hz:
case HDMI_VIDEO_1920x1080i_50Hz:
case HDMI_VIDEO_1920x1080p_25Hz:
case HDMI_VIDEO_1920x1080p_24Hz:
case HDMI_VIDEO_1920x1080p_50Hz:
#endif
{
OUTREG32(TVDPLL_CON1, 0x800b6c4e);
OUTREG32(TVDPLL_CON0, 0x80000081);
break;
}
case HDMI_VIDEO_1280x720p_60Hz:
#ifdef MTK_MT8193_HDMI_SUPPORT
case HDMI_VIDEO_1920x1080i_60Hz:
case HDMI_VIDEO_1920x1080p_23Hz:
case HDMI_VIDEO_1920x1080p_29Hz:
case HDMI_VIDEO_1920x1080p_60Hz:
#endif
{
OUTREG32(TVDPLL_CON1, 0x800b6964);
OUTREG32(TVDPLL_CON0, 0x80000081);
break;
}
default:
{
printk("[DPI1] not supported format, %s, %d, format = %d\n", __func__, __LINE__, resolution);
break;
}
}
udelay(20);
return DPI_STATUS_OK;
}
void lpm_init(void)
{
#if 1 /*TBC...*/
{
LPM_REG_CLR_SET(PLL_CLKSW_FDIV2, 0xF<<0, 4<<0);
DRV_SetReg32(PLL_CLKSW_FDIV6, 0x04);
DRV_SetReg32(PLL_CLKSW_FDIV6, 0x0100);
DRV_ClrReg32(PLL_CLKSW_FDIV6, 0x0100);
}
PDN_CLR(PDN_LPM);
#endif
/* It is disabled for low power(TOPSM) requirement. */
kal_set_timer(kal_create_timer("DCM_Timer"),
(kal_timer_func_ptr)DCM_Trace,
NULL,
KAL_TICKS_5_SEC,
KAL_TICKS_5_SEC);
}
static unsigned int hacc_set_mode(AES_MODE mode)
{
AES_CFG cfg;
DRV_ClrReg32(HACC_ACON, HACC_AES_MODE_MASK);
switch (mode) {
case AES_ECB_MODE:
/* no need cfg */
memset(&cfg.config[0], 0, sizeof(cfg.config));
DRV_SetReg32(HACC_ACON, HACC_AES_ECB);
break;
case AES_CBC_MODE:
DRV_SetReg32(HACC_ACON, HACC_AES_CBC);
break;
default:
return ERR_HACC_MODE_INVALID;
}
return SEC_OK;
}
void DCM_MCUBUS_DCM_OFF(kal_uint32 off)
{
kal_uint32 _savedMask;
_savedMask = SaveAndSetIRQMask();
if (0 != off) {
dcm_mcubus_dcm_off++;
}
else {
if (dcm_mcubus_dcm_off>0)
dcm_mcubus_dcm_off--;
}
#if defined (DCM_ENABLE)
if((0 != dcm_mcubus_dcm_off))
{
DRV_ClrReg32(MD_GLOBAL_CON1, 1UL<<25);
}
else
{
DRV_SetReg32(MD_GLOBAL_CON1, 1UL<<25);
}
#endif //#if defined (DCM_ENABLE)
RestoreIRQMask(_savedMask);
}
void platform_vusb_on(void)
{
#if !CFG_FPGA_PLATFORM
U32 ret=0;
ret=pmic_config_interface( (U32)(DIGLDO_CON2),
(U32)(1),
(U32)(PMIC_RG_VUSB_EN_MASK),
(U32)(PMIC_RG_VUSB_EN_SHIFT)
);
if(ret!=0)
{
print("[platform_vusb_on] Fail\n");
}
else
{
print("[platform_vusb_on] PASS\n");
}
// enable USB clock, clear cg bit (BIT13)
DRV_ClrReg32(0x10000024, 0x2000);
#endif
return;
}
static void DCM_Trace(void)
{
static kal_uint32 src_sel;
int timeout = 0;
if (dbg_lpm_enable & DBG_L1_LPM_ENABLE) {
DRV_ClrReg32(MD_L1_LPM_CON0, 1UL<<2); //Stop L1 LPM
kal_dev_trace(DRIVER_GROUP_SYSTEM, LPM_L1,
DRV_Reg32(MD_L1_LPM_CON0),
DRV_Reg32(MD_L1_LPM_STATUS0),
DRV_Reg32(MD_L1_LPM_STATUS1),
DRV_Reg32(MD_L1_LPM_STATUS2));
src_sel = (DRV_Reg32(MD_L1_LPM_CON0) & (0x0f<<4)) >> 4;
src_sel = ((src_sel+1) & 0x0f) << 4;
#if 1 //32k
DRV_WriteReg32(MD_L1_LPM_CON0, 2|0); //assert reset
for(timeout=500; timeout>0; timeout--) {
if (DRV_Reg32(MD_L1_LPM_STATUS0) == 0) {
DRV_WriteReg32(MD_L1_LPM_CON0, 2|1); //deassert reset
break;
}
}
timeout = 0;
#else //pll
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
//debug only
LPM_REG_CLR_SET(MD_L1_LPM_CON0, (0xffff<<16), timeout<<16);
LPM_REG_CLR_SET(MD_L1_LPM_CON0, (0xf<<4), (src_sel));
DRV_SetReg32_NPW(MD_L1_LPM_CON0, 1<<2);
}
void sc_dpidle_before_wfi(void)
{
#if 0
/* keep CA9 clock frequency when WFI to sleep */
topmisc = DRV_Reg32(TOP_MISC);
DRV_WriteReg32(TOP_MISC, (topmisc & ~(1U << 0)));
#endif
if (unlikely(get_chip_eco_ver() == CHIP_E1)) {
DRV_ClrReg32(WPLL_CON0, 0x1);
} else {
if (!(clk_mgr.subsys_state & 0x30) && clk_mgr.mmsys_state) {
mm_clk_pll2sq();
DRV_SetReg16(MDPLL_CON0, 0x1);
mmsys_switched_off = 1;
}
}
#ifndef CONFIG_LOCAL_TIMERS
if (mmsys_switched_off) {
dpidle_compare_update = dpidle_compare - dpidle_counter - 260;
} else {
dpidle_compare_update = dpidle_compare - dpidle_counter;
}
gpt_set_next_compare(dpidle_compare_update);
#endif
#ifdef CONFIG_LOCAL_WDT
wdt_counter_pre = mpcore_wdt_get_counter();
wdt_tick_pre = GPT_GetCounter(GPT2);
#endif
#ifdef PROFILE_DPIDLE
dpidle_tick_mid = GPT_GetCounter(GPT2);
#endif
}
void power_saving_init(void)
{
unsigned int reg_val = 0;
dcm_enable();
/* Power Controlled by SW */
DRV_SetReg32(SC_PWR_CON5, (0x1 << PWR_CTRL));
/* pull up PWR_ISO */
DRV_SetReg32(SC_PWR_CON5, (0x1 << PWR_ISO));
/* pull down PWR_RST_B, pull up PWR_MEM_OFF and PWR_CLK_DIS */
reg_val = DRV_Reg32(SC_PWR_CON5);
reg_val = (reg_val & ~(0x1 << PWR_RST_B)) | (0x1 << PWR_MEM_OFF) | (0x1 << PWR_CLK_DIS);
DRV_WriteReg32(SC_PWR_CON5, reg_val);
/* pull down PWR_ON */
DRV_ClrReg32(SC_PWR_CON5, (0x1 << PWR_ON));
/* wait for PWR_STA update */
while ((DRV_Reg32(SC_PWR_STA) & (0x1 << MM2_SUBSYS))) {
}
}
DPI_STATUS DPI_Init_PLL(unsigned int mipi_pll_clk_ref,unsigned int mipi_pll_clk_div1,unsigned int mipi_pll_clk_div2)
{
MASKREG32(CLK_CFG_5, 0x400, 0x400); // CLK_CFG_5[10] rg_lvds_tv_sel
// 0:dpi0_ck from tvhdmi pll
// 1:dpi0_ck from lvds pll
MASKREG32(CLK_CFG_7, 0x07000000, 0x01000000); // CLK_CFG_7[26:24] lvdspll clock divider selection
// 0: from 26M
// 1: lvds_pll_ck
// 2: lvds_pll_ck/2
// 3: lvds_pll_ck/4
// 4: lvds_pll_ck/8
// CLK_CFG_7[31] 0: clock on, 1: clock off
DRV_SetReg32(LVDSPLL_PWR_CON0, (0x1 << 0)); //PLL_PWR_ON
udelay(2);
DRV_ClrReg32(LVDSPLL_PWR_CON0, (0x1 << 1)); //PLL_ISO_EN
OUTREG32(LVDSPLL_CON1, mipi_pll_clk_div2);
OUTREG32(LVDSPLL_CON0, mipi_pll_clk_div1);
udelay(20);
return DPI_STATUS_OK;
}
static void __gpt_stop(struct gpt_device *dev)
{
DRV_ClrReg32(dev->base_addr + GPT_CON, GPT_CON_ENABLE);
}
static void __gpt_disable_irq(struct gpt_device *dev)
{
DRV_ClrReg32(GPT_IRQEN, 0x1 << (dev->id));
}
void Uboot_power_saving(void)
{
#if 0
u32 u4Val = 0;
#if 0
printf("GPIO Set\n");
/* GPIO48~55, turn-off PWM 0~1 */
DRV_WriteReg32(0x80002660, 0x0555);
/* GPIO56~63, turn-off EINT 0~4 */
DRV_WriteReg32(0x80002670, 0x0015);
/* GPIO64~71, turn-off EINT 5~7, UART4 CTS/RTS */
DRV_WriteReg32(0x80002680, 0x1400);
/* GPIO112~119, turn-off KP Row2~4, CLK_OUT0~4 */
DRV_WriteReg32(0x800026E0, 0x0000);
/* GPIO128~135, Keep I2C SCL2 ,turn-off others */
DRV_WriteReg32(0x80002700, 0x4000);
/* GPIO136~143, Keep I2C SDA2 ,turn-off TRACE signal */
DRV_WriteReg32(0x80002710, 0x0001);
#endif
/* TV power down*/
DRV_ClrReg32(TVENC, 0x13E0);
/* AFE power down*/
DRV_WriteReg32(PDN_AFE_AAPDN, 0);
DRV_WriteReg32(PDN_AFE_AAC_NEW, 0);
DRV_WriteReg32(PDN_AFE_AAC_CON1, 0x0003);
/* MIPI power down
Jett: Don't power down MIPI during uboot, or the DPI signal would
be turned off and the uboot logo is disappeared
*/
#if 0
PW_DEBUG("MIPI power down\n");
DRV_WriteReg32(MIPI_PD_B00, 0);
DRV_WriteReg32(MIPI_PD_B04, 0);
DRV_WriteReg32(MIPI_PD_B08, 0);
DRV_WriteReg32(MIPI_PD_B0C, 0);
DRV_WriteReg32(MIPI_PD_B10, 0);
DRV_WriteReg32(MIPI_PD_B14, 0);
DRV_WriteReg32(MIPI_PD_B18, 0);
DRV_WriteReg32(MIPI_PD_B1C, 0);
DRV_WriteReg32(MIPI_PD_B40, 0);
DRV_WriteReg32(MIPI_PD_B44, 0);
DRV_WriteReg32(MIPI_PD_B48, 0);
DRV_WriteReg32(MIPI_PD_B4C, 0);
DRV_WriteReg32(MIPI_PD_04C, 1);
#endif
/* MCU CG*/
DRV_SetReg32 (APMCUSYS_PDN_SET0, (1<<8)|(1<<9)|(1<<21));
/* MCU memory PDN*/
u4Val = 0;
u4Val = ((1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)|(1<<10)| \
(1<<11)|(1<<12)|(1<<13)|(1<<16) );
DRV_SetReg32 (MCU_MEM_PDN, u4Val);
/* GRAPH1SYS CG*/
DRV_SetReg32 (GRAPH1SYS_CG_SET, (1<<0));
/* GRAPH1SYS memory PDN*/
u4Val = 0;
u4Val = ((1<<2)|(1<<3)|(1<<4)|(1<<6)|(1<<9));
DRV_SetReg32 (G1_MEM_PDN, u4Val);
/* GRAPH2SYS CG */
DRV_SetReg32 (GRAPH2SYS_CG_SET, 0x1FF);
/* GRAPH2SYS memory PDN*/
u4Val = 0;
u4Val = ((1<<0));
DRV_SetReg32 (G2_MEM_PDN, u4Val);
/* GRAPH2SYS MTCMOS */
DRV_SetReg16(ISO_EN, 1<<4);
DRV_SetReg16(IN_ISO_EN, 1<<4 );
DRV_SetReg16(PWR_OFF, 1<<4 );
DRV_SetReg16(ACK_CLR, 0x2);
/* CEVA memory PDN*/
u4Val = 0;
u4Val = ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5));
DRV_SetReg32 (CEVA_MEM_PDN, u4Val);
/* CEVA MTCMOS */
DRV_SetReg16(ISO_EN, 1<<5);
DRV_SetReg16(IN_ISO_EN, 1<<5 );
DRV_SetReg16(PWR_OFF, 1<<5 );
DRV_SetReg16(ACK_CLR, 0x1);
/* Stop CEVA PLL*/
DRV_ClrReg32(CEVAPLL2,1<<0);
/* Stop UPLL*/
DRV_ClrReg32(PDN_CON,1<<4);
/* Stop DPLL*/
#if 0
printf("DPLL Power Down\n");
DRV_ClrReg32(PDN_CON,1<<3);
#endif
/* Stop VUSB */
//pmic_config_interface(0x3D, KAL_FALSE, VUSB_EN_MASK, VUSB_EN_SHIFT); //pmic_vsdio_enable(KAL_TRUE);
#endif
}
void Uboot_power_saving2(void)
{
#if 0
u32 u4Val = 0;
#if 0
printf("GPIO Set\n");
/* GPIO48~55, turn-off PWM 0~1 */
DRV_WriteReg32(0x80002660, 0x0555);
/* GPIO56~63, turn-off EINT 0~4 */
DRV_WriteReg32(0x80002670, 0x0015);
/* GPIO64~71, turn-off EINT 5~7, UART4 CTS/RTS */
DRV_WriteReg32(0x80002680, 0x1400);
/* GPIO112~119, turn-off KP Row2~4, CLK_OUT0~4 */
DRV_WriteReg32(0x800026E0, 0x0000);
/* GPIO128~135, Keep I2C SCL2 ,turn-off others */
DRV_WriteReg32(0x80002700, 0x4000);
/* GPIO136~143, Keep I2C SDA2 ,turn-off TRACE signal */
DRV_WriteReg32(0x80002710, 0x0001);
#endif
/* TV power down*/
DRV_ClrReg32(TVENC, 0x13E0);
/* AFE power down*/
DRV_WriteReg32(PDN_AFE_AAPDN, 0);
DRV_WriteReg32(PDN_AFE_AAC_NEW, 0);
DRV_WriteReg32(PDN_AFE_AAC_CON1, 0x0003);
/* MIPI power down*/
DRV_WriteReg32(MIPI_PD_B00, 0);
DRV_WriteReg32(MIPI_PD_B04, 0);
DRV_WriteReg32(MIPI_PD_B08, 0);
DRV_WriteReg32(MIPI_PD_B0C, 0);
DRV_WriteReg32(MIPI_PD_B10, 0);
DRV_WriteReg32(MIPI_PD_B14, 0);
DRV_WriteReg32(MIPI_PD_B18, 0);
DRV_WriteReg32(MIPI_PD_B1C, 0);
DRV_WriteReg32(MIPI_PD_B40, 0);
DRV_WriteReg32(MIPI_PD_B44, 0);
DRV_WriteReg32(MIPI_PD_B48, 0);
DRV_WriteReg32(MIPI_PD_B4C, 0);
DRV_WriteReg32(MIPI_PD_04C, 1);
#if 1
/* MCU CG*/
DRV_SetReg32 (APMCUSYS_PDN_SET0, (1<<8)|(1<<9)|(1<<21));
/* MCU memory PDN*/
u4Val = 0;
u4Val = ((1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)|(1<<10)| \
(1<<11)|(1<<12)|(1<<13)|(1<<16) );
DRV_SetReg32 (MCU_MEM_PDN, u4Val);
#endif
#if 1
/* GRAPH1SYS CG*/
DRV_SetReg32 (GRAPH1SYS_CG_SET, (1<<0));
/* GRAPH1SYS memory PDN*/
u4Val = 0;
u4Val = ((1<<2)|(1<<3)|(1<<4)|(1<<6)|(1<<9));
DRV_SetReg32 (G1_MEM_PDN, u4Val);
/* GRAPH2SYS CG */
DRV_SetReg32 (GRAPH2SYS_CG_SET, 0x1FF);
/* GRAPH2SYS memory PDN*/
u4Val = 0;
u4Val = ((1<<0));
DRV_SetReg32 (G2_MEM_PDN, u4Val);
/* GRAPH2SYS MTCMOS */
DRV_SetReg16(ISO_EN, 1<<4);
DRV_SetReg16(IN_ISO_EN, 1<<4 );
DRV_SetReg16(PWR_OFF, 1<<4 );
DRV_SetReg16(ACK_CLR, 0x2);
#endif
/* CEVA memory PDN*/
u4Val = 0;
u4Val = ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5));
DRV_SetReg32 (CEVA_MEM_PDN, u4Val);
/* CEVA MTCMOS */
//printf("CEVA MTCMOS\n");
DRV_SetReg16(ISO_EN, 1<<5);
DRV_SetReg16(IN_ISO_EN, 1<<5 );
DRV_SetReg16(PWR_OFF, 1<<5 );
DRV_SetReg16(ACK_CLR, 0x1);
#if 1
/* Stop CEVA PLL*/
DRV_ClrReg32(CEVAPLL2,1<<0);
#endif
/* Stop UPLL*/
DRV_ClrReg32(PDN_CON,1<<4);
/* Stop DPLL*/
#if 0
printf("DPLL Power Down\n");
DRV_ClrReg32(PDN_CON,1<<3);
#endif
#endif
}
unsigned int hacc_init(AES_KEY_SEED *keyseed)
{
unsigned int i = 0;
unsigned int *config;
unsigned int ret = 0;
hacc_deinit();
/* DRV_WriteReg32(HACC_SECINIT0, HACC_SECINIT0_MAGIC); */
/* DRV_WriteReg32(HACC_SECINIT1, HACC_SECINIT1_MAGIC); */
/* DRV_WriteReg32(HACC_SECINIT2, HACC_SECINIT2_MAGIC); */
/* clear aes module */
DRV_SetReg32(HACC_ACON2, HACC_AES_CLR);
/* set aes module in cbc mode with no byte order change */
DRV_ClrReg32(HACC_ACON2, HACC_AES_CHG_BO_MASK | HACC_AES_MODE_MASK);
DRV_SetReg32(HACC_ACON2, HACC_AES_CHG_BO_OFF | HACC_AES_CBC);
/* aes secure initialiation */
memset(&hacc_ctx, 0, sizeof(struct hacc_context));
for (i = 0; i < keyseed->size; i++)
hacc_ctx.sw_key[i] = keyseed->seed[i];
config = (unsigned int *)&hacc_ctx.cfg.config[0];
*config++ = HACC_CFG_0;
*config++ = HACC_CFG_1;
*config++ = HACC_CFG_2;
*config = HACC_CFG_3;
ret = hacc_set_cfg(&hacc_ctx.cfg);
if (SEC_OK != ret)
goto _end;
ret = hacc_set_mode(AES_CBC_MODE);
if (SEC_OK != ret)
goto _end;
/* derive the hardware wrapper key */
ret = hacc_set_key(AES_HW_KEY, HACC_HW_KEY_SZ);
if (SEC_OK != ret)
goto _end;
ret = hacc_do_aes(AES_ENC, &hacc_ctx.sw_key[0], &hacc_ctx.hw_key[0], AES_KEY_256);
if (SEC_OK != ret)
goto _end;
ret = hacc_set_key(AES_HW_WRAP_KEY, AES_KEY_256);
if (SEC_OK != ret)
goto _end;
hacc_test();
/* from now on, HACC HW wrap key can be used */
bHACC_HWWrapKeyInit = 1;
/* from now on, HACC SW key can be used */
bHACC_SWKeyInit = 1;
_end:
return ret;
}
