/*
* FUNCTION
* GPT_ResetTimer
*
* DESCRIPTION
* This function is to setup GPT parameters
*
* CALLS
* It is called to setup GPT parameters
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
* countValue = GPT count
* autoReload = KAL_TRUE,autoReload mode
* KAL_FALSE, Single shot mode
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_ResetTimer(kal_uint8 timerNum,kal_uint16 countValue,kal_bool autoReload)
{
if (timerNum == 1)
{
DRV_WriteReg(GPT1_LEN,countValue);
if (autoReload == KAL_TRUE)
{
DRV_Reg(GPT1_CTRL) |= GPT_CTRL_AUTOMODE;
}
else
{
DRV_Reg(GPT1_CTRL) &= ~GPT_CTRL_AUTOMODE;
}
}
if (timerNum == 2)
{
DRV_WriteReg(GPT2_LEN,countValue);
if (autoReload == KAL_TRUE)
{
DRV_Reg(GPT2_CTRL) |= GPT_CTRL_AUTOMODE;
}
else
{
DRV_Reg(GPT2_CTRL) &= ~GPT_CTRL_AUTOMODE;
}
}
}
void MT6302_spiPowerCtrl(kal_bool on)
{
kal_uint32 i;
if(0 == MT6302_getSPIInterface())
{
if(31 < MT6302_LCD_pdnHandle)
ASSERT(0);
if (KAL_FALSE == on)
lcd_clk_disable(MT6302_LCD_pdnHandle);
else if(KAL_TRUE == on){
lcd_clk_enable(MT6302_LCD_pdnHandle);
if(DRVPDN_CON1_LCD & DRV_Reg(DRVPDN_CON1))
ASSERT(0);
i = 1000;
while(i)
i--;
}
else
ASSERT(0);
}
else if(1 == MT6302_getSPIInterface())
{
/*we don't know should we do power control before want to write SPI in GPIO implementation*/
}
else{
IMPLEMENTING_ASSERT;
}
drv_trace8(TRACE_GROUP_4, SIM_GEMINI_GEN1, FILE_MT6302_SPI, __LINE__,
on, DRV_Reg(DRVPDN_CON1), MT6302_getSPIInterface(), MT6302_LCD_pdnHandle,
drv_get_current_time(), 0
);
}
/**********************************************************
Description : Wait for 32KHz clock srouce stable.
Input : None
Output : None
***********************************************************/
void WaitFor32KStable(void)
{
kal_uint32 result;
kal_uint16 result_low;
kal_uint16 result_high;
* (volatile kal_uint16 *) DRVPDN_CON2_CLR = DRVPDN_CON2_TDMA;
DRV_WriteReg(SM_FMDURATION,0);
while(1)
{
DRV_Reg(SM_CTRL) |= SM_CTRL_FM_START;
while(!(DRV_Reg(SM_STAT) & SM_STAT_FM_RDY));
result_low = DRV_Reg(SM_FM_RESULT_LOW);
result_high = DRV_Reg(SM_FM_RESULT_HIGH) & SM_FM_RESULT_HIGH_MASK;
result = (result_low | (result_high << 16));
if ((result < 950) && (result > 650))
break;
}
* (volatile kal_uint16 *) DRVPDN_CON2_SET = DRVPDN_CON2_TDMA;
}
static void tv_power_on(void)
{
kal_uint32 save_irq_mask;
/// Turn off TV PLL clock
#if defined(DRV_TVOUT_6228_SERIES)
DRV_Reg(DRVPDN_CON0_CLR) = DRVPDN_CON0_TPLL;
#elif defined(DRV_TVOUT_6238_SERIES)
//KKKKK
DRV_WriteReg(TPLL,0xe0);
DRV_WriteReg(TPLL2,0x0);
#endif
/// Power on TV module
DRV_Reg(DRVPDN_CON3_CLR) = DRVPDN_CON3_TV;
save_irq_mask=SaveAndSetIRQMask();
UPLL_Enable(UPLL_OWNER_TV);
RestoreIRQMask(save_irq_mask);
tv_operation_state=TV_DETECTION_STATE;
/* turn on TV DAC */
ENABLE_TV_HALF_BIAS_POWER;
ENABLE_TV_DAC2_POWER;
ENABLE_TV_DAC1_POWER;
ENABLE_TV_DAC0_POWER;
ENABLE_TV_BGVREF_POWER;
ENABLE_TV_DAC_POWER;
ENABLE_TV_ENCODER;
} /* tv_power_on() */
/*
* FUNCTION
* GPTI_BusyWait
*
* DESCRIPTION
* Use GPT2 as a counter to perform a busy waiting
*
* CALLS
*
* PARAMETERS
* len: length of the counter in unit of 1ms
*
* RETURNS
* None
*
* GLOBALS AFFECTED
*
*/
void GPTI_BusyWait(kal_uint16 len)
{
// disable PDN
#if defined(DRV_MISC_PDN_NO_SET_CLR)
DRV_Reg(DRVPDN_CON1) &= ~DRVPDN_CON1_GPT;
#else
DRV_WriteReg(DRVPDN_CON1_CLR, DRVPDN_CON1_GPT);
#endif
DRV_WriteReg(GPT2_LEN, len);
DRV_WriteReg(GPT2_PRESCALER, clk_1k); // 1K HZ
// one shot
DRV_WriteReg(GPT2_CTRL, GPT_CTRL_Enable);
while(!(DRV_Reg(GPT_STS) & GPT_STS_2));
// set PDN
#if defined(DRV_MISC_PDN_NO_SET_CLR)
DRV_Reg(DRVPDN_CON1) |= DRVPDN_CON1_GPT;
#else
DRV_WriteReg(DRVPDN_CON1_SET, DRVPDN_CON1_GPT);
#endif
}
static void tv_power_off(void)
{
kal_uint32 save_irq_mask;
/* turn off TV DAC */
DISABLE_TV_HALF_BIAS_POWER;
DISABLE_TV_DAC2_POWER;
DISABLE_TV_DAC1_POWER;
DISABLE_TV_DAC0_POWER;
DISABLE_TV_BGVREF_POWER;
DISABLE_TV_DAC_POWER;
DISABLE_TV_ENCODER;
DISABLE_TV_CONTROLLER;
RESET_TV_CONTROLLER;
tv_src_width=0;
tv_src_height=0;
/// Turn off TV PLL clock
#if defined(DRV_TVOUT_6228_SERIES)
DRV_Reg(DRVPDN_CON0_SET) = DRVPDN_CON0_TPLL;
#elif defined(DRV_TVOUT_6238_SERIES)
//KKKKK
DRV_WriteReg(TPLL2,0x1);
#endif
/// Power off TV module
DRV_Reg(DRVPDN_CON3_SET) = DRVPDN_CON3_TV;
save_irq_mask=SaveAndSetIRQMask();
UPLL_Disable(UPLL_OWNER_TV);
RestoreIRQMask(save_irq_mask);
tv_operation_state=TV_IDLE_STATE;
} /* tv_power_off() */
void idc_uart_hisr(void)
{
kal_uint16 IIR, LSR, RXTRIG;
IIR = DRV_Reg(IDC_UART_IIR);
LSR = DRV_Reg(IDC_UART_LSR);
RXTRIG = DRV_Reg(IDC_UART_RXTRIG);
if (IIR & IDC_UART_IIR_INT_INVALID)
{
IRQClearInt(MD_IRQID_IDC2ARM);
#if !defined(__UNIFIED_ISR_LEVEL__)
IRQUnmask(MD_IRQID_IDC2ARM);
#endif
return;
}
idc_hisr_time[idc_hisr_count] = DRV_Reg32(FRC_VAL_R);
idc_hisr_count++;
if (idc_hisr_count == 20)
{
idc_hisr_count = 0;
}
idc_send_rx_data_by_ilm();
if (KAL_FALSE == idc_read_RBR)
{
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_ERROR, 0, IDC_RX_HISR_MSG, IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
#else
kal_sprintf(idc_dbg_str, "drv_idc: HISR without Read Data, IIR = %x, LSR = %x, RXTRIG = %x, (%d, %d, %d)\n\r",
IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
DT_IDC_PRINTF(idc_dbg_str);
#endif
ASSERT(0);
}
else if (((LSR & 0x9F) != 0x1) || (IIR != 0xc4))
{
#if !defined(ATEST_DRV_ENABLE)
dhl_trace(TRACE_ERROR, 0, IDC_RX_EXCEPTION_MSG, IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
#else
kal_sprintf(idc_dbg_str, "drv_idc: Exception occur, IIR = %x, LSR = %x, RXTRIG = %x, (%d, %d, %d)\n\r",
IIR, LSR, RXTRIG, idc_port.main_state, idc_port.owner_id, idc_port.intr_en);
DT_IDC_PRINTF(idc_dbg_str);
#endif
}
else if (RXTRIG == 0);
idc_read_RBR = KAL_FALSE;
IRQClearInt(MD_IRQID_IDC2ARM);
#if !defined(__UNIFIED_ISR_LEVEL__)
IRQUnmask(MD_IRQID_IDC2ARM);
#endif
return;
}
/*************************************************************************
* FUNCTION
* keypad_check_fullpress
*
* DESCRIPTION
* This function is to check if 2step key is pressed
*
* PARAMETERS
* none
*
* RETURNS
* True or False
*
* GLOBALS AFFECTED
*
*************************************************************************/
kal_bool keypad_check_fullpress(void)
{
kal_uint16 iKey;
kal_uint16 key_reg, key_bit, key_status;
iKey = CUSTOM_2STEP_SEC_KEY_ROW * 9 + CUSTOM_2STEP_SEC_KEY_COL;
key_reg = iKey / 16;
key_bit = 0x0001 << (iKey & 0xF);
switch (key_reg) {
case low_key:
key_status = DRV_Reg(KP_LOW_KEY);
break;
#if defined(DRV_KBD_32KEYS_ABOVE)
case medium_key:
key_status = DRV_Reg(KP_MID_KEY);
break;
#endif
#if defined(DRV_KBD_48KEYS_ABOVE)
case medium_key:
key_status = DRV_Reg(KP_MID_KEY);
break;
case medium_key1:
key_status = DRV_Reg(KP_MID1_KEY);
break;
#endif
#if defined(DRV_KBD_64KEYS_ABOVE)
case medium_key:
key_status = DRV_Reg(KP_MID_KEY);
break;
case medium_key1:
key_status = DRV_Reg(KP_MID1_KEY);
break;
case medium_key2:
key_status = DRV_Reg(KP_MID2_KEY);
break;
#endif
case high_key:
key_status = DRV_Reg(KP_HI_KEY);
break;
default:
ASSERT(0);
break;
}
if ((DRV_Reg(KP_STS) & KP_STS_KEYPRESS) && ((~key_status) & key_bit)) {
return KAL_TRUE;
}else {
return KAL_FALSE;
}
}
void DRVPDN_ON(kal_uint32 addr,kal_uint16 code,PDN_DEVICE hanlde) //change name
{
#if ( (defined(MT6205)) || (defined(MT6208)) )
kal_uint32 savedMask;
savedMask = SaveAndSetIRQMask();
DRV_Reg(addr) &= (~code);
RestoreIRQMask(savedMask);
#else
DRV_Reg(addr+0x20) = code;
#endif /*MT6205B,MT6218*/
}
/*
* FUNCTION
* GPIO_DinvSetup
*
* DESCRIPTION
* This function is to enable data invert of the related GPIO pin
*
* PARAMETERS
* enable: enable the data inversion
*
* RETURNS
* None
*
* GLOBALS AFFECTED
*
*/
void GPIO_DinvSetup(kal_uint16 pin, kal_bool enable)
{
kal_uint16 modeno;
kal_uint16 remainder;
modeno = pin/16;
remainder = pin % 16;
if(enable)
DRV_Reg(GPIO_DINV_ADRS(modeno)) |= (1 << remainder);
else
DRV_Reg(GPIO_DINV_ADRS(modeno)) &= ~(1 << remainder);
}
void USBDL_CLK_ON(kal_bool turn_on)
{
#if defined(DRV_UPLL_V1)
DRV_Reg(DRVPDN_CON0_CLR) |= DRVPDN_CON0_UPLL;
#elif defined(DRV_UPLL_V2)
/* hardware issue */
USB_PDNDisable(USB_PDN_OWNER_UPLL);
DRV_Reg(DRVPDN_CON0_CLR) |= DRVPDN_CON0_UPLL;
#elif defined(DRV_UPLL_V3)
/* select UPLL clock source from PLL */
DRV_Reg(PLL) |= 0x0040;
#elif defined(DRV_UPLL_V4)
DRV_Reg(DRVPDN_CON0) &= (~DRVPDN_CON0_PLL2);
/* disable USB clock from external clock */
DRV_Reg(CLK_CON) &= ~0x4000;
DRV_Reg(PLLSEL) |= 0x0008;
#elif defined(DRV_UPLL_V5)
/* This will be changed in 6238 E2 */
DRV_Reg(PLL) |= 0x0040;
#elif defined(DRV_USB_UPLL_MT50_SERIES)
if (SW_SEC_0 == INT_SW_SecVersion())
{
//DRV_Reg(0xA0010320) |= 0x0800;
PDN_CLR(PDN_USB_48M);
}
#endif
#if defined(MT6276)
DRV_Reg(0x61140280) |= 0x0080;
#endif
}
void PWM2_Configure(kal_uint32 freq, kal_uint8 duty)
{
kal_uint32 clock;
kal_uint32 tmp;
kal_uint16 clkdiv;
kal_uint16 reg;
ASSERT(duty <= 100);
PWM2_FRE_SAVE=freq;
PWM2_DUTY_SAVE=duty;
reg = DRV_Reg(PWM2_CTRL);
clkdiv = (1 << (reg & 0x0003));
if (reg & 0x0004)
clock = 32000;
else
clock = 13000000;
clock = clock/clkdiv;
if(0==freq)
tmp = clock/(freq+1);
else
tmp = clock/(freq);
tmp--;
DRV_WriteReg(PWM2_COUNT,(kal_uint16)tmp);
tmp = ((tmp+1)*duty)/100;
DRV_WriteReg(PWM2_THRESHOLD,(kal_uint16)tmp);
}
//----------------------------Sccb internal arbiteration------------------------------
//--When return from this function, I bit is turned off!!--
static kal_uint32 i2c_wait_transaction_complete_and_lock(SCCB_OWNER owner)
{
kal_uint32 savedMask;
while(1)
{
if(i2c_status.state==SCCB_READY_STATE)
{
savedMask = SaveAndSetIRQMask();
#if defined(I2C_DEBUG)
LT=DRV_Reg(0x80200000);
#endif
if(i2c_status.state==SCCB_READY_STATE) //The sccb is currently free
{
i2c_status.state=SCCB_BUSY_STATE; //Lock it
i2c_status.owner=owner;
I2C_POWER_ON;
return savedMask;
}
else
RestoreIRQMask(savedMask); // What a pity, that the handle is locked by somebody again. back to waiting loop
}
else if(sccb_handle[owner].sccb_config.get_handle_wait==KAL_FALSE)
return 0;
}//end of while
}
/* INPUT */
input.MK0 = (kal_int16) input_mk; /* LSB */
input.MK1 = (kal_int16)(input_mk >> 16); /* MSB */
input.DIRECTION = direction; /*decipher=1;cipher=0*/
key_ptr = (kal_uint8 *)&key;
DRVPDN_Disable(DRVPDN_CON0,DRVPDN_CON0_GCU,PDN_GCU);
GCU_InputData(&input);
if(cipher_algo == 1) /*A5_1 == 1*/
GCU_GEA1Start(); /* for uplink link. According to spec. 04.64 */
else if(cipher_algo == 2)
GCU_GEA2Start(); /* for uplink link. According to spec. 04.64 */
#if defined(DRV_GCU_GEA3)
else if(cipher_algo == 3)
GCU_GEA3Start();
#endif
else
ASSERT(0);
for(index1=0;index1 < ((buff_len+3)/4);index1++)
{
GCU_ReadKey(key);
for(index2=0;index2 < 4;index2++)
{
if((index1*4+index2) == buff_len)
break;
#if defined(DRV_GCU_GEA3) // Julie : GEA3 RBO reverse with bithe GEA1 and GEA2
if(cipher_algo == 3)
dest_buff_ptr[(index1*4+index2)] = src_buff_ptr[(index1*4+index2)] ^ key_ptr[3-index2];
else
dest_buff_ptr[(index1*4+index2)] = src_buff_ptr[(index1*4+index2)] ^ key_ptr[index2];
#else
dest_buff_ptr[(index1*4+index2)] = src_buff_ptr[(index1*4+index2)] ^ key_ptr[index2];
#endif
}
}
DRVPDN_Enable(DRVPDN_CON0,DRVPDN_CON0_GCU,PDN_GCU);
return KAL_TRUE;
}
#ifdef DRV_GCU_REV_BIT_DISABLE/*only 6218B has this, Others projects dont have*/
void GCU_Disable_ReverseBit(void)
{
DRVPDN_Disable(DRVPDN_CON0,DRVPDN_CON0_GCU,PDN_GCU);
// clear GCU reverse bit
DRV_Reg(GCU_CTRL) &= ~GCU_CTRL_RBO;
DRVPDN_Enable(DRVPDN_CON0,DRVPDN_CON0_GCU,PDN_GCU);
}
/*
* FUNCTION
* adc_sche_measure
*
* DESCRIPTION
* This function is to measure ADC channel.
*
* CALLS
*
* PARAMETERS
* adc_sche_id: logical channel id
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* None
*/
void adc_sche_measure(void* msg_ptr)
{
MeasParameter *adc_param = (MeasParameter *)msg_ptr;
#if ( (defined(MT6205B))||defined(MT6226M) || (defined(MT6218))|| (defined(MT6218B))|| (defined(MT6219))|| (defined(MT6217))|| (defined(MT6225))|| (defined(MT6228))|| (defined(MT6229))|| (defined(MT6230))|| (defined(MT6226))|| (defined(MT6227)))
#ifdef BMT_DEBUG
//dbg_printWithTime("mea,%d..\r\n",adc_param->adc_logic_id);
#endif
#if 0
/* under construction !*/
/* under construction !*/
#endif
adc_parameters[adc_param->adc_logic_id].adc_sche_event_id = NULL;
if (adc_parameters[adc_param->adc_logic_id].conti_measure)
{
#if !defined(__CHARGER_WITH_IMMEDIMATE_ADC__)
kal_uint32 savedMask;
savedMask = SaveAndSetIRQMask();
adc_sync_mode_on = KAL_TRUE;
adc_pwrdown_disable();
DRV_Reg(AUXADC_SYNC) |= (1<<adc_param->adc_phy_id);
RestoreIRQMask(savedMask);
#endif
adc_sche_rw_status |= (1 << adc_param->adc_logic_id);
adc_sche_set_timer(adc_param->adc_logic_id,1,adc_sche_readback);
}
#endif /*MT6205B,MT6218, MT6218B*/
}
static void mtk_wdt_reset(char mode)
{
/* Watchdog Rest */
unsigned short wdt_mode_val;
DRV_WriteReg16(MTK_WDT_RESTART, MTK_WDT_RESTART_KEY);
wdt_mode_val = DRV_Reg(MTK_WDT_MODE);
/* clear autorestart bit: autoretart: 1, bypass power key, 0: not bypass power key */
wdt_mode_val &=(~MTK_WDT_MODE_AUTO_RESTART);
/* make sure WDT mode is hw reboot mode, can not config isr mode */
wdt_mode_val &=(~(MTK_WDT_MODE_IRQ|MTK_WDT_MODE_ENABLE));
if(mode){ /* mode != 0 means by pass power key reboot, We using auto_restart bit as by pass power key flag */
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN|MTK_WDT_MODE_AUTO_RESTART);
//DRV_WriteReg(MTK_WDT_MODE, wdt_mode_val);
//DRV_WriteReg(MTK_WDT_MODE, (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN|MTK_WDT_MODE_AUTO_RESTART));
}else{
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN);
//DRV_WriteReg(MTK_WDT_MODE,wdt_mode_val);
//DRV_WriteReg(MTK_WDT_MODE, (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN));
}
DRV_WriteReg(MTK_WDT_MODE,wdt_mode_val);
//DRV_WriteReg(MTK_WDT_LENGTH, MTK_WDT_LENGTH_KEY);
gpt_busy_wait_us(100);
DRV_WriteReg(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY);
}
/*
* FUNCTION
* GPT_Stop
*
* DESCRIPTION
* Stop GPT timer
*
* CALLS
* It is called to stop GPT timer
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_Stop(kal_uint8 timerNum)
{
kal_uint16 gpt_ctrl1;
kal_uint16 gpt_ctrl2;
#if defined(DRV_GPT_GPT3)
kal_uint16 gpt_ctrl3;
#endif
gpt_ctrl1 = DRV_Reg(GPT1_CTRL);
gpt_ctrl2 = DRV_Reg(GPT2_CTRL);
#if defined(DRV_GPT_GPT3)
gpt_ctrl3 = DRV_Reg(GPT3_CTRL);
#endif
if (timerNum == 1)
{
gpt_ctrl1 &= ~GPT_CTRL_Enable;
DRV_WriteReg(GPT1_CTRL,gpt_ctrl1);
}
if (timerNum == 2)
{
gpt_ctrl2 &= ~GPT_CTRL_Enable;
DRV_WriteReg(GPT2_CTRL,gpt_ctrl2);
}
#if defined(DRV_GPT_GPT3)
if (timerNum == 3)
{
gpt_ctrl3 =(kal_uint16) ~GPT3_ENABLE;
DRV_WriteReg(GPT3_CTRL,gpt_ctrl3);
}
if ( (((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0)&& (!(gpt_ctrl3&GPT3_ENABLE)))
#else
if ( ((gpt_ctrl1|gpt_ctrl2)&GPT_CTRL_Enable)==0 )
#endif
{
kal_uint16 GPT_Status;
GPT_Status = DRV_Reg(GPT_STS);
IRQMask(IRQ_GPT_CODE);
IRQClearInt(IRQ_GPT_CODE);
#ifdef GPT_DRVPDN_FAST
DRVPDN_ENABLE2(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#else
DRVPDN_Enable(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#endif
}
}
void DRV_PDN_DIS(void *parameter)
{
PDN_INPUT *pdn_data = (PDN_INPUT *)parameter;
#if defined(MT6208) || defined(MT6205)
DRV_Reg(pdn_data->addr) |= pdn_data->code;
#else
DRV_WriteReg((pdn_data->addr+0x20), pdn_data->code);
#endif
}
static void mtk_wdt_disable(void)
{
u16 tmp;
tmp = DRV_Reg(MTK_WDT_MODE);
tmp &= ~MTK_WDT_MODE_ENABLE; /* disable watchdog */
tmp |= (MTK_WDT_MODE_KEY); /* need key then write is allowed */
DRV_WriteReg(MTK_WDT_MODE,tmp);
}
/* config SRAM back from L2 cache for DA relocation */
void config_shared_SRAM_size(void)
{
volatile unsigned int cache_cfg;
/* set L2C size to 256KB */
cache_cfg = DRV_Reg(MCUSYS_CFGREG_BASE);
cache_cfg &= (~0x7) << L2C_SIZE_CFG_OFF;
cache_cfg |= 0x1 << L2C_SIZE_CFG_OFF;
DRV_WriteReg(MCUSYS_CFGREG_BASE, cache_cfg);
}
void hw_watchdog_disable(void)
{
u16 tmp;
tmp = DRV_Reg(MT6573_WDT_MODE);
tmp &= ~MT6573_WDT_MODE_ENABLE; /* disable watchdog */
tmp |= (MT6573_WDT_MODE_KEY); /* need key then write is allowed */
DRV_WriteReg(MT6573_WDT_MODE,tmp);
}
/*conf_data = 0~3*/
void GPO_ModeSetup(kal_uint16 pin, kal_uint16 conf_dada)
{
kal_uint16 mode;
mode = DRV_Reg(GPI_O_MODE);
mode &= ~(0x0003 << (pin*2));
mode |= (conf_dada << (pin*2));
DRV_WriteReg(GPI_O_MODE,mode);
}
kal_uint16 drv_reg_dbg_trace_read16(kal_uint16 line, kal_uint32 addr)
{
kal_uint16 value;
kal_uint32 savedMask;
savedMask = SaveAndSetIRQMask();
value = DRV_Reg(addr);
drv_reg_dbg_trace(0, line, addr, value);
RestoreIRQMask(savedMask);
return value;
}
/*************************************************************************
* FUNCTION
* PDN_iniEnable
*
* DESCRIPTION
*
* CALLS
*
* PARAMETERS
* MTK_SLEEP_ENABLE is to enable sleep mode
* DRV_SLEEPONLY is only to enable drver sleep mode
*
* RETURNS
*
* GLOBALS AFFECTED
*
* HISTORY
* NAME DATE REMARKS
* Jessen Hu 04-03-2002 Create initial version 1.0
* Rex Luo 04-03-2002 Add comements and function description
*
*************************************************************************/
void DRVPDN_Enable(kal_uint32 addr,kal_uint16 code,kal_uint8 handle)
{
#if defined(MT6205) || defined(MT6208)
kal_uint32 savedMask;
savedMask = SaveAndSetIRQMask();
if ((code == DRVPDN_CON1_UART1) ||
(code == DRVPDN_CON1_UART2)
)
{
;
}
else
DRV_Reg(addr) |= code;
#ifdef MTK_SLEEP_ENABLE
L1SM_SleepEnable(PDNhandle[handle]);
#endif /*MTK_SLEEP_ENABLE*/
RestoreIRQMask(savedMask);
#else /* MT6205 || MT6208 */
#if defined(MT6208) || defined(MT6205B) || defined(MT6218B) || defined(MT6217)
if ((code == DRVPDN_CON1_UART1) || (code == DRVPDN_CON1_UART2))
#else /* MT6208, MT6205B, MT6218B, MT6217 */
if ((code == DRVPDN_CON1_UART1) || (code == DRVPDN_CON1_UART2) || (code == DRVPDN_CON1_UART3))
#endif /* MT6208, MT6205B, MT6218B, MT6217 */
{
;
}
else
DRV_Reg(addr+0x10) = code;
#ifdef MTK_SLEEP_ENABLE
L1SM_SleepEnable(PDNhandle[handle]);
#endif /*MTK_SLEEP_ENABLE*/
#endif /*MT6205B,MT6218*/
}
/*
* FUNCTION
* GCU_isBUZY
*
* DESCRIPTION
* check whether GCU is computing new keyn stream
*
* CALLS
*
* PARAMETERS
* None
*
* RETURNS
* KAL_TRUE, GCU is computing new keyn stream
* KAL_FALSE, GCU isn't computing new keyn stream
*
* GLOBALS AFFECTED
* external_global
*/
kal_bool GCU_isBUZY(void)
{
kal_uint16 STAT = DRV_Reg(GCU_STAT);
if (STAT & GCU_STAT_BUZY)
{
return KAL_TRUE;
}
else
{
return KAL_FALSE;
}
}
/*conf_data = 0~3*/
void GPO_ModeSetup(kal_uint16 pin, kal_uint16 conf_dada)
{
kal_uint16 mode;
kal_uint32 savedMask;
savedMask = SAVEANDSETIRQMASK();
mode = DRV_Reg(GPIO_MODE4);
mode &= ~(0x0003 << (pin*2));
mode |= (conf_dada << (pin*2));
DRV_WriteReg(GPIO_MODE4,mode);
RESTOREIRQMASK(savedMask);
}
void B2PSI_write_fast(kal_uint8 data, kal_uint16 register_index)
{
#ifdef __USB_DOWNLOAD__
kal_uint16 write_data=0;
kal_uint16 i, status=0;
// extern kal_uint8 pmic_reg_save[];
#if defined(__DRV_B2SPI_SHARE_PIN__)
b2spi_serial_lock();
B2PSI_init_sharePin();
#endif
write_data=(register_index|B2PSI_WRITE_MASK|data);
DRV_WriteReg(DRVPDN_CON1+0x20,(kal_uint16)DRVPDN_CON1_B2SPI);
#if (defined(SUPERMAN29_DEMO_BB)&&defined(PCB01))
GPIO_WriteIO(0, B2PSI_CS_PIN);
for(debug_loop=0;debug_loop<debug_loop_cnt;debug_loop++){};
#endif
//L1D_MeasureMaxDuration_Start( &b2psi_duration );
DRV_WriteReg(B2PSI_DATA,B2PSI_DATA_KEY);
#if (defined(SUPERMAN29_DEMO_BB)&&defined(PCB01))
GPIO_WriteIO(1, B2PSI_CS_PIN);
#endif
/*this short loop is becasue B2PSI needs this to change his state machine*/
for(i=0;i<B2SPI_WAIT_CNT;i++){}
#if (defined(SUPERMAN29_DEMO_BB)&&defined(PCB01))
GPIO_WriteIO(0, B2PSI_CS_PIN);
for(debug_loop=0;debug_loop<debug_loop_cnt;debug_loop++){};
#endif
DRV_WriteReg(B2PSI_DATA,write_data);
//L1D_MeasureMaxDuration_Stop( &b2psi_duration );
/*write data to reg_save*/
//pmic_reg_save[(register_index>>PMIC_SHIFT_BITS)]=data;
//dbg_data=data;
//dbg_index=register_index;
do
{
status=DRV_Reg(B2PSI_STAT);
}
while(!(status&=0x2));
#if (defined(SUPERMAN29_DEMO_BB)&&defined(PCB01))
GPIO_WriteIO(1, B2PSI_CS_PIN);
#endif
#if defined(__DRV_B2SPI_SHARE_PIN__)
serial_init_sharePin();
b2spi_serial_unlock();
#endif
DRV_WriteReg(DRVPDN_CON1+0x10,(kal_uint16)DRVPDN_CON1_B2SPI);
#endif /* __USB_DOWNLOAD__ */
}
/*************************************************************************
* FUNCTION
* PDN_iniEnable
*
* DESCRIPTION
*
* CALLS
*
* PARAMETERS
* MTK_SLEEP_ENABLE is to enable sleep mode
* DRV_SLEEPONLY is only to enable drver sleep mode
*
* RETURNS
*
* GLOBALS AFFECTED
*
* HISTORY
* NAME DATE REMARKS
* Jessen Hu 04-03-2002 Create initial version 1.0
* Rex Luo 04-03-2002 Add comements and function description
*
*************************************************************************/
void DRVPDN_Disable(kal_uint32 addr,kal_uint16 code,kal_uint8 handle)
{
#if ( (defined(MT6205)) || (defined(MT6208)) )
kal_uint32 savedMask;
savedMask = SaveAndSetIRQMask();
DRV_Reg(addr) &= (~code);
#ifdef MTK_SLEEP_ENABLE
L1SM_SleepDisable(PDNhandle[handle]);
#endif /*MTK_SLEEP_ENABLE*/
RestoreIRQMask(savedMask);
#else
DRV_Reg(addr+0x20) = code;
#ifdef MTK_SLEEP_ENABLE
L1SM_SleepDisable(PDNhandle[handle]);
#endif /*MTK_SLEEP_ENABLE*/
#endif /*MT6205B,MT6218*/
}
void PWM1_Stop(void)
{
#if defined(DRV_PWM_CLK_SEL)
kal_uint16 reg;
kal_uint32 clock;
reg = DRV_Reg(PWM1_CTRL);
if (reg & 0x0004)
clock = 32000;
else
clock = 13000000;
DRV_WriteReg(DRVPDN_CON1_SET,DRVPDN_CON1_PWM);
#if defined(MTK_SLEEP_ENABLE) && !defined(__FUE__)
if(clock == 13000000)
L1SM_SleepEnable(PWM1_PDNhandle);
#endif
#else /*!(DRV_PWM_CLK_SEL)*/
kal_uint32 savedMask;
savedMask = SaveAndSetIRQMask();
DRV_Reg(DRVPDN_CON1) |= DRVPDN_CON1_PWM;
RestoreIRQMask(savedMask);
#endif /*DRV_PWM_CLK_SEL*/
}
/*
* FUNCTION
* GPT_Start
*
* DESCRIPTION
* Start GPT timer
*
* CALLS
* It is called to start GPT timer
*
* PARAMETERS
* timerNum = 1(GPT1) or 2(GPT2)
*
* RETURNS
* None
*
* GLOBALS AFFECTED
* external_global
*/
void GPT_Start(kal_uint8 timerNum)
{
if (timerNum == 1)
{
DRV_Reg(GPT1_CTRL) |= GPT_CTRL_Enable;
}
if (timerNum == 2)
{
DRV_Reg(GPT2_CTRL) |= GPT_CTRL_Enable;
}
#if defined(DRV_GPT_GPT3)
if (timerNum == 3)
{
DRV_Reg(GPT3_CTRL) |= GPT3_ENABLE;
}
#endif
#ifdef GPT_DRVPDN_FAST
DRVPDN_DISABLE2(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#else
DRVPDN_Disable(DRVPDN_CON1,DRVPDN_CON1_GPT,PDN_GPT);
#endif
IRQUnmask(IRQ_GPT_CODE);
}
