static void __gpt_start(struct gpt_device *dev) { DRV_SetReg32(dev->base_addr + GPT_CON, GPT_CON_ENABLE); }
void Uboot_power_saving2(void) { #if 0 u32 u4Val = 0; #if 0 printf("GPIO Set\n"); /* GPIO48~55, turn-off PWM 0~1 */ DRV_WriteReg32(0x80002660, 0x0555); /* GPIO56~63, turn-off EINT 0~4 */ DRV_WriteReg32(0x80002670, 0x0015); /* GPIO64~71, turn-off EINT 5~7, UART4 CTS/RTS */ DRV_WriteReg32(0x80002680, 0x1400); /* GPIO112~119, turn-off KP Row2~4, CLK_OUT0~4 */ DRV_WriteReg32(0x800026E0, 0x0000); /* GPIO128~135, Keep I2C SCL2 ,turn-off others */ DRV_WriteReg32(0x80002700, 0x4000); /* GPIO136~143, Keep I2C SDA2 ,turn-off TRACE signal */ DRV_WriteReg32(0x80002710, 0x0001); #endif /* TV power down*/ DRV_ClrReg32(TVENC, 0x13E0); /* AFE power down*/ DRV_WriteReg32(PDN_AFE_AAPDN, 0); DRV_WriteReg32(PDN_AFE_AAC_NEW, 0); DRV_WriteReg32(PDN_AFE_AAC_CON1, 0x0003); /* MIPI power down*/ DRV_WriteReg32(MIPI_PD_B00, 0); DRV_WriteReg32(MIPI_PD_B04, 0); DRV_WriteReg32(MIPI_PD_B08, 0); DRV_WriteReg32(MIPI_PD_B0C, 0); DRV_WriteReg32(MIPI_PD_B10, 0); DRV_WriteReg32(MIPI_PD_B14, 0); DRV_WriteReg32(MIPI_PD_B18, 0); DRV_WriteReg32(MIPI_PD_B1C, 0); DRV_WriteReg32(MIPI_PD_B40, 0); DRV_WriteReg32(MIPI_PD_B44, 0); DRV_WriteReg32(MIPI_PD_B48, 0); DRV_WriteReg32(MIPI_PD_B4C, 0); DRV_WriteReg32(MIPI_PD_04C, 1); #if 1 /* MCU CG*/ DRV_SetReg32 (APMCUSYS_PDN_SET0, (1<<8)|(1<<9)|(1<<21)); /* MCU memory PDN*/ u4Val = 0; u4Val = ((1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)|(1<<10)| \ (1<<11)|(1<<12)|(1<<13)|(1<<16) ); DRV_SetReg32 (MCU_MEM_PDN, u4Val); #endif #if 1 /* GRAPH1SYS CG*/ DRV_SetReg32 (GRAPH1SYS_CG_SET, (1<<0)); /* GRAPH1SYS memory PDN*/ u4Val = 0; u4Val = ((1<<2)|(1<<3)|(1<<4)|(1<<6)|(1<<9)); DRV_SetReg32 (G1_MEM_PDN, u4Val); /* GRAPH2SYS CG */ DRV_SetReg32 (GRAPH2SYS_CG_SET, 0x1FF); /* GRAPH2SYS memory PDN*/ u4Val = 0; u4Val = ((1<<0)); DRV_SetReg32 (G2_MEM_PDN, u4Val); /* GRAPH2SYS MTCMOS */ DRV_SetReg16(ISO_EN, 1<<4); DRV_SetReg16(IN_ISO_EN, 1<<4 ); DRV_SetReg16(PWR_OFF, 1<<4 ); DRV_SetReg16(ACK_CLR, 0x2); #endif /* CEVA memory PDN*/ u4Val = 0; u4Val = ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)); DRV_SetReg32 (CEVA_MEM_PDN, u4Val); /* CEVA MTCMOS */ //printf("CEVA MTCMOS\n"); DRV_SetReg16(ISO_EN, 1<<5); DRV_SetReg16(IN_ISO_EN, 1<<5 ); DRV_SetReg16(PWR_OFF, 1<<5 ); DRV_SetReg16(ACK_CLR, 0x1); #if 1 /* Stop CEVA PLL*/ DRV_ClrReg32(CEVAPLL2,1<<0); #endif /* Stop UPLL*/ DRV_ClrReg32(PDN_CON,1<<4); /* Stop DPLL*/ #if 0 printf("DPLL Power Down\n"); DRV_ClrReg32(PDN_CON,1<<3); #endif #endif }
static void __gpt_clrcnt(struct gpt_device *dev) { DRV_SetReg32(dev->base_addr + GPT_CON, GPT_CON_CLRCNT); while (DRV_Reg32(dev->base_addr + GPT_CNT)) { } }
static void __gpt_enable_irq(struct gpt_device *dev) { DRV_SetReg32(GPT_IRQEN, 0x1 << (dev->id)); }
unsigned int hacc_init(AES_KEY_SEED *keyseed) { unsigned int i = 0; unsigned int *config; unsigned int ret = 0; hacc_deinit(); /* DRV_WriteReg32(HACC_SECINIT0, HACC_SECINIT0_MAGIC); */ /* DRV_WriteReg32(HACC_SECINIT1, HACC_SECINIT1_MAGIC); */ /* DRV_WriteReg32(HACC_SECINIT2, HACC_SECINIT2_MAGIC); */ /* clear aes module */ DRV_SetReg32(HACC_ACON2, HACC_AES_CLR); /* set aes module in cbc mode with no byte order change */ DRV_ClrReg32(HACC_ACON2, HACC_AES_CHG_BO_MASK | HACC_AES_MODE_MASK); DRV_SetReg32(HACC_ACON2, HACC_AES_CHG_BO_OFF | HACC_AES_CBC); /* aes secure initialiation */ memset(&hacc_ctx, 0, sizeof(struct hacc_context)); for (i = 0; i < keyseed->size; i++) hacc_ctx.sw_key[i] = keyseed->seed[i]; config = (unsigned int *)&hacc_ctx.cfg.config[0]; *config++ = HACC_CFG_0; *config++ = HACC_CFG_1; *config++ = HACC_CFG_2; *config = HACC_CFG_3; ret = hacc_set_cfg(&hacc_ctx.cfg); if (SEC_OK != ret) goto _end; ret = hacc_set_mode(AES_CBC_MODE); if (SEC_OK != ret) goto _end; /* derive the hardware wrapper key */ ret = hacc_set_key(AES_HW_KEY, HACC_HW_KEY_SZ); if (SEC_OK != ret) goto _end; ret = hacc_do_aes(AES_ENC, &hacc_ctx.sw_key[0], &hacc_ctx.hw_key[0], AES_KEY_256); if (SEC_OK != ret) goto _end; ret = hacc_set_key(AES_HW_WRAP_KEY, AES_KEY_256); if (SEC_OK != ret) goto _end; hacc_test(); /* from now on, HACC HW wrap key can be used */ bHACC_HWWrapKeyInit = 1; /* from now on, HACC SW key can be used */ bHACC_SWKeyInit = 1; _end: return ret; }
void sc_dpidle_after_wfi(void) { #ifdef PROFILE_DPIDLE dpidle_tick_pos = GPT_GetCounter(GPT2); dpidle_wakeup_src = DRV_Reg32(SC_WAKEUP_SRC); if (dpidle_debug_mask & DEBUG_PROFILE) { #ifdef CONFIG_LOCAL_TIMERS dcm_info("[%s]%5d %10u %10u %10u %10u %08x\n", __func__, dpidle_profile_idx, dpidle_tick_pre, dpidle_tick_mid, dpidle_tick_pos, dpidle_counter, dpidle_wakeup_src); #else dcm_info("[%s]%5d %10u %10u %10u %10u %10u %10u %08x\n", __func__, dpidle_profile_idx, dpidle_tick_pre, dpidle_tick_mid, dpidle_tick_pos, dpidle_counter, dpidle_compare, dpidle_compare_update, dpidle_wakeup_src); #endif dpidle_profile_idx++; } #endif #ifdef CONFIG_LOCAL_WDT wdt_tick_pos = GPT_GetCounter(GPT2); if (wdt_counter_pre > (wdt_tick_pos - wdt_tick_pre)) { wdt_counter_pos = wdt_counter_pre - (wdt_tick_pos - wdt_tick_pre); mpcore_wdt_set_counter(wdt_counter_pos); } else { dcm_info("[%s]:wdt_counter_pre=%10lu, wdt_tick_pre=%10lu, wdt_tick_pos=%10lu\n", __func__, wdt_counter_pre, wdt_tick_pre, wdt_tick_pos); mpcore_wdt_set_counter(1); } #endif #ifdef CONFIG_LOCAL_TIMERS if (GPT_Get_IRQ(WAKEUP_GPT)) { /* waked up by WAKEUP_GPT */ localtimer_set_next_event(1); } else { /* waked up by other wakeup source */ unsigned int temp1 = GPT_GetCompare(WAKEUP_GPT); unsigned int temp2 = GPT_GetCounter(WAKEUP_GPT); if (unlikely(temp1 <= temp2)) { dcm_err("[%s]GPT%d: counter = %10u, compare = %10u\n", __func__, temp1, temp2); BUG(); } localtimer_set_next_event(temp1-temp2); GPT_Stop(WAKEUP_GPT); GPT_ClearCount(WAKEUP_GPT); } #endif if (get_chip_eco_ver() == CHIP_E1) { DRV_SetReg32(WPLL_CON0, 0x1); } else { if (mmsys_switched_off) { DRV_ClrReg16(MDPLL_CON0, 0x1); udelay(20); mm_clk_sq2pll(); mmsys_switched_off = 0; } } #if 0 /* restore TOP_MISC */ DRV_WriteReg32(TOP_MISC, topmisc); #endif dpidle_count++; if ((dpidle_debug_mask & DEBUG_TRACING)) { dpidle_single_count++; } }
void Uboot_power_saving(void) { #if 0 u32 u4Val = 0; #if 0 printf("GPIO Set\n"); /* GPIO48~55, turn-off PWM 0~1 */ DRV_WriteReg32(0x80002660, 0x0555); /* GPIO56~63, turn-off EINT 0~4 */ DRV_WriteReg32(0x80002670, 0x0015); /* GPIO64~71, turn-off EINT 5~7, UART4 CTS/RTS */ DRV_WriteReg32(0x80002680, 0x1400); /* GPIO112~119, turn-off KP Row2~4, CLK_OUT0~4 */ DRV_WriteReg32(0x800026E0, 0x0000); /* GPIO128~135, Keep I2C SCL2 ,turn-off others */ DRV_WriteReg32(0x80002700, 0x4000); /* GPIO136~143, Keep I2C SDA2 ,turn-off TRACE signal */ DRV_WriteReg32(0x80002710, 0x0001); #endif /* TV power down*/ DRV_ClrReg32(TVENC, 0x13E0); /* AFE power down*/ DRV_WriteReg32(PDN_AFE_AAPDN, 0); DRV_WriteReg32(PDN_AFE_AAC_NEW, 0); DRV_WriteReg32(PDN_AFE_AAC_CON1, 0x0003); /* MIPI power down Jett: Don't power down MIPI during uboot, or the DPI signal would be turned off and the uboot logo is disappeared */ #if 0 PW_DEBUG("MIPI power down\n"); DRV_WriteReg32(MIPI_PD_B00, 0); DRV_WriteReg32(MIPI_PD_B04, 0); DRV_WriteReg32(MIPI_PD_B08, 0); DRV_WriteReg32(MIPI_PD_B0C, 0); DRV_WriteReg32(MIPI_PD_B10, 0); DRV_WriteReg32(MIPI_PD_B14, 0); DRV_WriteReg32(MIPI_PD_B18, 0); DRV_WriteReg32(MIPI_PD_B1C, 0); DRV_WriteReg32(MIPI_PD_B40, 0); DRV_WriteReg32(MIPI_PD_B44, 0); DRV_WriteReg32(MIPI_PD_B48, 0); DRV_WriteReg32(MIPI_PD_B4C, 0); DRV_WriteReg32(MIPI_PD_04C, 1); #endif /* MCU CG*/ DRV_SetReg32 (APMCUSYS_PDN_SET0, (1<<8)|(1<<9)|(1<<21)); /* MCU memory PDN*/ u4Val = 0; u4Val = ((1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)|(1<<10)| \ (1<<11)|(1<<12)|(1<<13)|(1<<16) ); DRV_SetReg32 (MCU_MEM_PDN, u4Val); /* GRAPH1SYS CG*/ DRV_SetReg32 (GRAPH1SYS_CG_SET, (1<<0)); /* GRAPH1SYS memory PDN*/ u4Val = 0; u4Val = ((1<<2)|(1<<3)|(1<<4)|(1<<6)|(1<<9)); DRV_SetReg32 (G1_MEM_PDN, u4Val); /* GRAPH2SYS CG */ DRV_SetReg32 (GRAPH2SYS_CG_SET, 0x1FF); /* GRAPH2SYS memory PDN*/ u4Val = 0; u4Val = ((1<<0)); DRV_SetReg32 (G2_MEM_PDN, u4Val); /* GRAPH2SYS MTCMOS */ DRV_SetReg16(ISO_EN, 1<<4); DRV_SetReg16(IN_ISO_EN, 1<<4 ); DRV_SetReg16(PWR_OFF, 1<<4 ); DRV_SetReg16(ACK_CLR, 0x2); /* CEVA memory PDN*/ u4Val = 0; u4Val = ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)); DRV_SetReg32 (CEVA_MEM_PDN, u4Val); /* CEVA MTCMOS */ DRV_SetReg16(ISO_EN, 1<<5); DRV_SetReg16(IN_ISO_EN, 1<<5 ); DRV_SetReg16(PWR_OFF, 1<<5 ); DRV_SetReg16(ACK_CLR, 0x1); /* Stop CEVA PLL*/ DRV_ClrReg32(CEVAPLL2,1<<0); /* Stop UPLL*/ DRV_ClrReg32(PDN_CON,1<<4); /* Stop DPLL*/ #if 0 printf("DPLL Power Down\n"); DRV_ClrReg32(PDN_CON,1<<3); #endif /* Stop VUSB */ //pmic_config_interface(0x3D, KAL_FALSE, VUSB_EN_MASK, VUSB_EN_SHIFT); //pmic_vsdio_enable(KAL_TRUE); #endif }