DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, smode), DSI_DLY_MS(20), DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_NO_OP, 0x0), DSI_DLY_MS(20), #endif #if DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_TEARING_EFFECT_ON, 0x0), DSI_DLY_MS(20), #endif DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0), DSI_DLY_MS(120), DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0), DSI_DLY_MS(20), DSI_SEND_FRAME(1), DSI_DLY_MS(120), }; static struct tegra_dsi_cmd dsi_s_wqxga_10_1_suspend_cmd[] = { DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_OFF, 0x0), DSI_DLY_MS(50), DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_ENTER_SLEEP_MODE, 0x0), DSI_DLY_MS(200), #if DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_TEARING_EFFECT_OFF, 0x0), DSI_DLY_MS(20), #endif };
err = gpio_request(DSI_PANEL_EN_GPIO, "panel en"); if (err < 0) { pr_err("panel en gpio request failed\n"); goto fail; } gpio_requested = true; return 0; fail: return err; } static struct tegra_dsi_cmd dsi_j_1440_810_5_8_init_cmd[] = { /* panel exit_sleep_mode sequence */ DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0), DSI_SEND_FRAME(5), DSI_DLY_MS(20), /* panel set_display_on sequence */ DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0), DSI_DLY_MS(20), }; static struct tegra_dsi_cmd dsi_j_1440_810_5_8_suspend_cmd[] = { /* panel set_display_off sequence */ DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_OFF, 0x0), /* panel enter_sleep_mode sequence*/ DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_ENTER_SLEEP_MODE, 0x0), DSI_DLY_MS(80), };
static u8 panel_internal[] = {0x51, 0x0f, 0xff}; static struct tegra_dsi_cmd dsi_s_1080p_5_init_cmd[] = { DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xb0, 0x04), DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_NO_OP, 0x0), DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_NO_OP, 0x0), DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xd6, 0x01), DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_internal), DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0x53, 0x04), DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0), DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0), DSI_DLY_MS(10), DSI_SEND_FRAME(7), }; static struct tegra_dsi_cmd dsi_s_1080p_5_suspend_cmd[] = { DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_OFF, 0x0), DSI_DLY_MS(50), DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_ENTER_SLEEP_MODE, 0x0), DSI_DLY_MS(10), }; static struct tegra_dsi_out dsi_s_1080p_5_pdata = { .n_data_lanes = 4, .refresh_rate = 60, .video_data_type = TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE, .video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS,
}; static struct tegra_dsi_cmd dsi_j_qxga_8_9_init_cmd[] = { DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0, CMD_NOT_CLUBBED), DSI_DLY_MS(120), DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x53, 0x24, CMD_CLUBBED), DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x55, 0x00, CMD_CLUBBED), DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x35, 0x00, CMD_CLUBBED), DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0, CMD_CLUBBED), }; static struct tegra_dsi_cmd dsi_j_qxga_8_9_suspend_cmd[] = { DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_1_PARAM, 0x51, 0x00, CMD_CLUBBED), DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_OFF, 0x0, CMD_CLUBBED), DSI_CMD_VBLANK_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_ENTER_SLEEP_MODE, 0x0, CMD_CLUBBED), DSI_SEND_FRAME(3), DSI_CMD_VBLANK_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xB0, 0x04, CMD_CLUBBED), DSI_CMD_VBLANK_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xB1, 0x01, CMD_CLUBBED), }; static struct tegra_dsi_out dsi_j_qxga_8_9_pdata = { .controller_vs = DSI_VS_1, .n_data_lanes = 8, #if DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE .video_data_type = TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE, .ganged_type = TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT, .suspend_aggr = DSI_HOST_SUSPEND_LV2, .refresh_rate = 61, .rated_refresh_rate = 60,