static int32_t spi_master_transfer_asynch(spi_t *obj)
{
dspi_transfer_t masterXfer;
int32_t status;
uint32_t transferSize;
/*Start master transfer*/
masterXfer.txData = obj->tx_buff.buffer;
masterXfer.rxData = obj->rx_buff.buffer;
masterXfer.dataSize = obj->tx_buff.length;
masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
/* Busy transferring */
obj->spi.status = kDSPI_Busy;
if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED ||
obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
status = DSPI_MasterTransferEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, &masterXfer);
if (status == kStatus_DSPI_OutOfRange) {
if (obj->spi.bits > 8) {
transferSize = 1022;
} else {
transferSize = 511;
}
masterXfer.dataSize = transferSize;
/* Save amount of TX done by DMA */
obj->tx_buff.pos += transferSize;
obj->rx_buff.pos += transferSize;
/* Try again */
status = DSPI_MasterTransferEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, &masterXfer);
}
} else {
status = DSPI_MasterTransferNonBlocking(spi_address[obj->spi.instance], &obj->spi.spi_master_handle, &masterXfer);
}
return status;
}
uint32_t spi_irq_handler_asynch(spi_t *obj)
{
uint32_t transferSize;
dspi_transfer_t masterXfer;
/* Determine whether the current scenario is DMA or IRQ, and act accordingly */
if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
/* DMA implementation */
/* Check If there is still data in the TX buffer */
if (obj->tx_buff.pos < obj->tx_buff.length) {
/* Setup a new DMA transfer. */
if (obj->spi.bits > 8) {
transferSize = 1022;
} else {
transferSize = 511;
}
/* Update the TX buffer only if it is used */
if (obj->tx_buff.buffer) {
masterXfer.txData = ((uint8_t *)obj->tx_buff.buffer) + obj->tx_buff.pos;
} else {
masterXfer.txData = 0;
}
/* Update the RX buffer only if it is used */
if (obj->rx_buff.buffer) {
masterXfer.rxData = ((uint8_t *)obj->rx_buff.buffer) + obj->rx_buff.pos;
} else {
masterXfer.rxData = 0;
}
/* Check how much data is remaining in the buffer */
if ((obj->tx_buff.length - obj->tx_buff.pos) > transferSize) {
masterXfer.dataSize = transferSize;
} else {
masterXfer.dataSize = obj->tx_buff.length - obj->tx_buff.pos;
}
masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
/* Save amount of TX done by DMA */
obj->tx_buff.pos += masterXfer.dataSize;
obj->rx_buff.pos += masterXfer.dataSize;
/* Start another transfer */
DSPI_MasterTransferEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, &masterXfer);
return 0;
} else {
/* Release the dma channels if they were opportunistically allocated */
if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) {
dma_channel_free(obj->spi.spiDmaMasterRx.dmaChannel);
dma_channel_free(obj->spi.spiDmaMasterTx.dmaChannel);
dma_channel_free(obj->spi.spiDmaMasterIntermediary.dmaChannel);
obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;
}
obj->spi.status = kDSPI_Idle;
return SPI_EVENT_COMPLETE;
}
} else {
/* Interrupt implementation */
obj->spi.status = kDSPI_Idle;
return SPI_EVENT_COMPLETE;
}
}
/*!
* @brief Main function
*/
int main(void)
{
BOARD_InitPins();
BOARD_BootClockRUN();
BOARD_InitDebugConsole();
PRINTF("DSPI edma example start.\r\n");
PRINTF("This example use one dspi instance as master and another as slave on one board.\r\n");
PRINTF("Master use edma way , slave uses interrupt.\r\n");
PRINTF("Please make sure you make the correct line connection. Basically, the connection is: \r\n");
PRINTF("DSPI_master -- DSPI_slave \r\n");
PRINTF(" CLK -- CLK \r\n");
PRINTF(" PCS -- PCS \r\n");
PRINTF(" SOUT -- SIN \r\n");
PRINTF(" SIN -- SOUT \r\n");
/* DMA Mux setting and EDMA init */
uint32_t masterRxChannel, masterIntermediaryChannel, masterTxChannel;
uint32_t slaveRxChannel, slaveTxChannel;
edma_config_t userConfig;
masterRxChannel = 0U;
masterIntermediaryChannel = 1U;
masterTxChannel = 2U;
slaveRxChannel = 3U;
slaveTxChannel = 4U;
/* DMA MUX init */
DMAMUX_Init(EXAMPLE_DSPI_MASTER_DMA_MUX_BASEADDR);
#if (defined EXAMPLE_DSPI_MASTER_DMA_MUX_BASE) && (defined EXAMPLE_DSPI_SLAVE_DMA_MUX_BASE) && \
(EXAMPLE_DSPI_MASTER_DMA_MUX_BASE != EXAMPLE_DSPI_SLAVE_DMA_MUX_BASE)
DMAMUX_Init(EXAMPLE_DSPI_SLAVE_DMA_MUX_BASEADDR);
#endif
DMAMUX_SetSource(EXAMPLE_DSPI_MASTER_DMA_MUX_BASEADDR, masterRxChannel, EXAMPLE_DSPI_MASTER_DMA_RX_REQUEST_SOURCE);
DMAMUX_EnableChannel(EXAMPLE_DSPI_MASTER_DMA_MUX_BASEADDR, masterRxChannel);
#if (defined EXAMPLE_DSPI_MASTER_DMA_TX_REQUEST_SOURCE)
DMAMUX_SetSource(EXAMPLE_DSPI_MASTER_DMA_MUX_BASEADDR, masterTxChannel, EXAMPLE_DSPI_MASTER_DMA_TX_REQUEST_SOURCE);
DMAMUX_EnableChannel(EXAMPLE_DSPI_MASTER_DMA_MUX_BASEADDR, masterTxChannel);
#endif
DMAMUX_SetSource(EXAMPLE_DSPI_SLAVE_DMA_MUX_BASEADDR, slaveRxChannel, EXAMPLE_DSPI_SLAVE_DMA_RX_REQUEST_SOURCE);
DMAMUX_EnableChannel(EXAMPLE_DSPI_SLAVE_DMA_MUX_BASEADDR, slaveRxChannel);
#if (defined EXAMPLE_DSPI_SLAVE_DMA_TX_REQUEST_SOURCE)
DMAMUX_SetSource(EXAMPLE_DSPI_SLAVE_DMA_MUX_BASEADDR, slaveTxChannel, EXAMPLE_DSPI_SLAVE_DMA_TX_REQUEST_SOURCE);
DMAMUX_EnableChannel(EXAMPLE_DSPI_SLAVE_DMA_MUX_BASEADDR, slaveTxChannel);
#endif
/* EDMA init*/
/*
* userConfig.enableRoundRobinArbitration = false;
* userConfig.enableHaltOnError = true;
* userConfig.enableContinuousLinkMode = false;
* userConfig.enableDebugMode = false;
*/
EDMA_GetDefaultConfig(&userConfig);
EDMA_Init(EXAMPLE_DSPI_MASTER_DMA_BASEADDR, &userConfig);
#if (defined EXAMPLE_DSPI_SLAVE_DMA_BASE) && (defined EXAMPLE_DSPI_MASTER_DMA_BASE) && \
(EXAMPLE_DSPI_SLAVE_DMA_BASE != EXAMPLE_DSPI_MASTER_DMA_BASE)
EDMA_Init(EXAMPLE_DSPI_SLAVE_DMA_BASEADDR, &userConfig);
#endif
/*DSPI init*/
uint32_t srcClock_Hz;
uint32_t errorCount;
uint32_t i;
dspi_master_config_t masterConfig;
dspi_slave_config_t slaveConfig;
dspi_transfer_t masterXfer;
dspi_transfer_t slaveXfer;
/*Master config*/
masterConfig.whichCtar = kDSPI_Ctar0;
masterConfig.ctarConfig.baudRate = TRANSFER_BAUDRATE;
masterConfig.ctarConfig.bitsPerFrame = 8U;
masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
masterConfig.ctarConfig.direction = kDSPI_MsbFirst;
masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / TRANSFER_BAUDRATE;
masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / TRANSFER_BAUDRATE;
masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / TRANSFER_BAUDRATE;
masterConfig.whichPcs = EXAMPLE_DSPI_MASTER_PCS_FOR_INIT;
masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow;
masterConfig.enableContinuousSCK = false;
masterConfig.enableRxFifoOverWrite = false;
masterConfig.enableModifiedTimingFormat = false;
masterConfig.samplePoint = kDSPI_SckToSin0Clock;
srcClock_Hz = CLOCK_GetFreq(DSPI_MASTER_CLK_SRC);
DSPI_MasterInit(EXAMPLE_DSPI_MASTER_BASEADDR, &masterConfig, srcClock_Hz);
/*Slave config*/
slaveConfig.whichCtar = kDSPI_Ctar0;
slaveConfig.ctarConfig.bitsPerFrame = masterConfig.ctarConfig.bitsPerFrame;
slaveConfig.ctarConfig.cpol = masterConfig.ctarConfig.cpol;
slaveConfig.ctarConfig.cpha = masterConfig.ctarConfig.cpha;
slaveConfig.enableContinuousSCK = masterConfig.enableContinuousSCK;
slaveConfig.enableRxFifoOverWrite = masterConfig.enableRxFifoOverWrite;
slaveConfig.enableModifiedTimingFormat = masterConfig.enableModifiedTimingFormat;
slaveConfig.samplePoint = masterConfig.samplePoint;
DSPI_SlaveInit(EXAMPLE_DSPI_SLAVE_BASEADDR, &slaveConfig);
/* Set up the transfer data */
for (i = 0U; i < TRANSFER_SIZE; i++)
{
masterTxData[i] = i % 256U;
masterRxData[i] = 0U;
slaveTxData[i] = ~masterTxData[i];
slaveRxData[i] = 0U;
}
/* Set up dspi slave first */
memset(&(dspiEdmaSlaveRxRegToRxDataHandle), 0, sizeof(dspiEdmaSlaveRxRegToRxDataHandle));
memset(&(dspiEdmaSlaveTxDataToTxRegHandle), 0, sizeof(dspiEdmaSlaveTxDataToTxRegHandle));
EDMA_CreateHandle(&(dspiEdmaSlaveRxRegToRxDataHandle), EXAMPLE_DSPI_SLAVE_DMA_BASEADDR, slaveRxChannel);
EDMA_CreateHandle(&(dspiEdmaSlaveTxDataToTxRegHandle), EXAMPLE_DSPI_SLAVE_DMA_BASEADDR, slaveTxChannel);
isTransferCompleted = false;
DSPI_SlaveTransferCreateHandleEDMA(EXAMPLE_DSPI_SLAVE_BASEADDR, &g_dspi_edma_s_handle, DSPI_SlaveUserCallback, NULL,
&dspiEdmaSlaveRxRegToRxDataHandle, &dspiEdmaSlaveTxDataToTxRegHandle);
slaveXfer.txData = slaveTxData;
slaveXfer.rxData = slaveRxData;
slaveXfer.dataSize = TRANSFER_SIZE;
slaveXfer.configFlags = kDSPI_SlaveCtar0;
if (kStatus_Success != DSPI_SlaveTransferEDMA(EXAMPLE_DSPI_SLAVE_BASEADDR, &g_dspi_edma_s_handle, &slaveXfer))
{
PRINTF("There is error when start DSPI_SlaveTransferEDMA \r\n");
}
/* Set up dspi master */
memset(&(dspiEdmaMasterRxRegToRxDataHandle), 0, sizeof(dspiEdmaMasterRxRegToRxDataHandle));
memset(&(dspiEdmaMasterTxDataToIntermediaryHandle), 0, sizeof(dspiEdmaMasterTxDataToIntermediaryHandle));
memset(&(dspiEdmaMasterIntermediaryToTxRegHandle), 0, sizeof(dspiEdmaMasterIntermediaryToTxRegHandle));
EDMA_CreateHandle(&(dspiEdmaMasterRxRegToRxDataHandle), EXAMPLE_DSPI_MASTER_DMA_BASEADDR, masterRxChannel);
EDMA_CreateHandle(&(dspiEdmaMasterTxDataToIntermediaryHandle), EXAMPLE_DSPI_MASTER_DMA_BASEADDR,
masterIntermediaryChannel);
EDMA_CreateHandle(&(dspiEdmaMasterIntermediaryToTxRegHandle), EXAMPLE_DSPI_MASTER_DMA_BASEADDR, masterTxChannel);
DSPI_MasterTransferCreateHandleEDMA(EXAMPLE_DSPI_MASTER_BASEADDR, &g_dspi_edma_m_handle, DSPI_MasterUserCallback,
NULL, &dspiEdmaMasterRxRegToRxDataHandle,
&dspiEdmaMasterTxDataToIntermediaryHandle,
&dspiEdmaMasterIntermediaryToTxRegHandle);
/* Start master transfer */
masterXfer.txData = masterTxData;
masterXfer.rxData = masterRxData;
masterXfer.dataSize = TRANSFER_SIZE;
masterXfer.configFlags = kDSPI_MasterCtar0 | EXAMPLE_DSPI_MASTER_PCS_FOR_TRANSFER | kDSPI_MasterPcsContinuous;
if (kStatus_Success != DSPI_MasterTransferEDMA(EXAMPLE_DSPI_MASTER_BASEADDR, &g_dspi_edma_m_handle, &masterXfer))
{
PRINTF("There is error when start DSPI_MasterTransferEDMA \r\n ");
}
/* Wait until transfer completed */
while (!isTransferCompleted)
{
}
/* Check the data */
errorCount = 0U;
for (i = 0U; i < TRANSFER_SIZE; i++)
{
if (masterTxData[i] != slaveRxData[i])
{
errorCount++;
}
if (slaveTxData[i] != masterRxData[i])
{
errorCount++;
}
}
if (errorCount == 0)
{
PRINTF("DSPI transfer all data matched! \r\n");
}
else
{
PRINTF("Error occured in DSPI transfer ! \r\n");
}
DSPI_Deinit(EXAMPLE_DSPI_MASTER_BASEADDR);
DSPI_Deinit(EXAMPLE_DSPI_SLAVE_BASEADDR);
while (1)
{
}
}
