static inline size_t dwmac_desc_enh_get_rx_frame_len(
dwmac_common_context *self,
const unsigned int desc_idx )
{
volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) self->dma_rx;
/* The type-1 checksum offload engines append the checksum at
* the end of frame and the two bytes of checksum are added in
* the length.
* Adjust for that in the framelen for type-1 checksum offload
* engines. */
if ( self->dmagrp->hw_feature & DMAGRP_HW_FEATURE_RXTYP1COE ) {
return DWMAC_DESC_ERX_DES0_FRAME_LENGTH_GET( p_enh[desc_idx].erx.des0_3.des0 )
- 2U;
} else {
return DWMAC_DESC_ERX_DES0_FRAME_LENGTH_GET( p_enh[desc_idx].erx.des0_3.des0 );
}
}
static void dwmac_desc_enh_print_rx_desc(
volatile dwmac_desc *p,
const unsigned int count )
{
volatile dwmac_desc_ext *p_enh = (volatile dwmac_desc_ext *) p;
unsigned int index;
if ( p_enh != NULL ) {
for ( index = 0; index < count; ++index ) {
printf( "Receive DMA Descriptor %d\n", index );
printf( "des0\n" );
printf(
" %u Own Bit\n"
" %u Dest. Addr. Filter Fail\n"
" %lu Frame Length\n"
" %u Source Addr. Filter Fail\n"
" %u Length Error\n"
" %u VLAN Tag\n"
" %u First Descriptor\n"
" %u Last Descriptor\n"
" %u Frame Type\n"
" %u Dribble Bit Error\n"
" %u Extended Status Available\n",
( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_OWN_BIT ) != 0,
( p_enh[index].erx.des0_3.des0
& DWMAC_DESC_ERX_DES0_DEST_ADDR_FILTER_FAIL ) != 0,
DWMAC_DESC_ERX_DES0_FRAME_LENGTH_GET(
p_enh[index].erx.des0_3.des0 ),
( p_enh[index].erx.des0_3.des0
& DWMAC_DESC_ERX_DES0_SRC_ADDR_FILTER_FAIL ) != 0,
( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_LENGTH_ERROR ) != 0,
( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_VLAN_TAG ) != 0,
( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_FIRST_DESCRIPTOR ) != 0,
( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_LAST_DESCRIPTOR ) != 0,
( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_FREAME_TYPE ) != 0,
( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_DRIBBLE_BIT_ERROR ) != 0,
( p_enh[index].erx.des0_3.des0
& DWMAC_DESC_ERX_DES0_EXT_STATUS_AVAIL_OR_RX_MAC_ADDR_STATUS ) != 0
);
if ( ( p_enh[index].erx.des0_3.des0
& DWMAC_DESC_ERX_DES0_ERROR_SUMMARY ) != 0 ) {
printf( " Error Summary:\n" );
if ( ( p_enh[index].erx.des0_3.des0
& DWMAC_DESC_ERX_DES0_DESCRIPTOR_ERROR ) != 0 ) {
printf( " Descriptor Error\n" );
}
if ( ( p_enh[index].erx.des0_3.des0
& DWMAC_DESC_ERX_DES0_OVERFLOW_ERROR ) != 0 ) {
printf( " Overflow Error\n" );
}
if ( ( p_enh[index].erx.des0_3.des0
&
DWMAC_DESC_ERX_DES0_TIMESTAMP_AVAIL_OR_CHECKSUM_ERROR_OR_GIANT_FRAME )
!= 0 ) {
printf( " Giant Frame\n" );
}
if ( ( p_enh[index].erx.des0_3.des0
& DWMAC_DESC_ERX_DES0_LATE_COLLISION ) != 0 ) {
printf( " Late Collision\n" );
}
if ( ( p_enh[index].erx.des0_3.des0
& DWMAC_DESC_ERX_DES0_RECEIVE_WATCHDOG_TIMEOUT ) != 0
|| ( p_enh[index].erx.des0_3.des0
& DWMAC_DESC_ERX_DES0_RECEIVE_ERROR ) != 0 ) {
printf( " IP Header or IP Payload:\n" );
if ( ( p_enh[index].erx.des0_3.des0
& DWMAC_DESC_ERX_DES0_RECEIVE_WATCHDOG_TIMEOUT ) != 0 ) {
printf( " Watchdog Timeout\n" );
}
if ( ( p_enh[index].erx.des0_3.des0
& DWMAC_DESC_ERX_DES0_RECEIVE_ERROR ) != 0 ) {
printf( " Receive Error\n" );
}
}
if ( ( p_enh[index].erx.des0_3.des0 & DWMAC_DESC_ERX_DES0_CRC_ERROR )
!= 0 ) {
printf( " CRC Error\n" );
}
}
printf( "des1\n" );
printf(
" %u Disable Interrupt on Completion\n"
" %lu Receive Buffer 2 Size\n"
" %u Receive End of Ring\n"
" %u Second Addr. Chained\n"
" %lu Receive Buffer 1 Size\n",
( p_enh[index].erx.des0_3.des1
& DWMAC_DESC_ERX_DES1_DISABLE_IRQ_ON_COMPLETION ) != 0,
DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE_GET( p_enh[index].erx.des0_3.
des1 ),
( p_enh[index].erx.des0_3.des1 & DWMAC_DESC_ERX_DES1_RECEIVE_END_OF_RING ) != 0,
( p_enh[index].erx.des0_3.des1 & DWMAC_DESC_ERX_DES1_SECOND_ADDR_CHAINED ) != 0,
DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_GET( p_enh[index].erx.des0_3.
des1 )
);
printf( "des2\n" );
printf( " %p Buffer 1 Address\n", (void *) p_enh[index].erx.des0_3.des2 );
printf( "des3\n" );
printf( " %p Buffer 2 Address\n", (void *) p_enh[index].erx.des0_3.des3 );
}
}
}
