void InitSysCtrl(void)
{
// Disable the watchdog
DisableDog();
// *IMPORTANT*
// The Device_cal function, which copies the ADC & oscillator calibration values
// from TI reserved OTP into the appropriate trim registers, occurs automatically
// in the Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC and oscillators to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // Enable ADC peripheral clock
(*Device_cal)();
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0; // Return ADC clock to original state
EDIS;
// Select Internal Oscillator 1 as Clock Source (default), and turn off all unused clocks to
// conserve power.
IntOsc1Sel();
// Initialize the PLL control: PLLCR and DIVSEL
// DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2802x_Examples.h
InitPll(DSP28_PLLCR,DSP28_DIVSEL);
// Initialize the peripheral clocks
InitPeripheralClocks();
}
void InitPll2(Uint16 clksrc, Uint16 pllmult, Uint16 clkdiv)
{
EALLOW;
// Check if SYSCLK2DIV2DIS is in /2 mode
if(DevEmuRegs.DEVICECNF.bit.SYSCLK2DIV2DIS != 0)
{
DevEmuRegs.DEVICECNF.bit.SYSCLK2DIV2DIS = 0;
}
// Enable PLL2
SysCtrlRegs.PLL2CTL.bit.PLL2EN = 1;
// Select clock source for PLL2
SysCtrlRegs.PLL2CTL.bit.PLL2CLKSRCSEL = clksrc;
// Set PLL2 Multiplier
SysCtrlRegs.PLL2MULT.bit.PLL2MULT = pllmult;
// Wait for PLL to lock.
// Uncomment to disable the watchdog
DisableDog();
while(SysCtrlRegs.PLL2STS.bit.PLL2LOCKS!= 1)
{
// Uncomment to service the watchdog
// ServiceDog();
}
// Set System Clock 2 divider
DevEmuRegs.DEVICECNF.bit.SYSCLK2DIV2DIS = clkdiv;
EDIS;
}
void InitSysCtrl(void)
{
// Disable the watchdog
DisableDog();
// Initialize the PLLCR
InitPll(DSP28_PLLCR);
// Initialize the peripheral clocks
InitPeripheralClocks();
}
int main(void){
DisableDog();
EALLOW;
int test = 0;
int laggingValue = 0xFF;
unsigned int value = 0;
EALLOW;
CPUinit();
EALLOW;
DINT;
outputEnable();
initADC();
EALLOW;
outputEnable(); //having issues when not enabling twice
SRAMwrite(0);
SRAMaddress = 0x260000;
//DAC_init();
DAC_init();
timerINIT();
EALLOW;
int oldvalue = 0;
while(1){
// SRAMaddress = 0x2FFFFF;
// *SRAMaddress = 0x77;
if(a == 1){ //cross your fingers folks
value = keypadScan();
*outputPORT = value;
if(value < 0xF && value != 1 && oldvalue != value){
FreqSet(value); //setting the frequency based upon keypad input
oldvalue = value;
}
}
}
EALLOW;
return 0;
}
void InitSysCtrl(void)
{
// Disable the watchdog
DisableDog();
// Initialize the PLL control: PLLCR and DIVSEL
// DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
InitPll(DSP28_PLLCR,DSP28_DIVSEL);
// Initialize the peripheral clocks
InitPeripheralClocks();
}
int main(void) {
DisableDog();
CPUinit();
EALLOW;
outputEnable();
LCDinit();
LCDclear();
initADC();
DAC_init();
// SRAMwrite(0);
// SRAMaddress = 0x260000; //shouldn't need SRAM here
fft_init();
initBuffers();
timerINIT(ISRvalue, samplingRate);
while(1){
if(sampleBufferFull){
fft.InBuf = &sampleBuffer[0];
int i;
for(i = 0;i<FFT_SIZE;i++){
outBuffer[i] = 0;
}
for(i=0;i<FFT_SIZE/2;i++){
MagBuffer[i] = 0;
}
RFFT_f32(&fft);
//fft.MagBuf = &sampleBuffer[0];
RFFT_f32_mag(&fft);
sampleBufferFull = 0;
EINT;
}
else{
//do nothing
}
}
return 0;
}
void init_board ()
{
DisableDog();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;/* Enable ADC peripheral clock*/
(*Device_cal)();
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0;/* Return ADC clock to original state*/
EDIS;
/* Select Internal Oscillator 1 as Clock Source (default), and turn off all unused clocks to
* conserve power.
*/
IntOsc1Sel();
/* Initialize the PLL control: PLLCR and DIVSEL
* DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2806x_Examples.h
*/
InitPll(9,3);
InitPeripheralClocks();
EALLOW;
/* Configure low speed peripheral clocks */
SysCtrlRegs.LOSPCP.all = 0U;
EDIS;
/* Disable and clear all CPU interrupts */
DINT;
IER = 0x0000;
IFR = 0x0000;
InitPieCtrl();
InitPieVectTable();
InitCpuTimers();
/* initial ePWM GPIO assignment... */
config_ePWM_GPIO();
/* initial GPIO qualification settings.... */
EALLOW;
GpioCtrlRegs.GPAQSEL1.all = 0x0;
GpioCtrlRegs.GPAQSEL2.all = 0x0;
GpioCtrlRegs.GPBQSEL1.all = 0x0;
GpioCtrlRegs.GPBQSEL2.all = 0x0;
EDIS;
}
void InitPll(Uint16 val)
{
volatile Uint16 iVol;
if (SysCtrlRegs.PLLCR.bit.DIV != val)
{
EALLOW;
SysCtrlRegs.PLLCR.bit.DIV = val;
EDIS;
// Optional: Wait for PLL to lock.
// During this time the CPU will switch to OSCCLK/2 until the PLL is
// stable. Once the PLL is stable the CPU will switch to the new PLL value.
//
// This switch time is 131072 CLKIN cycles as of Rev C silicon.
//
// Code is not required to sit and wait for the PLL to lock.
// However, if the code does anything that is timing critical,
// and requires the correct clock be locked, then it is best to
// wait until this switching has completed.
// If this function is run from waitstated memory, then the loop count can
// be reduced as long as the minimum switch time is still met.
// iVol is volatile so the compiler will not optimize this loop out
//
// The watchdog should be disabled before this loop, or fed within
// the loop.
DisableDog();
// Wait lock cycles.
// Note, This loop is tuned to 0-waitstate RAM memory. If this
// function is run from wait-stated memory such as Flash or XINTF,
// then the number of times through the loop can be reduced
// accordingly.
for(iVol= 0; iVol< ( (131072/2)/12 ); iVol++)
{
}
}
}
int main(void) {
DisableDog();
CPUinit();
EALLOW;
outputEnable();
LCDinit();
LCDclear();
initADC();
DAC_init();
init_buffer();
timerINIT(ISRvalue, samplingRate);
while(1){
}
return 0;
}
void InitPll(u_int16 pllcr)
{
volatile u_int16 i;
if (SYS_CTRL_REGS.PLLCR.bits.DIV != pllcr) {
EALLOW;
SYS_CTRL_REGS.PLLCR.bits.DIV = pllcr;
EDIS;
//-----------------------------------------------------------------------
// Ожидание установки нового PLL.
//-----------------------------------------------------------------------
// На период установки нового значения PLL процессор (CPU) переключится
// на частоту OSCCLK/2.
//
// Время переключения равно 131072 XCLKIN циклов для Rev C silicon.
//
// Не обязательно ждать окончания данного периода, однако для
// использования корректных задержек, это сделать рекомендуется.
//------------------------------------------------------------------------
//------------------------------------------------------------------------
// Watchdog необходимо отключить, либо сбрасывать внутри цикла
//------------------------------------------------------------------------
DisableDog();
//-----------------------------------------------------------------------
// Формирование периода установки нового значения PLL
//-----------------------------------------------------------------------
// Длительность цикла рассчитана для 0-waitstate RAM memory.
//
// Если данная функция выполнятеся с wait-stated memory (например, FLASH
// или XINTF), тогда число циклов можно уменьшить
//-----------------------------------------------------------------------
for(i = 0; i < (131072/2) / 12; i++) // т.к. цикл занимает 12 команд
{
// ServiceDog();
}
}
}
int main(void){
DisableDog();
EALLOW;
unsigned int test = 0;
int laggingValue = 0xFF;
//unsigned int value = 0;
EALLOW;
CPUinit();
EALLOW;
DINT;
outputEnable();
initADC();
EALLOW;
DAC_init();
EALLOW;
outputEnable(); //having issues when not enabling twice
EALLOW;
timerINIT();
EALLOW;
while(1){
}
EALLOW;
return 0;
}
void InitSysCtrl(void)
{
// On F2812/F2810 TMX samples prior to rev C this initialization was
// required. For Rev C and after this is no longer required
/*
EALLOW;
DevEmuRegs.M0RAMDFT = 0x0300;
DevEmuRegs.M1RAMDFT = 0x0300;
DevEmuRegs.L0RAMDFT = 0x0300;
DevEmuRegs.L1RAMDFT = 0x0300;
DevEmuRegs.H0RAMDFT = 0x0300;
EDIS;
*/
// Disable the watchdog
DisableDog();
// Initialize the PLLCR to 0xA - set TMS320F clock to perform 150MHZ
InitPll(0xA);
// Initialize the peripheral clocks
InitPeripheralClocks();
}
Uint32 main(void) {
//GPIO and SCI are still setup from Sci_Boot()
//Setup sysctl and pll
DisableDog();
IntOsc1Sel();
InitPll(DSP28_PLLCR,DSP28_DIVSEL);
InitFlash();
DELAY_US(100);
// ApplicationPtr = (void(*)(void))SCI_Boot();
//
// if(ApplicationPtr)
// ApplicationPtr();
return SCI_Boot();
// asm(" .ref _ExitBoot");
// asm(" BF _ExitBoot,UNC");
// return 0;
}
void main(void)
{
DisableDog(); // Disable the watchdog
//-------------------------------------------------------------
// CLA module initialization
// 1) Enable the CLA clock
// 2) Init the CLA interrupt vectors
// 3) Allow the IACK instruction to flag a CLA interrupt/start a task
// 4) Assign CLA program and data memory to the CLA
// 5) Enable CLA interrupts (MIER)
//
// Note: As provided, the linker .cmd file links the CLA assembly
// code directly to the CLA program memory. Likewise the
// CLA data is copied directly to CLA data memory.
// This way the debugger will load the CLA assembly code
// into the program memory. (No need to copy the CLA code
// or data during debug).
//
//-------------------------------------------------------------
EALLOW;
SysCtrlRegs.PCLKCR3.bit.CLA1ENCLK = 1;
Cla1Regs.MVECT1 = (Uint16) (&Cla1Task1 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT2 = (Uint16) (&Cla1Task2 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT3 = (Uint16) (&Cla1Task3 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT4 = (Uint16) (&Cla1Task4 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT5 = (Uint16) (&Cla1Task5 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT6 = (Uint16) (&Cla1Task6 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT7 = (Uint16) (&Cla1Task7 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT8 = (Uint16) (&Cla1Task8 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MCTL.bit.IACKE = 1;
Cla1Regs.MMEMCFG.bit.PROGE = 1;
Cla1Regs.MMEMCFG.bit.RAM1E = 1;
asm(" RPT #3 || NOP");
Cla1Regs.MIER.bit.INT1 = 1;
Cla1Regs.MIER.bit.INT2 = 1;
Cla1Regs.MIER.bit.INT3 = 1;
Cla1Regs.MIER.bit.INT4 = 1;
Cla1Regs.MIER.bit.INT5 = 1;
Cla1Regs.MIER.bit.INT6 = 1;
Cla1Regs.MIER.bit.INT7 = 1;
Cla1Regs.MIER.bit.INT8 = 1;
EDIS;
//-------------------------------------------------------------
// Task 2: Clear all output variables
//
// Force Task 2 by the IACK instruction
// Wait for the task to complete
// This macro is defined in the Cla_Defines.h file
//-------------------------------------------------------------
Cla1ForceTask2andWait();
//-------------------------------------------------------------
// Initialize the input data
//-------------------------------------------------------------
CpuToCla1Msg.rad0 = -6.28318530718; // -2*pi = 1.0
CpuToCla1Msg.rad1 = -5.497787143783; // -7*pi/4 = 0.707106781187
CpuToCla1Msg.rad2 = -4.712388980385; // -6*pi/4 = 0.0
CpuToCla1Msg.rad3 = -3.926990816988; // -5*pi/4 = -0.707106781187
CpuToCla1Msg.rad4 = -3.14159265359; // -pi = -1.0
CpuToCla1Msg.rad5 = -2.356194490193; // -3*pi/4 = -0.707106781187
CpuToCla1Msg.rad6 = -1.570796326795; // -2*pi/4 = 0.0
CpuToCla1Msg.rad7 = -0.7853981633975; // -pi/4 = 0.707106781187
CpuToCla1Msg.rad8 = 0.0; // = 1.0
CpuToCla1Msg.rad9 = 0.7853981633975; // pi/4 = 0.707106781187
CpuToCla1Msg.rad10 = 1.570796326795; // 2*pi/4 = 0.0
CpuToCla1Msg.rad11 = 2.356194490193; // 3*pi/4 = -0.707106781187
CpuToCla1Msg.rad12 = 3.14159265359; // pi = -1.0
CpuToCla1Msg.rad13 = 3.926990816988; // 5*pi/4 = -0.707106781187
CpuToCla1Msg.rad14 = 4.712388980385; // 6*pi/4 = 0.0
CpuToCla1Msg.rad15 = 5.497787143783; // 7*pi/4 = 0.707106781187
CpuToCla1Msg.rad16 = 6.28318530718; // 2*pi = 1.0
CpuToCla1Msg.rad17 = 5.890486225482; // sin(.) = 0.9238795325118
CpuToCla1Msg.rad18 = -0.04; // sin(.) = 0.999200106661
CpuToCla1Msg.rad19 = -0.01; // sin(.) = 0.9999500004167
//-------------------------------------------------------------
// Force Task 1 by the IACK instruction
// Wait for the task to complete
// This macro is defined in the Cla_Defines.h file
//
// Note: Task 1 is setup to run the macro on rad0 - rad19
// The results will be stored in in y0-y19
//
//-------------------------------------------------------------
Cla1ForceTask1andWait();
//-------------------------------------------------------------
// When the task completes, check the results
//-------------------------------------------------------------
if(Cla1ToCpuMsg.y0.i32 == 0x3F800000)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y1.i32 == 0x3F3504EF)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y2.i32 == 0x00000000)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y3.i32 == 0xBF3504F8)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y4.i32 == 0xBF800000)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y5.i32 == 0xBF3504F3)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y6.i32 == 0x00000000)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y7.i32 == 0x3F3504F3)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y8.i32 == 0x3F800000)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y9.i32 == 0x3F3504F3)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y10.i32 == 0x00000000)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y11.i32 == 0xBF3504F3)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y12.i32 == 0xBF800000)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y13.i32 == 0xBF3504F8)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y14.i32 == 0x00000000)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y15.i32 == 0x3F3504EF)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y16.i32 == 0x3F800000)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y17.i32 == 0x3F6C835C)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y18.i32 == 0x3F7FCB94)
PASS_COUNT++;
else
FAIL_COUNT++;
if(Cla1ToCpuMsg.y19.i32 == 0x3F7FFCB9)
PASS_COUNT++;
else
FAIL_COUNT++;
//-------------------------------------------------------------
// End of test
//-------------------------------------------------------------
if(PASS_COUNT == GOLDEN_PASS_COUNT && FAIL_COUNT == 0)
{
// If test stopped here, it passed
ESTOP0;
}
else
{
// If test stopped here, it failed
ESTOP0;
}
}
void Disable_WAKEINT()
{
DisableDog();
}
//---------------------------------------------------------------------------
// InitECan:
//---------------------------------------------------------------------------
// This function initializes the eCAN module to a known state.
//
void InitECan(void)
{
long i;
asm(" EALLOW");
/* Disable Watchdog */
DisableDog();
/* Enable peripheral clocks */
InitPeripheralClocks();
/* Set PLL multiplication factor */
InitPll(0xA);
asm(" EALLOW");
/* Configure eCAN pins using GPIO regs*/
GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;
/* Configure eCAN RX and TX pins for eCAN transmissions using eCAN regs*/
ECanaRegs.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANRIOC.bit.RXFUNC = 1;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature
ECanaRegs.CANMC.bit.SCB = 1;
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
/* Clear all TAn bits */
ECanaRegs.CANTA.all = 0xFFFFFFFF;
/* Clear all RMPn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF;
/* Clear all interrupt flag bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters */
ECanaRegs.CANMC.bit.CCR = 1 ; // Set CCR = 1
while(ECanaRegs.CANES.bit.CCE != 1 ) {} // Wait for CCE bit to be set..
ECanaRegs.CANBTC.bit.BRPREG = 9;
ECanaRegs.CANBTC.bit.TSEG2REG = 2;
ECanaRegs.CANBTC.bit.TSEG1REG = 10;
ECanaRegs.CANMC.bit.CCR = 0 ; // Set CCR = 0
while(ECanaRegs.CANES.bit.CCE == !0 ) {} // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
}
void InitPll(Uint16 val, Uint16 divsel)
{
volatile Uint16 iVol;
// Make sure the PLL is not running in limp mode
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
{
EALLOW;
// OSCCLKSRC1 failure detected. PLL running in limp mode.
// Re-enable missing clock logic.
SysCtrlRegs.PLLSTS.bit.MCLKCLR = 1;
EDIS;
// Replace this line with a call to an appropriate
// SystemShutdown(); function.
asm(" ESTOP0"); // Uncomment for debugging purposes
}
// DIVSEL MUST be 0 before PLLCR can be changed from
// 0x0000. It is set to 0 by an external reset XRSn
// This puts us in 1/4
if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
EDIS;
}
// Change the PLLCR
if (SysCtrlRegs.PLLCR.bit.DIV != val)
{
EALLOW;
// Before setting PLLCR turn off missing clock detect logic
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
SysCtrlRegs.PLLCR.bit.DIV = val;
EDIS;
// Optional: Wait for PLL to lock.
// During this time the CPU will switch to OSCCLK/2 until
// the PLL is stable. Once the PLL is stable the CPU will
// switch to the new PLL value.
//
// This time-to-lock is monitored by a PLL lock counter.
//
// Code is not required to sit and wait for the PLL to lock.
// However, if the code does anything that is timing critical,
// and requires the correct clock be locked, then it is best to
// wait until this switching has completed.
// Wait for the PLL lock bit to be set.
// The watchdog should be disabled before this loop, or fed within
// the loop via ServiceDog().
// Uncomment to disable the watchdog
DisableDog();
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
{
// Uncomment to service the watchdog
// ServiceDog();
}
EALLOW;
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
EDIS;
}
// If switching to 1/2
if((divsel == 1)||(divsel == 2))
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
EDIS;
}
// If switching to 1/1
// * First go to 1/2 and let the power settle
// The time required will depend on the system, this is only an example
// * Then switch to 1/1
if(divsel == 3)
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
//DELAY_US(50L);
SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
EDIS;
}
}
void main(void)
{
// union F32_I32 temp;
DisableDog(); // Disable the watchdog
//-------------------------------------------------------------
// CLA module initialization
// 1) Enable the CLA clock
// 2) Init the CLA interrupt vectors
// 3) Allow the IACK instruction to flag a CLA interrupt/start a task
// 4) Assign CLA program memory to the CLA
// 5) Enable CLA interrupts (MIER)
//
// Note: As provided, the linker .cmd file links the CLA assembly
// code directly to the CLA program memory.
// This way the debugger will load the CLA assembly code
// into the program memory. (No need to copy the CLA code
// during debug).
//
//-------------------------------------------------------------
EALLOW;
SysCtrlRegs.PCLKCR3.bit.CLA1ENCLK = 1;
Cla1Regs.MVECT1 = (Uint16) (&Cla1Task1 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT2 = (Uint16) (&Cla1Task2 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT3 = (Uint16) (&Cla1Task3 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT4 = (Uint16) (&Cla1Task4 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT5 = (Uint16) (&Cla1Task5 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT6 = (Uint16) (&Cla1Task6 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT7 = (Uint16) (&Cla1Task7 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MVECT8 = (Uint16) (&Cla1Task8 - &Cla1Prog_Start)*sizeof(Uint32);
Cla1Regs.MCTL.bit.IACKE = 1;
Cla1Regs.MMEMCFG.bit.PROGE = 1;
Cla1Regs.MMEMCFG.bit.RAM1E = 1;
asm(" RPT #3 || NOP");
Cla1Regs.MIER.bit.INT1 = 1;
Cla1Regs.MIER.bit.INT2 = 1;
Cla1Regs.MIER.bit.INT3 = 1;
Cla1Regs.MIER.bit.INT4 = 1;
Cla1Regs.MIER.bit.INT5 = 1;
Cla1Regs.MIER.bit.INT6 = 1;
Cla1Regs.MIER.bit.INT7 = 1;
Cla1Regs.MIER.bit.INT8 = 1;
EDIS;
//-------------------------------------------------------------
// All tests performed with rounding off (RNDF32=0)
//-------------------------------------------------------------
//-------------------------------------------------------------
// Test 1:
//-------------------------------------------------------------
CpuToCla1Msg.Num1 = 1.0;
CpuToCla1Msg.Base1 = 2.0;
// Force Task 2 by the IACK instruction
// Wait for the task to complete
// This macro is defined in the Cla_Defines.h file
Cla1ForceTask2andWait()
y_x1=Cla1ToCpuMsg.y1.f32;
//-------------------------------------------------------------
// Test 2:
//-------------------------------------------------------------
CpuToCla1Msg.Num1 = 10;
CpuToCla1Msg.Base1 = 10.0;
// Force Task 2 by the IACK instruction
// Wait for the task to complete
// This macro is defined in the Cla_Defines.h file
Cla1ForceTask2andWait()
y_x2=Cla1ToCpuMsg.y1.f32;
//-------------------------------------------------------------
// Test 3:
//-------------------------------------------------------------
CpuToCla1Msg.Num1 = 4.6;
CpuToCla1Msg.Base1 = 2.3;
// Force Task 2 by the IACK instruction
// Wait for the task to complete
// This macro is defined in the Cla_Defines.h file
Cla1ForceTask2andWait()
y_x3=Cla1ToCpuMsg.y1.f32;
//-------------------------------------------------------------
// Test 4:
//-------------------------------------------------------------
CpuToCla1Msg.Num1 = 256;
CpuToCla1Msg.Base1 = 2;
// Force Task 2 by the IACK instruction
// Wait for the task to complete
// This macro is defined in the Cla_Defines.h file
Cla1ForceTask2andWait()
y_x4=Cla1ToCpuMsg.y1.f32;
//-------------------------------------------------------------
// Test 5:
//-------------------------------------------------------------
CpuToCla1Msg.Num1 = 50.923;
CpuToCla1Msg.Base1 = 10.0;
// Force Task 2 by the IACK instruction
// Wait for the task to complete
// This macro is defined in the Cla_Defines.h file
Cla1ForceTask2andWait()
y_x5=Cla1ToCpuMsg.y1.f32;
//-------------------------------------------------------------
// start of test
//-------------------------------------------------------------
chk1=0- y_x1;
chk2=1 - y_x2;
chk3=1.83220025 - y_x3;
chk4=8 - y_x4;
chk5=1.70691398 - (y_x5 );
if(chk1>=-10e-6 & chk1<=10e-6)
PASS_COUNT++; // If all tests pass, this should equal golden value
else
FAIL_COUNT++;
if(chk2>=-10e-6 & chk2<=10e-6)
PASS_COUNT++; // If all tests pass, this should equal golden value
else
FAIL_COUNT++;
if(chk3>=-10e-6 & chk3<=10e-6)
PASS_COUNT++; // If all tests pass, this should equal golden value
else
FAIL_COUNT++;
if(chk4>=-10e-6 & chk4<=10e-6)
PASS_COUNT++; // If all tests pass, this should equal golden value
else
FAIL_COUNT++;
if(chk5>=-10e-6 & chk5<=10e-6)
PASS_COUNT++; // If all tests pass, this should equal golden value
else
FAIL_COUNT++;
if(PASS_COUNT == GOLDEN_PASS_COUNT && FAIL_COUNT == 0)
{
// If test stopped here, it passed
ESTOP0;
}
else
{
// If test stopped here, it failed
ESTOP0;
}
}
void InitSysCtrl(void)
{
// Disable the watchdog
DisableDog();
#ifdef _FLASH
// Copy time critical code and Flash setup code to RAM
// This includes the following functions: InitFlash();
// The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart
// symbols are created by the linker. Refer to the device .cmd file.
memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize);
// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
InitFlash();
#endif
// *IMPORTANT*
// The Device_cal function, which copies the ADC & oscillator calibration values
// from TI reserved OTP into the appropriate trim registers, occurs automatically
// in the Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC and oscillators to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.
#ifdef CPU1
EALLOW;
//enable pull-ups on unbonded IOs as soon as possible to reduce power consumption.
GPIO_EnableUnbondedIOPullups();
CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
CpuSysRegs.PCLKCR13.bit.ADC_B = 1;
CpuSysRegs.PCLKCR13.bit.ADC_C = 1;
CpuSysRegs.PCLKCR13.bit.ADC_D = 1;
//check if device is trimmed
if(*((Uint16 *)0x5D1B6) == 0x0000){
//device is not trimmed, apply static calibration values
AnalogSubsysRegs.ANAREFTRIMA.all = 31709;
AnalogSubsysRegs.ANAREFTRIMB.all = 31709;
AnalogSubsysRegs.ANAREFTRIMC.all = 31709;
AnalogSubsysRegs.ANAREFTRIMD.all = 31709;
}
CpuSysRegs.PCLKCR13.bit.ADC_A = 0;
CpuSysRegs.PCLKCR13.bit.ADC_B = 0;
CpuSysRegs.PCLKCR13.bit.ADC_C = 0;
CpuSysRegs.PCLKCR13.bit.ADC_D = 0;
EDIS;
// Initialize the PLL control: PLLCR and CLKINDIV
// F28_PLLCR and F28_CLKINDIV are defined in F2837xD_Examples.h
// Note: The internal oscillator CANNOT be used as the PLL source if the
// PLLSYSCLK is configured to frequencies above 194 MHz.
InitSysPll(XTAL_OSC,IMULT_20,FMULT_1,PLLCLK_BY_2); //PLLSYSCLK = 20MHz(XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
//Turn on all peripherals
InitPeripheralClocks();
#endif
}
