void SystemClockInit(void)
{
UNLOCKREG();
DrvSYS_SetOscCtrl(E_SYS_XTL12M, ENABLE);
DrvSYS_Delay(5000);
DrvSYS_Open(50000000);
/* Enable PLL */
//DrvSYS_SetPLLMode(0);
/* Switch to PLL clock */
// DrvSYS_SelectHCLKSource(2);
/* Update system core clock */
//SystemCoreClockUpdate();
}
void setupSystemClock()
{
#ifdef M451
SYS_UnlockReg();
/* Enable HIRC clock */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to HIRC */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Set core clock as PLL_CLOCK from PLL and SysTick source to HCLK/2*/
CLK_SetCoreClock(SYSTEM_CLOCK);
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_HCLK_DIV2);
SYS_LockReg();
#else
uint32_t u32PllCr;
uint16_t i;
UNLOCKREG();
DrvSYS_SetOscCtrl(E_SYS_OSC22M, 1);
while (DrvSYS_GetChipClockSourceStatus(E_SYS_OSC22M) != 1);
DrvSYS_SelectPLLSource(E_SYS_INTERNAL_22M);
u32PllCr = DrvSYS_GetPLLContent(E_SYS_INTERNAL_22M, SYSTEM_CLOCK);
/*Delay for 12M or 22M stable*/
for (i=0;i<10000;i++);
DrvSYS_SetPLLContent(u32PllCr);
SYSCLK->PLLCON.OE = 0;
SYSCLK->PLLCON.PD = 0;
/*Delay for PLL stable*/
for (i=0;i<10000;i++);
/* Change HCLK clock source to be PLL. */
DrvSYS_SelectHCLKSource(2);
LOCKREG(); // Lock the protected registers
#endif
}
int main(void)
{
uint8_t buffer[32] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16};
/* Unlock the protected registers */
UNLOCKREG();
/* Enable the 12MHz oscillator oscillation */
DrvSYS_SetOscCtrl(E_SYS_XTL12M, 1);
/* Waiting for 12MHz Xtal stable */
DrvSYS_Delay(5000);
/* HCLK clock source. 0: external 12MHz. */
DrvSYS_SelectHCLKSource(0);
LOCKREG();
DrvSYS_SetClockDivider(E_SYS_HCLK_DIV, 0); /* HCLK clock frequency = HCLK clock source / (HCLK_N + 1) */
nrf_init();
nrf_detect();
//nrf_rx_mode_no_aa(addr,5,16,40);
//nrf_rx_mode(addr,5,16,40);
nrf_rx_mode_dual(addr,5,40);
nrf_test_reg();
DrvGPIO_Open(E_GPA, 2, E_IO_OUTPUT);
DrvGPIO_Open(E_GPA, 3, E_IO_OUTPUT);
DrvGPIO_Open(E_GPA, 4, E_IO_OUTPUT);
DrvGPIO_Open(E_GPA, 5, E_IO_OUTPUT);
{
uint8_t status = nrf_read_reg(NRF_STATUS);
nrf_write_reg(NRF_WRITE_REG|NRF_STATUS,status); // clear IRQ flags
nrf_write_reg(NRF_FLUSH_RX, 0xff);
nrf_write_reg(NRF_FLUSH_TX, 0xff);
}
while(1) {
uint8_t buffer[32];
if(tx_done) {
static uint8_t yy = 0;
yy++;
if(yy&1) {
DrvGPIO_SetBit(E_GPA,2);
} else {
DrvGPIO_ClrBit(E_GPA,2);
}
if(tx_done == 1) {
} else {
}
buffer[0] = tx_done;
tx_done = 0;
}
if(rx_done) {
static uint8_t xx = 0;
rx_done = 0;
xx++;
if(xx & 1)
DrvGPIO_SetBit(E_GPA,5);
else
DrvGPIO_ClrBit(E_GPA,5);
//nrf_ack_packet(0,buffer, (xx&15) + 1);
nrf_ack_packet(0,rx_buffer, rx_len);
}
}
while(1) {
static uint8_t cnt = 0;
if(cnt&1) {
DrvGPIO_SetBit(E_GPA,2);
} else {
DrvGPIO_ClrBit(E_GPA,2);
}
DrvSYS_Delay(50000*2);
cnt++;
//nrf_tx_packet(buffer, 16);
//buffer[0]++;
if(nrf_rx_packet(buffer,16) == NRF_RX_OK)
{
static uint8_t xx = 0;
xx++;
if(xx & 1)
DrvGPIO_SetBit(E_GPA,5);
else
DrvGPIO_ClrBit(E_GPA,5);
}
}
return 0;
}