void isr_Edma3CCError(unsigned int intnum) {
UNUSED(intnum);
unsigned int qdmamisserror, dmamisserror_L, dmamisserror_H, ccerror;
qdmamisserror = EDMA3QdmaGetErrIntrStatus(EDMA_INST_BASE);
dmamisserror_L = EDMA3GetErrIntrStatus(EDMA_INST_BASE);
dmamisserror_H = EDMA3ErrIntrHighStatusGet(EDMA_INST_BASE);
ccerror = EDMA3GetCCErrStatus(EDMA_INST_BASE);
/*set globle error bit*/
g_Edma.bmQdmaMissError |= qdmamisserror;
g_Edma.bmDmaMissErrorL |= dmamisserror_L;
g_Edma.bmDmaMissErrorH |= dmamisserror_H;
g_Edma.bmEdmaCcError |= ccerror;
/*if error bit set,clear conrrisponding error bit*/
if (qdmamisserror) {
EDMA3QdmaClrMissEvt_all(EDMA_INST_BASE, qdmamisserror);
}
if (dmamisserror_L) {
EDMA3ClrMissEvt_L(EDMA_INST_BASE, dmamisserror_L);
}
if (dmamisserror_H) {
EDMA3ClrMissEvt_H(EDMA_INST_BASE, dmamisserror_H);
}
if (ccerror) {
EDMA3ClrCCErr(EDMA_INST_BASE, ccerror);
}
/*revalue the error bit, if have new error bit trig ERROR intr*/
qdmamisserror = EDMA3QdmaGetErrIntrStatus(EDMA_INST_BASE);
dmamisserror_L = EDMA3GetErrIntrStatus(EDMA_INST_BASE);
dmamisserror_H = EDMA3ErrIntrHighStatusGet(EDMA_INST_BASE);
ccerror = EDMA3GetCCErrStatus(EDMA_INST_BASE);
if (qdmamisserror || dmamisserror_L || dmamisserror_H || ccerror) {
EDMA3ErrIntrTrig(EDMA_INST_BASE);
}
}
/*
** EDMA Error Interrupt Service Routine(ISR).
*/
static void Edma3CCErrorIsr(void)
{
volatile unsigned int pendingIrqs = 0;
unsigned int evtqueNum = 0;
unsigned int index = 1;
unsigned int Cnt = 0;
if((0 != EDMA3GetErrIntrStatus(SOC_EDMA30CC_0_REGS)) ||
(0 != (EDMA3GetCCErrStatus(SOC_EDMA30CC_0_REGS))))
{
/* Loop for EDMA3CC_ERR_HANDLER_RETRY_COUNT number of time, breaks
when no pending interrupt is found */
while ((Cnt < EDMA3CC_ERR_HANDLER_RETRY_COUNT) && (index != 0u))
{
index = 0u;
pendingIrqs = EDMA3GetErrIntrStatus(SOC_EDMA30CC_0_REGS);
while (pendingIrqs)
{
/*Process all the pending interrupts*/
if((pendingIrqs & 1u)==TRUE)
{
/* Writing to EMCR to clear the corresponding EMR bits.
Also clearing any Secondary events in SER. */
EDMA3ClrMissEvt(SOC_EDMA30CC_0_REGS, index);
}
++index;
pendingIrqs >>= 1u;
}
index = 0u;
pendingIrqs = EDMA3GetCCErrStatus(SOC_EDMA30CC_0_REGS);
if (pendingIrqs != 0u)
{
/* Process all the pending CC error interrupts. */
/* Queue threshold error for different event queues. */
for (evtqueNum = 0u; evtqueNum < EDMA3_0_NUM_EVTQUE; evtqueNum++)
{
if((pendingIrqs & (1u << evtqueNum)) != 0u)
{
/* Clear the error interrupt. */
EDMA3ClrCCErr(SOC_EDMA30CC_0_REGS, (1u << evtqueNum));
}
}
/* Transfer completion code error. */
if ((pendingIrqs & (1 << EDMA3CC_CCERR_TCCERR_SHIFT)) != 0u)
{
EDMA3ClrCCErr(SOC_EDMA30CC_0_REGS,
(0x01u << EDMA3CC_CCERR_TCCERR_SHIFT));
}
++index;
}
Cnt++;
}
/* Enable error to be evaluated again */
EDMA3CCErrorEvaluate(SOC_EDMA30CC_0_REGS);
}
}
static void Edma3CCErrorIsr(void)
{
volatile unsigned int pendingIrqs;
volatile unsigned int evtqueNum = 0; /* Event Queue Num */
volatile unsigned int isIPRH = 0;
volatile unsigned int isIPR = 0;
volatile unsigned int Cnt = 0u;
volatile unsigned int index;
pendingIrqs = 0u;
index = 1u;
isIPR = EDMA3GetIntrStatus(EDMA_INST_BASE);
isIPRH = EDMA3IntrStatusHighGet(EDMA_INST_BASE);
if((isIPR | isIPRH ) || (EDMA3QdmaGetErrIntrStatus(EDMA_INST_BASE) != 0)
|| (EDMA3GetCCErrStatus(EDMA_INST_BASE) != 0))
{
/* Loop for EDMA3CC_ERR_HANDLER_RETRY_COUNT number of time,
* breaks when no pending interrupt is found
*/
while ((Cnt < EDMA3CC_ERR_HANDLER_RETRY_COUNT)
&& (index != 0u))
{
index = 0u;
if(isIPR)
{
pendingIrqs = EDMA3GetErrIntrStatus(EDMA_INST_BASE);
}
else
{
pendingIrqs = EDMA3ErrIntrHighStatusGet(EDMA_INST_BASE);
}
while (pendingIrqs)
{
/*Process all the pending interrupts*/
if(TRUE == (pendingIrqs & 1u))
{
/* Write to EMCR to clear the corresponding EMR bits.
*/
/*Clear any SER*/
if(isIPR)
{
EDMA3ClrMissEvt(EDMA_INST_BASE, index);
}
else
{
EDMA3ClrMissEvt(EDMA_INST_BASE, index + 32);
}
}
++index;
pendingIrqs >>= 1u;
}
index = 0u;
pendingIrqs = EDMA3QdmaGetErrIntrStatus(EDMA_INST_BASE);
while (pendingIrqs)
{
/*Process all the pending interrupts*/
if(TRUE == (pendingIrqs & 1u))
{
/* Here write to QEMCR to clear the corresponding QEMR bits*/
/*Clear any QSER*/
EDMA3QdmaClrMissEvt(EDMA_INST_BASE, index);
}
++index;
pendingIrqs >>= 1u;
}
index = 0u;
pendingIrqs = EDMA3GetCCErrStatus(EDMA_INST_BASE);
if (pendingIrqs != 0u)
{
/* Process all the pending CC error interrupts. */
/* Queue threshold error for different event queues.*/
for (evtqueNum = 0u; evtqueNum < SOC_EDMA3_NUM_EVQUE; evtqueNum++)
{
if((pendingIrqs & (1u << evtqueNum)) != 0u)
{
/* Clear the error interrupt. */
EDMA3ClrCCErr(EDMA_INST_BASE, (1u << evtqueNum));
}
}
/* Transfer completion code error. */
if ((pendingIrqs & (1 << EDMA3CC_CCERR_TCCERR_SHIFT)) != 0u)
{
EDMA3ClrCCErr(EDMA_INST_BASE,
(0x01u << EDMA3CC_CCERR_TCCERR_SHIFT));
}
++index;
}
Cnt++;
}
}
}
/*
** Interrupt ISR for Channel controller error.
**
** Note: This function first disables its own interrupt to make it non-entrant.
*/
void _EDMAAppEdma3ccErrIsr()
{
volatile unsigned int pendingIrqs;
volatile unsigned int evtQueNum = 0u; /* Event Queue Num */
volatile unsigned int isHighIntrPending = 0u;
volatile unsigned int isIntrPending = 0u;
volatile unsigned int count = 0u;
volatile unsigned int index;
pendingIrqs = 0u;
index = 1u;
isIntrPending = EDMA3GetIntrStatus(EDMAAPP_EDMACC_BASE_ADDRESS);
isHighIntrPending = EDMA3IntrStatusHighGet(EDMAAPP_EDMACC_BASE_ADDRESS);
if((isIntrPending | isHighIntrPending ) ||
(EDMA3QdmaGetErrIntrStatus(EDMAAPP_EDMACC_BASE_ADDRESS) != 0u)
|| (EDMA3GetCCErrStatus(EDMAAPP_EDMACC_BASE_ADDRESS) != 0u))
{
/* Loop for EDMA3CC_ERR_HANDLER_RETRY_COUNT number of time,
** breaks when no pending interrupt is found
*/
while ((count < EDMA3CC_ERR_HANDLER_RETRY_COUNT) && (index != 0u))
{
index = 0u;
if(isIntrPending)
{
pendingIrqs =
EDMA3GetErrIntrStatus(EDMAAPP_EDMACC_BASE_ADDRESS);
}
else
{
pendingIrqs =
EDMA3ErrIntrHighStatusGet(EDMAAPP_EDMACC_BASE_ADDRESS);
}
while(pendingIrqs)
{
/* Process all the pending interrupts */
if(TRUE == (pendingIrqs & 1u))
{
/*
** Write to EMCR to clear the corresponding EMR bits.
** Clear any SER
*/
if(isIntrPending)
{
EDMA3ClrMissEvt(EDMAAPP_EDMACC_BASE_ADDRESS, index);
}
else
{
EDMA3ClrMissEvt(EDMAAPP_EDMACC_BASE_ADDRESS,
index + 32u);
}
}
++index;
pendingIrqs >>= 1u;
}
index = 0u;
pendingIrqs =
EDMA3QdmaGetErrIntrStatus(EDMAAPP_EDMACC_BASE_ADDRESS);
while(pendingIrqs)
{
/* Process all the pending interrupts */
if(TRUE == (pendingIrqs & 1u))
{
/*
** Here write to QEMCR to clear the corresponding QEMR bits
** Clear any QSER
*/
EDMA3QdmaClrMissEvt(EDMAAPP_EDMACC_BASE_ADDRESS, index);
}
++index;
pendingIrqs >>= 1u;
}
index = 0u;
pendingIrqs = EDMA3GetCCErrStatus(EDMAAPP_EDMACC_BASE_ADDRESS);
if(pendingIrqs != 0u)
{
/*
** Process all the pending CC error interrupts.
** Queue threshold error for different event queues.
*/
for(evtQueNum = 0u; evtQueNum < SOC_EDMA3_NUM_EVQUE;
evtQueNum++)
{
if((pendingIrqs & (1u << evtQueNum)) != 0u)
{
/* Clear the error interrupt. */
EDMA3ClrCCErr(EDMAAPP_EDMACC_BASE_ADDRESS,
(1u << evtQueNum));
}
}
/* Transfer completion code error. */
if((pendingIrqs & (1u << EDMA3CC_CCERR_TCCERR_SHIFT)) != 0u)
{
EDMA3ClrCCErr(EDMAAPP_EDMACC_BASE_ADDRESS,
(1u << EDMA3CC_CCERR_TCCERR_SHIFT));
}
++index;
}
count++;
}
}
}
