IOReturn IrDAUserClient::registerNotificationPort(mach_port_t port, UInt32 type) { ELG(0, 0, 'irda', "IrDAUser: register notification ignored"); return (kIOReturnUnsupported); }
IOReturn IrDAUserClient::connectClient(IOUserClient *client) { ELG(0, 0, 'irda', "IrDAUser: connect client"); return (kIOReturnSuccess); }
IOReturn IrDAUserClient::getIrDALog(void *pIn, void *pOut, IOByteCount inputSize, IOByteCount *outPutSize) { #if (hasTracing > 0) IOMemoryDescriptor *md; // make a memory descriptor for the client's big buffer unsigned char *input = (unsigned char *)pIn; mach_vm_address_t bigaddr; IOByteCount biglen; IrDALogInfo *info; require(inputSize == 9, Fail); require(outPutSize, Fail); require(*outPutSize == sizeof(IrDALogInfo), Fail); //bigaddr = input[1] << 24 | input[2] << 16 | input[3] << 8 | input[4]; //biglen = input[5] << 24 | input[6] << 16 | input[7] << 8 | input[8]; bcopy(&input[1], &bigaddr, sizeof(bigaddr)); bcopy(&input[5], &biglen, sizeof(biglen)); //IOLog("biglen is %d\n", biglen); // create and init the memory descriptor //md = IOMemoryDescriptor::withAddress(bigaddr, biglen, kIODirectionOutIn, fTask); // REVIEW direction //use withAddressRange() and prepare() instead md = IOMemoryDescriptor::withAddressRange(bigaddr, biglen, kIODirectionOutIn, fTask); // REVIEW direction md->prepare(kIODirectionOutIn); require(md, Fail); info = IrDALogGetInfo(); // get the info block //ELG(info->hdr, info->hdrSize, 'irda', "info hdr"); //ELG(info->eventLog, info->eventLogSize, 'irda', "info events"); //ELG(info->msgBuffer, info->msgBufferSize, 'irda', "info msg buf"); bcopy(info, pOut, sizeof(*info)); // copy the info record back to the client *outPutSize = sizeof(*info); // set the output size (nop, it already is) // copy the buffer over now if there is room if (biglen >= info->hdrSize + info->eventLogSize + info->msgBufferSize) { IOByteCount ct; IOReturn rc; rc = md->prepare(kIODirectionNone); if (rc) {ELG(-1, rc, 'irda', "prepare failed"); } ct = md->writeBytes(0, info->hdr, info->hdrSize); if (ct != info->hdrSize) ELG(-1, rc, 'irda', "write of hdr failed"); ct = md->writeBytes(info->hdrSize, info->eventLog, info->eventLogSize); if (ct != info->eventLogSize) ELG(-1, rc, 'irda', "write of events failed"); ct = md->writeBytes(info->hdrSize+info->eventLogSize, info->msgBuffer, info->msgBufferSize); if (ct != info->msgBufferSize) ELG(-1, rc, 'irda', "write of msgs failed"); ELG(0, info->hdrSize+info->eventLogSize, 'irda', "wrote msgs at offset"); rc = md->complete(kIODirectionNone); if (!rc) { ELG(0, 0, 'irda', "complete worked"); } else { ELG(-1, rc, 'irda', "complete failed"); } // todo check return code of above before resetting the buffer IrDALogReset(); // reset the buffer now } md->release(); // free it return kIOReturnSuccess; Fail: #endif // hasTracing > 0 return kIOReturnBadArgument; }
IOReturn IrDAUserClient::clientDied(void) { ELG(0, 0, 'irda', "IrDAUser: client died"); return (clientClose()); }
void UniNEnet::stopPHY() { UInt32 val32; UInt16 i, val16; ELG( fWOL, fPHYType, '-Phy', "UniNEnet::stopPHY" ); if ( !fBuiltin || (fPHYType == 0) ) return; if ( fWOL == false ) { // disabling MIF interrupts on the 5201 is explicit if ( fPHYType == 0x5201 ) miiWriteWord( 0x0000, MII_BCM5201_INTERRUPT ); } /* Turn off PHY status-change polling to prevent immediate wakeup: */ val32 = READ_REGISTER( MIFConfiguration ); val32 &= ~kMIFConfiguration_Poll_Enable; WRITE_REGISTER( MIFConfiguration, val32 ); if ( fWOL ) { // For multicast filtering these bits must be enabled WRITE_REGISTER( RxMACConfiguration, kRxMACConfiguration_Hash_Filter_Enable | kRxMACConfiguration_Strip_FCS | kRxMACConfiguration_Rx_Mac_Enable ); UInt16 *p16; p16 = (UInt16*)myAddress.bytes; WRITE_REGISTER( WOLMagicMatch[ 2 ], p16[ 0 ] ); // enet address WRITE_REGISTER( WOLMagicMatch[ 1 ], p16[ 1 ] ); WRITE_REGISTER( WOLMagicMatch[ 0 ], p16[ 2 ] ); WRITE_REGISTER( WOLPatternMatchCount, kWOLPatternMatchCount_M | kWOLPatternMatchCount_N ); val32 = kWOLWakeupCSR_Magic_Wakeup_Enable; // Assume GMII if ( !(fXIFConfiguration & kXIFConfiguration_GMIIMODE) ) val32 |= kWOLWakeupCSR_Mode_MII; // NG - indicate non GMII WRITE_REGISTER( WOLWakeupCSR, val32 ); } else { WRITE_REGISTER( RxMACConfiguration, 0 ); IOSleep( 4 ); // it takes time for enable bit to clear } WRITE_REGISTER( TxMACConfiguration, 0 ); WRITE_REGISTER( XIFConfiguration, 0 ); fTxConfiguration &= ~kTxConfiguration_Tx_DMA_Enable; WRITE_REGISTER( TxConfiguration, fTxConfiguration ); fRxConfiguration &= ~kRxConfiguration_Rx_DMA_Enable; WRITE_REGISTER( RxConfiguration, fRxConfiguration ); if ( !fWOL ) { // this doesn't power down stuff, but if we don't hit it then we can't // superisolate the transceiver WRITE_REGISTER( SoftwareReset, kSoftwareReset_TX | kSoftwareReset_RX ); i = 0; do { IODelay( 10 ); if ( i++ >= 100 ) { ALRT( 0, val32, 'Sft-', "UniNEnet::stopPHY - timeout on SoftwareReset" ); break; } val32 = READ_REGISTER( SoftwareReset ); } while ( (val32 & (kSoftwareReset_TX | kSoftwareReset_RX)) != 0 ); WRITE_REGISTER( TxMACSoftwareResetCommand, kTxMACSoftwareResetCommand_Reset ); WRITE_REGISTER( RxMACSoftwareResetCommand, kRxMACSoftwareResetCommand_Reset ); // This is what actually turns off the LINK LED switch ( fPHYType ) { case 0x5400: case 0x5401: #if 0 // The 5400 has read/write privilege on this bit, // but 5201 is read-only. miiWriteWord( MII_CONTROL_POWERDOWN, MII_CONTROL ); #endif break; case 0x5221: // 1: enable shadow mode registers in 5221 (0x1A-0x1E) miiReadWord( &val16, MII_BCM5221_TestRegister ); miiWriteWord( val16 | MII_BCM5221_ShadowRegEnableBit, MII_BCM5221_TestRegister ); // 2: Force IDDQ mode for max power savings // remember..after setting IDDQ mode we have to "hard" reset // the PHY in order to access it. miiReadWord( &val16, MII_BCM5221_AuxiliaryMode4 ); miiWriteWord( val16 | MII_BCM5221_SetIDDQMode, MII_BCM5221_AuxiliaryMode4 ); break; case 0x5241: // 1: enable shadow register mode miiReadWord( &val16, MII_BCM5221_TestRegister ); miiWriteWord( val16 | MII_BCM5221_ShadowRegEnableBit, MII_BCM5221_TestRegister ); // 2: Set standby power bit miiReadWord( &val16, MII_BCM5221_AuxiliaryMode4 ); miiWriteWord( val16 | MII_BCM5241_StandbyPowerMode, MII_BCM5221_AuxiliaryMode4 ); break; case 0x5201: #if 0 miiReadWord( &val16, MII_BCM5201_AUXMODE2 ); miiWriteWord( val16 & ~MII_BCM5201_AUXMODE2_LOWPOWER, MII_BCM5201_AUXMODE2 ); #endif miiWriteWord( MII_BCM5201_MULTIPHY_SUPERISOLATE, MII_BCM5201_MULTIPHY ); break; case 0x5411: case 0x5421: default: miiWriteWord( MII_CONTROL_POWERDOWN, MII_CONTROL ); break; }/* end SWITCH on PHY type */ /* Put the MDIO pins into a benign state. */ /* Note that the management regs in the PHY will be inaccessible. */ /* This is to guarantee max power savings on Powerbooks and */ /* to eliminate damage to Broadcom PHYs. */ WRITE_REGISTER( MIFConfiguration, kMIFConfiguration_BB_Mode ); // bit bang mode WRITE_REGISTER( MIFBitBangClock, 0x0000 ); WRITE_REGISTER( MIFBitBangData, 0x0000 ); WRITE_REGISTER( MIFBitBangOutputEnable, 0x0000 ); WRITE_REGISTER( XIFConfiguration, kXIFConfiguration_GMIIMODE | kXIFConfiguration_MII_Int_Loopback ); val32 = READ_REGISTER( XIFConfiguration ); /// ??? make sure it takes. }// end of non-WOL case return; }/* end stopPHY */