//-----------------------------------------------------------------------------
// \brief initialize the lcd controller for raster use.
//
// \param none.
//
// \return uint32_t
// ERR_NO_ERROR - everything is ok...lcdc ready to use.
// ERR_INIT_FAIL - something happened during initialization.
//-----------------------------------------------------------------------------
uint32_t LIDD_init(void)
{
uint32_t rtn = ERR_NO_ERROR;
/* Enable the LCD Hardware */
EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_LCDC, PSC_ENABLE);
/* Set MUX_MODE on UI GPIO expander to LCD */
EVMOMAPL138_pinmuxConfig(PINMUX_LCD_D_BUS_0_REG, PINMUX_LCD_D_BUS_0_MASK, PINMUX_LCD_D_BUS_0_VALUE);
EVMOMAPL138_pinmuxConfig(PINMUX_LCD_D_BUS_1_REG, PINMUX_LCD_D_BUS_1_MASK, PINMUX_LCD_D_BUS_1_VALUE);
EVMOMAPL138_pinmuxConfig(PINMUX_LCD_D_BUS_2_REG, PINMUX_LCD_D_BUS_2_MASK, PINMUX_LCD_D_BUS_2_VALUE);
EVMOMAPL138_pinmuxConfig(PINMUX_LCD_CONTROL_0_REG, PINMUX_LCD_CONTROL_0_MASK, PINMUX_LCD_CONTROL_0_VALUE);
EVMOMAPL138_pinmuxConfig(PINMUX_LCD_CONTROL_1_REG, PINMUX_LCD_CONTROL_1_MASK, PINMUX_LCD_CONTROL_1_VALUE);
/*
* LCD Panel
* 8.824 MHz, raster mode pixel clock, 480-272 viewable frame
*/
LCD_RASTER_CTRL &= 0xfffffffe; // Turn raster controller off
LCD_LIDD_CTRL = 0x0000000C; // LIDD mode 0x4
LCD_LCD_STAT = 0x000003ff; // Clear status bits
LCD_LCD_CTRL = 0x00002500; // PCLK = 150MHz / 37 = 4.054 MHz, LIDD mode
LCD_LIDD_CS0_CONF = 0xF7DCE3BA;
//F 7 D C E 3 B A
//1111 0111 1101 1100 1110 0011 1011 1010
//gggg gfff fffe eeed dddd cccc ccbb bbaa
//////////////////////////////////////////////////
// Enable the Char LCD
//////////////////////////////////////////////////
// enable video (active low) via gpio expander and disable rmii phy to
// ensure we have exclusive access to the bus.
// TODO: need to update for new board rev.
rtn = I2CGPIO_init(I2C_ADDR_GPIO_UI);
if (rtn != ERR_NO_ERROR)
return (ERR_NO_UI_BOARD);
/*
rtn = EMAC_init(EMAC_INTERFACE_RMII);
rtn |= EMAC_phyPowerDown();
if (rtn != ERR_NO_ERROR)
return (rtn);
*/
// make sure we are getting a 27MHz clock.
rtn = CDCE913_init();
rtn |= I2CGPIO_setOutput(I2C_ADDR_GPIO_UI, I2C_GPIO_UI_ETHER_PGM_ENn, 1);
rtn |= I2CGPIO_setOutput(I2C_ADDR_GPIO_UI, I2C_GPIO_UI_SELA, 0);
rtn |= I2CGPIO_setOutput(I2C_ADDR_GPIO_UI, I2C_GPIO_UI_SELB, 0);
rtn |= I2CGPIO_setOutput(I2C_ADDR_GPIO_UI, I2C_GPIO_UI_SELC, 0);
return (rtn);
}
void init_ColorVision(void) {
// initialize ov6620 cmos camera
i2cdata[0] = 0x01;
i2cdata[1] = 0x8F; // Blue Gain control (default 0x80)
i2cdata[2] = 0x8F; // Red Gain Control
i2cdata[3] = 0x80; // Saturation
i2cdata[4] = 0x00; // Reserved
i2cdata[5] = 0x4f; // Contrast
i2cdata[6] = 0x9f; // Brightness
i2cdata[7] = 0xCF; // Sharpness (default 0xC6)
i2cdata[8] = 0x00; // Reserved
i2cdata[9] = 0x00; // Reserved
i2cdata[10] = 0x00; // Reserved
i2cdata[11] = 0x00; // Reserved
i2cdata[12] = 0x20; // AWB - Blue
i2cdata[13] = 0x20; // AWB - Red
i2cdata[14] = 0x0D; // COMR
i2cdata[15] = 0x05; // COMS
i2cdata[16] = 0x9A; // AEC
i2cdata[17] = 0x01; // CLKRC
i2cdata[18] = 0x28; // COMA
i2cdata[19] = 0x01; // 0x01; // COMB
I2C_write(I2C0, 0x60, i2cdata, 20, SET_STOP_BIT_AFTER_WRITE);
i2cdata[0] = 0x20;
i2cdata[1] = 0x01; // COME
I2C_write(I2C0, 0x60, i2cdata, 2, SET_STOP_BIT_AFTER_WRITE);
i2cdata[0] = 0x28;
i2cdata[1] = 0x81; // COMH
I2C_write(I2C0, 0x60, i2cdata, 2, SET_STOP_BIT_AFTER_WRITE);
i2cdata[0] = 0x39;
// changed to PCLK always on.
i2cdata[1] = 0x00; //0x40; // COML
I2C_write(I2C0, 0x60, i2cdata, 2, SET_STOP_BIT_AFTER_WRITE);
VPIF_initReceive(VIDEO_CONN_CAMERA);
// PRU setup
EVMOMAPL138_lpscTransition(PSC0, DOMAIN0, LPSC_DMAX, PSC_ENABLE);
PRU_stop(PRU0);
PRU_reset(PRU0);
PRU_load(PRU0_PROG, PRUCode, sizeof(PRUCode)/sizeof(uint32_t));
PRU_reset(PRU0);
PRU_run(PRU0);
// VPIF (95) interrupt serviced by INT4
ICR = 0x010; // clear pending interrupts
IER |= 0x010; // enable interrupt on line
// PRU (6) interrupt serviced by INT6
ICR = 0x040; // clear pending interrupts
IER |= 0x040; // enable interrupt on line
pic_data = (int *)ADDR_VIDEO_DATA_BASE;
Image_data = (bgr *)(IMAGE_DATA_MEM);
Thres_Image = (unsigned char *)(THRES_IMAGE_MEM);
Linux_Image = (bgr *)(ADDR_VIDEO_DATA_BASE+LINUX_IMAGE_OFFSET);
LCD_Image = (bgr *)(ADDR_VIDEO_DATA_BASE+LCD_IMAGE_OFFSET);
ptrshrdmem = (sharedmemstruct *)SHARED_MEM;
while (CHKBIT(VPIF->INTSTAT,INT_FRAME_CH1) == 0) {}
SETBIT(VPIF->INTSTATCLR, INT_FRAME_CH1);
}
//-----------------------------------------------------------------------------
// \brief initialize the given spi port.
//
// \param spi_regs_t *spi - pointer to reg struct for the desired spi port.
//
// \param spi_config_t *in_config - desired spi configuration.
//
// \return uint32_t
// ERR_NO_ERROR - everything is ok...spi ready to use.
// ERR_INIT_FAIL - something happened during initialization.
//-----------------------------------------------------------------------------
uint32_t SPI_init(spi_regs_t *spi, spi_config_t *in_config)
{
uint32_t rtn = ERR_INIT_FAIL;
// enable the psc and config pinmux for the given spi port.
switch ((uint32_t)spi)
{
case SPI0_REG_BASE:
EVMOMAPL138_lpscTransition(PSC0, DOMAIN0, LPSC_SPI0, PSC_ENABLE);
EVMOMAPL138_pinmuxConfig(PINMUX_SPI0_REG_0, PINMUX_SPI0_MASK_0, PINMUX_SPI0_VAL_0);
EVMOMAPL138_pinmuxConfig(PINMUX_SPI0_REG_1, PINMUX_SPI0_MASK_1, PINMUX_SPI0_VAL_1);
break;
case SPI1_REG_BASE:
EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_SPI1, PSC_ENABLE);
EVMOMAPL138_pinmuxConfig(PINMUX_SPI1_REG, PINMUX_SPI1_MASK, PINMUX_SPI1_VAL);
break;
default:
return (ERR_INIT_FAIL);
}
if (in_config != NULL)
{
uint32_t prescaler;
// reset spi port.
spi->SPIGCR0 = 0;
USTIMER_delay(5);
SETBIT(spi->SPIGCR0, RESET);
// config master/slave mode.
if (SPI_MODE_MASTER == in_config->mode)
{
// set clkmod and master for master mode.
spi->SPIGCR1 = CLKMOD | MASTER;
}
else if (SPI_MODE_SLAVE == in_config->mode)
{
// clear spigcr1 for slave mode.
spi->SPIGCR1 = 0;
}
else
{
return (ERR_INIT_FAIL);
}
// config pin options.
switch (in_config->pin_option)
{
case SPI_3PIN:
// enable spi SOMI, SIMO, and CLK.
spi->SPIPC0 = SOMI | SIMO | CLK;
// config SCS0 as gpio output.
SETBIT(spi->SPIPC1, SCS0);
break;
case SPI_4PIN_CS:
// enable spi SOMI, SIMO, CLK, and SCS0.
spi->SPIPC0 = SOMI | SIMO | CLK | SCS0;
break;
case SPI_4PIN_EN:
// enable spi SOMI, SIMO, CLK, and ENA.
spi->SPIPC0 = SOMI | SIMO | CLK | ENA;
break;
case SPI_5PIN:
// enable spi SOMI, SIMO, CLK, SCS0, and ENA.
spi->SPIPC0 = SOMI | SIMO | CLK | ENA | SCS0;
break;
default:
return (ERR_INIT_FAIL);
}
// config the cs active...high or low.
spi->SPIDEF = 0;
if (SPI_CS_ACTIVE_LOW == in_config->cs_active)
{
// clear csnr for active low and set cs default to 1.
spi->SPIDAT1 = 0;
SETBIT(spi->SPIDEF, CSDEF0);
}
else if (SPI_CS_ACTIVE_HIGH == in_config->cs_active)
{
// set csnr for active high and set cs default to 0.
spi->SPIDAT1 = 0;
SETBIT(spi->SPIDAT1, CSNR);
}
else
{
return (ERR_INIT_FAIL);
}
// config spi direction, polarity, and phase.
spi->SPIFMT0 = 0;
if (SPI_SHIFT_LSB == in_config->shift_dir)
{
SETBIT(spi->SPIFMT0, SHIFTDIR);
}
if (in_config->polarity)
{
SETBIT(spi->SPIFMT0, POLARITY);
}
if (in_config->phase)
{
SETBIT(spi->SPIFMT0, PHASE);
}
// set the prescaler and character length.
prescaler = (((SYSCLOCK2_HZ / in_config->freq) - 1) & 0xFF);
#ifdef DEBUG
printf("desired spi freq: %u\r\n", in_config->freq);
printf("spi sysclock: %u\r\n", SYSCLOCK2_HZ);
printf("prescaler set to: %u\r\n", prescaler);
#endif
SETBIT(spi->SPIFMT0, (prescaler << SHIFT_PRESCALE));
SETBIT(spi->SPIFMT0, (DEFAULT_CHAR_LEN << SHIFT_CHARLEN));
spi->SPIDELAY = (8 << 24) | (8 << 16);
// disable interrupts.
spi->SPIINT = 0x00;
spi->SPILVL = 0x00;
// enable spi.
SETBIT(spi->SPIGCR1, ENABLE);
rtn = ERR_NO_ERROR;
}
return (rtn);
}
//----------------------------------------------------------------------------
// \brief Configure the USB module for OTG mode.
//
// \return none.
//-----------------------------------------------------------------------------
void USB_OTG_init()
{
uint16_t I;
// **************************************************************************
// Configure DRVVBUS Pin to be used for USB
// **************************************************************************
// MAKE SURE WRITE ACCESS KEY IS INITIALIZED PRIOR TO ACCESSING ANY OF THE
// BOOTCFG REGISTERS.
//SYSCONFIG->KICKR[0] = KICK0R_UNLOCK;
//SYSCONFIG->KICKR[1] = KICK1R_UNLOCK;
/* CONFIGURE THE DRVVBUS PIN HERE.*/
/* See your device-specific System Reference Guide for more information on how to set up the
pinmux. */
// Power up the USB HW.
EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_USB0, PSC_ENABLE);
// Reset the USB controller:
USB_OTG->CTRLR |= 0x00000001;
//Wait until controller is finished with Reset. When done, it will clear the RESET bit field.
while ((USB_OTG->CTRLR & 0x1) == 1);
// RESET: Hold PHY in Reset
SYSCONFIG->CFGCHIP[2] |= 0x00008000; // Hold PHY in Reset
// Drive Reset for few clock cycles
for (I=0; I < 50; I++);
// RESET: Release PHY from Reset
SYSCONFIG->CFGCHIP[2] &= 0xFFFF7FFF; // Release PHY from Reset
/* Configure PHY with the Desired Operation */
// OTGMODE
SYSCONFIG->CFGCHIP[2] &= 0xFFFF9FFF; // 00= > Do Not Override PHY Values
//SYSCONFIG->CFGCHIP[2] |= 0x00002000; // 11= > Override PHY Values, force host, VBUS low
// PHYPWDN
SYSCONFIG->CFGCHIP[2] &= 0xFFFFFBFF; // 1/0 = > PowerdDown/ NormalOperation
// OTGPWRDN
SYSCONFIG->CFGCHIP[2] &= 0xFFFFFDFF; // 1/0 = > PowerDown/ NormalOperation
// DATAPOL
SYSCONFIG->CFGCHIP[2] |= 0x00000100; // 1/0 = > Normal/ Reversed
// SESNDEN
SYSCONFIG->CFGCHIP[2] |= 0x00000020; // 1/0 = > NormalOperation/ SessionEnd
// VBDTCTEN
SYSCONFIG->CFGCHIP[2] |= 0x00000010; // 1/0 = > VBUS Comparator Enable/ Disable
/* Configure PHY PLL use and Select Source */
// REF_FREQ[3:0]
SYSCONFIG->CFGCHIP[2] |= 0x00000002; // 0010b = > 24MHz Input Source
// USB2PHYCLKMUX: Select External Source
SYSCONFIG->CFGCHIP[2] &= 0xFFFFF7FF; // 1/0 = > Internal/External(Pin)
// PHY_PLLON: On Simulation PHY PLL is OFF
SYSCONFIG->CFGCHIP[2] |= 0x00000040; // 1/0 = > On/ Off
/* Wait Until PHY Clock is Good */
while ((SYSCONFIG->CFGCHIP[2] & 0x00020000) == 0); // Wait Until PHY Clock is Good.
#ifndef HS_ENABLE
// Disable high-speed
//CSL_FINS(USB_OTG->POWER,USB_OTG_POWER_HSEN,0);
USB_OTG->POWER &= ~USB_OTG_POWER_HSEN;
#else
// Enable high-speed
//CSL_FINS(usbRegs->POWER,USB_OTG_POWER_HSEN,1);
USB_OTG->POWER |= USB_OTG_POWER_HSEN;
#endif
// Enable Interrupts
// Enable interrupts in OTG block
USB_OTG->CTRLR &= 0xFFFFFFF7; // Enable PDR2.0 Interrupt
USB_OTG->INTRTXE = 0x1F; // Enable All Core Tx Endpoints Interrupts + EP0 Tx/Rx interrupt
USB_OTG->INTRRXE = 0x1E; // Enable All Core Rx Endpoints Interrupts
// Enable all interrupts in OTG block
USB_OTG->INTMSKSETR = 0x01FF1E1F;
// Enable all USB interrupts in MUSBMHDRC
USB_OTG->INTRUSBE = 0xFF;
// Enable SUSPENDM so that suspend can be seen UTMI signal
//CSL_FINS(USB_OTG->POWER,USB_OTG_POWER_ENSUSPM,1);
USB_OTG->POWER |= USB_OTG_POWER_ENSUSPM;
//Clear all pending interrupts
USB_OTG->INTCLRR = USB_OTG->INTSRCR;
// Start a session
//CSL_FINS(USB_OTG->DEVCTL,USB_OTG_DEVCTL_SESSION,1);
//USB_OTG->DEVCTL |= USB_OTG_DEVCTL_SESSION;
}
Void main()
{
int i = 0;
// unlock the system config registers.
SYSCONFIG->KICKR[0] = KICK0R_UNLOCK;
SYSCONFIG->KICKR[1] = KICK1R_UNLOCK;
SYSCONFIG1->PUPD_SEL |= 0x10000000; // change pin group 28 to pullup for GP7[12/13] (LCD switches)
// Initially set McBSP1 pins as GPIO ins
CLRBIT(SYSCONFIG->PINMUX[1], 0xFFFFFFFF);
SETBIT(SYSCONFIG->PINMUX[1], 0x88888880); // This is enabling the McBSP1 pins
CLRBIT(SYSCONFIG->PINMUX[16], 0xFFFF0000);
SETBIT(SYSCONFIG->PINMUX[16], 0x88880000); // setup GP7.8 through GP7.13
CLRBIT(SYSCONFIG->PINMUX[17], 0x000000FF);
SETBIT(SYSCONFIG->PINMUX[17], 0x00000088); // setup GP7.8 through GP7.13
//Rick added for LCD DMA flagging test
GPIO_setDir(GPIO_BANK0, GPIO_PIN8, GPIO_OUTPUT);
GPIO_setOutput(GPIO_BANK0, GPIO_PIN8, OUTPUT_HIGH);
GPIO_setDir(GPIO_BANK0, GPIO_PIN0, GPIO_INPUT);
GPIO_setDir(GPIO_BANK0, GPIO_PIN1, GPIO_INPUT);
GPIO_setDir(GPIO_BANK0, GPIO_PIN2, GPIO_INPUT);
GPIO_setDir(GPIO_BANK0, GPIO_PIN3, GPIO_INPUT);
GPIO_setDir(GPIO_BANK0, GPIO_PIN4, GPIO_INPUT);
GPIO_setDir(GPIO_BANK0, GPIO_PIN5, GPIO_INPUT);
GPIO_setDir(GPIO_BANK0, GPIO_PIN6, GPIO_INPUT);
GPIO_setDir(GPIO_BANK7, GPIO_PIN8, GPIO_OUTPUT);
GPIO_setDir(GPIO_BANK7, GPIO_PIN9, GPIO_OUTPUT);
GPIO_setDir(GPIO_BANK7, GPIO_PIN10, GPIO_OUTPUT);
GPIO_setDir(GPIO_BANK7, GPIO_PIN11, GPIO_OUTPUT);
GPIO_setDir(GPIO_BANK7, GPIO_PIN12, GPIO_INPUT);
GPIO_setDir(GPIO_BANK7, GPIO_PIN13, GPIO_INPUT);
GPIO_setOutput(GPIO_BANK7, GPIO_PIN8, OUTPUT_HIGH);
GPIO_setOutput(GPIO_BANK7, GPIO_PIN9, OUTPUT_HIGH);
GPIO_setOutput(GPIO_BANK7, GPIO_PIN10, OUTPUT_HIGH);
GPIO_setOutput(GPIO_BANK7, GPIO_PIN11, OUTPUT_HIGH);
CLRBIT(SYSCONFIG->PINMUX[13], 0xFFFFFFFF);
SETBIT(SYSCONFIG->PINMUX[13], 0x88888811); //Set GPIO 6.8-13 to GPIOs and IMPORTANT Sets GP6[15] to /RESETOUT used by PHY, GP6[14] CLKOUT appears unconnected
#warn GP6.15 is also connected to CAMERA RESET This is a Bug in my board design Need to change Camera Reset to different IO.
GPIO_setDir(GPIO_BANK6, GPIO_PIN8, GPIO_OUTPUT);
GPIO_setDir(GPIO_BANK6, GPIO_PIN9, GPIO_OUTPUT);
GPIO_setDir(GPIO_BANK6, GPIO_PIN10, GPIO_OUTPUT);
GPIO_setDir(GPIO_BANK6, GPIO_PIN11, GPIO_OUTPUT);
GPIO_setDir(GPIO_BANK6, GPIO_PIN12, GPIO_OUTPUT);
GPIO_setDir(GPIO_BANK6, GPIO_PIN13, GPIO_INPUT);
// on power up wait until Linux has initialized Timer1
while ((T1_TGCR & 0x7) != 0x7) {
for (index=0;index<50000;index++) {} // small delay before checking again
}
USTIMER_init();
// Turn on McBSP1
EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_MCBSP1, PSC_ENABLE);
// If Linux has already booted It sets a flag so no need to delay
if ( GET_ISLINUX_BOOTED == 0) {
USTIMER_delay(4*DELAY_1_SEC); // delay allowing Linux to partially boot before continuing with DSP code
}
// init the us timer and i2c for all to use.
I2C_init(I2C0, I2C_CLK_100K);
init_ColorVision();
init_LCD_mem(); // added rick
EVTCLR0 = 0xFFFFFFFF;
EVTCLR1 = 0xFFFFFFFF;
EVTCLR2 = 0xFFFFFFFF;
EVTCLR3 = 0xFFFFFFFF;
init_DMA();
init_McBSP();
init_LADAR();
CLRBIT(SYSCONFIG->PINMUX[1], 0xFFFFFFFF);
SETBIT(SYSCONFIG->PINMUX[1], 0x22222220); // This is enabling the McBSP1 pins
CLRBIT(SYSCONFIG->PINMUX[5], 0x00FF0FFF);
SETBIT(SYSCONFIG->PINMUX[5], 0x00110111); // This is enabling SPI pins
CLRBIT(SYSCONFIG->PINMUX[16], 0xFFFF0000);
SETBIT(SYSCONFIG->PINMUX[16], 0x88880000); // setup GP7.8 through GP7.13
CLRBIT(SYSCONFIG->PINMUX[17], 0x000000FF);
SETBIT(SYSCONFIG->PINMUX[17], 0x00000088); // setup GP7.8 through GP7.13
init_LCD();
LADARps.x = 3.5/12; // 3.5/12 for front mounting
LADARps.y = 0;
LADARps.theta = 1; // not inverted
OPTITRACKps.x = 0;
OPTITRACKps.y = 0;
OPTITRACKps.theta = 0;
for(i = 0;i<LADAR_MAX_DATA_SIZE;i++)
{ LADARdistance[i] = LADAR_MAX_READING; } //initialize all readings to max value.
// ROBOTps will be updated by Optitrack during gyro calibration
// TODO: specify the starting position of the robot
ROBOTps.x = 0; //the estimate in array form (useful for matrix operations)
ROBOTps.y = 0;
ROBOTps.theta = 0; // was -PI: need to flip OT ground plane to fix this
// flag pins
GPIO_setDir(IMAGE_TO_LINUX_BANK, IMAGE_TO_LINUX_FLAG, GPIO_OUTPUT);
GPIO_setDir(OPTITRACKDATA_FROM_LINUX_BANK, OPTITRACKDATA_FROM_LINUX_FLAG, GPIO_OUTPUT);
GPIO_setDir(DATA_TO_LINUX_BANK, DATA_TO_LINUX_FLAG, GPIO_OUTPUT);
GPIO_setDir(DATA_FROM_LINUX_BANK, DATA_FROM_LINUX_FLAG, GPIO_OUTPUT);
GPIO_setDir(DATAFORFILE_TO_LINUX_BANK, DATAFORFILE_TO_LINUX_FLAG, GPIO_OUTPUT);
GPIO_setDir(LVDATA_FROM_LINUX_BANK, LVDATA_FROM_LINUX_FLAG, GPIO_OUTPUT);
GPIO_setDir(LVDATA_TO_LINUX_BANK, LVDATA_TO_LINUX_FLAG, GPIO_OUTPUT);
CLR_OPTITRACKDATA_FROM_LINUX; // Clear = tell linux DSP is ready for new Opitrack data
CLR_DATA_FROM_LINUX; // Clear = tell linux that DSP is ready for new data
CLR_DATAFORFILE_TO_LINUX; // Clear = linux not requesting data
SET_DATA_TO_LINUX; // Set = put float array data into shared memory for linux
SET_IMAGE_TO_LINUX; // Set = put image into shared memory for linux
CLR_LVDATA_FROM_LINUX; // Clear = tell linux that DSP is ready for new LV data
SET_LVDATA_TO_LINUX; // Set = put LV char data into shared memory for linux
// clear all possible EDMA
EDMA3_0_Regs->SHADOW[1].ICR = 0xFFFFFFFF;
// Add your init code here
}