void EZUSB_Delay(WORD ms)
{
//
// Adjust the delay based on the CPU clock
// EZUSB_Delay1ms() assumes a 24MHz clock
//
if ((CPUCS & bmCLKSPD) == 0) // 12Mhz
ms = (ms + 1) / 2; // Round up before dividing so we can accept 1.
else if ((CPUCS & bmCLKSPD) == bmCLKSPD1) // 48Mhz
ms = ms * 2;
while(ms--)
EZUSB_Delay1ms();
}
/* ******************************************************************** */
void Check_Bootloader(void)
{
// reinit all chip
TD_Init();
// just to allow send/receive from midi and usb inputs
z8_board_fully_updated_from_ez0_bit = 1;
// Init i2c bus for eeprom ez upgrade
//EZUSB_InitI2C();
// update bootloading flags and state
bootloader_state = SEND_IDENTITY_SYSEX;
// First send the Bootloader identity sysex acknoledge to midi & usb out
SendIdentityBootLoader();
must_program_z8 = FALSE;
// The data firmware upgrade starts here
bootloader_state = WAIT_EZ_FW_DATA;
// Now Wait for the ez firmware data sysexs
WaitNextBootLoaderState(bootloader_state);
if(must_program_z8)
{
// Release Z8 board reset line
Z8_RESET_PORT_OUT |= Z8_RESET_PIN;
// wait por
EZUSB_Delay(200);
// disable rx1
SCON1 = 0x40; /* SCON1: mode 1, 8-bit UART, disable rcvr */
// tx1 is now dedicated to z8 dbg pin
OCD_EN_PORT_OUT |= OCD_EN_PIN;
// set z8 dbg pin low
TX1_TO_Z8_DBG_PORT_OUT &= ~TX1_TO_Z8_DBG_PIN;
// wait 2sec
EZUSB_Delay(2000);
// set z8 dbg pin high
TX1_TO_Z8_DBG_PORT_OUT |= TX1_TO_Z8_DBG_PIN;
// turn on tx1 and rx1 (serial to/from z8)
PORTBCFG |= 0x0C;
// send ocd first byte so the z8 autobaudrate the serial line
Send_To_Serial_Z8(OCD_FIRST_BYTE);
EZUSB_Delay1ms();
// place the z8 chip in ocd mode
Send_To_Serial_Z8(OCD_WRITE_CTR_REG_CMD);
Send_To_Serial_Z8(OCD_CTR_REG_DBGMODE);
EZUSB_Delay(100);
InitFlashFrqAndUnlock();
// selet flash page 0
WriteSingleRegOCD(OCD_FLASH_SELECT_PAGE, 0x00);
// launch a mass erase
WriteSingleRegOCD(OCD_FLASH_CTR_REG_ADD, OCD_FLASH_MASS_ERASE);
EZUSB_Delay(Z8_ERASING_TIME);
InitFlashFrqAndUnlock();
// Now Wait for the z8 firmware data sysexs
WaitNextBootLoaderState(bootloader_state);
EZUSB_Delay(50);
// relock the flash controller
WriteSingleRegOCD(OCD_FLASH_CTR_REG_ADD, OCD_FLASH_CTR_REG_RESET);
/*
///////////////////// Z8 CRC CHECKS /////////////////////////////////
// V1.4 it is now time to verify Z8 programmed flash
bootloader_state = VERIFY_Z8_CRC;
// V1.4 Read the Z8 memory CRC and compare to calculated CRC
Send_To_Serial_Z8(OCD_READ_FLASH_CRC);
// V1.4 required time is 65536 * 1/(20MHz)
EZUSB_Delay(50);
// V1.4 the serial port should now have received the z8 internal CRC in buffer 0 to 3
// Send this CRC to host
Serial_In_From_Z8.buffer[7] = Serial_In_From_Z8.buffer[0];
Serial_In_From_Z8.buffer[8] = Serial_In_From_Z8.buffer[1];
Serial_In_From_Z8.end_index = WID_SYX_HEADER_SIZE + 3 + 1;
AssignWidSysexHeader();
// send ack firmware
Serial_In_From_Z8.buffer[6] = FRAME_IS_FIRMWARE_OR_PURE_MIDI | sysex_direction_sysxid0 | prog_upload_sysxid0;
// send eox
Serial_In_From_Z8.buffer[9] = MIDI_EOX;
SendDispatchFwSysex();
///////////////////// END Z8 CRC CHECKS /////////////////////////////////
*/
// exit z8 ocd mode
OCD_EN_PORT_OUT &= ~OCD_EN_PIN;
// exit z8 ocd mode
Z8_RESET_PORT_OUT &= ~Z8_RESET_PIN;
}
// Now finish with a soft reset
// SoftReset();
while(1)
{
Check_Usb();
Ep2out_Function();
}
}
void DSLogic_Poll(void)
{
if (cfg_init && EP0BCL == sizeof(struct cmd_cfg_count))
{
cfg_init = FALSE;
init_config_intf();
FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
SYNCDELAY;
FIFORESET = 0x02; // reset EP2 FIFO
SYNCDELAY;
FIFORESET = 0x06; // reset EP6 FIFO
SYNCDELAY;
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
SYNCDELAY;
EP2FIFOCFG = 0x00; // allow core to see zero to one transition of auto out bit
SYNCDELAY;
EP2FIFOCFG = 0x10; // auto out mode, disable PKTEND zero length send, word ops
SYNCDELAY;
EP6FIFOCFG = 0x08; // auto in mode, disable PKTEND zero length send, word ops
SYNCDELAY;
GPIFIDLECTL &= 0xFB; //PROG_B signal low
EZUSB_Delay1ms(); //PROG_B signal kept asserted for 1 ms
GPIFIDLECTL |= 0x04; //PROG_B signal high
SYNCDELAY;
// setup transaction count
GPIFTCB0 = ((const struct cmd_cfg_count *)EP0BUF)->byte0;
SYNCDELAY;
GPIFTCB1 = ((const struct cmd_cfg_count *)EP0BUF)->byte1;
SYNCDELAY;
GPIFTCB2 = ((const struct cmd_cfg_count *)EP0BUF)->byte2;
SYNCDELAY;
cfg_enable = TRUE;
}
if (cfg_enable && (GPIFTRIG & 0x80)) // if GPIF interface IDLE
{
if ( (EP24FIFOFLGS & 0x01) && (GPIFREADYSTAT & 0x01)) {
// if there's a packet in the peripheral domain for EP2
// and FPGA is ready to receive the configuration bitstream
IFCONFIG = 0xA6;
// 7 IFCLKSRC=1 , FIFOs executes on internal clk source
// 6 xMHz=0 , 30MHz internal clk rate
// 5 IFCLKOE=1 , Drive IFCLK pin signal at 30MHz
// 4 IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
// 3 ASYNC=0 , master samples asynchronous
// 2 GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
// 1:0 IFCFG=10, FX2 in GPIF master mode
SYNCDELAY;
//delay(1); //avoid CSI_B deasserted during sync words
GPIFTRIG = GPIFTRIGWR | GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ); // poll GPIFTRIG.7 GPIF Done bit
SYNCDELAY;
cfg_enable= FALSE; //end of configuration
/* Put the FX2 into GPIF master mode and setup the GPIF. */
//init_capture_intf();
if (GPIFREADYSTAT & 0x02) { // FPGA Configure Done
IOA |= 0x01;
IOA &= 0xf5;
EZUSB_Delay1ms();
IOA |= 0x08;
} else {
IOA &= 0xfc;
}
}
}
switch(command)
{
case CMD_START:
{
if ((EP0CS & bmEPBUSY) != 0)
break;
if (EP0BCL == sizeof(struct cmd_start))
{
if ((*(BYTE *)EP0BUF) & CMD_START_FLAGS_STOP)
stop_capture();
else
start_capture();
}
command = 0;
break;
}
case CMD_SETTING:
{
if ((EP0CS & bmEPBUSY) != 0)
break;
if (EP0BCL == sizeof(struct cmd_setting_count))
{
GPIFABORT = 0xff;
SYNCDELAY;
EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word operation
SYNCDELAY;
setting_count_b0 = ((const struct cmd_setting_count *)EP0BUF)->byte0;
setting_count_b1 = ((const struct cmd_setting_count *)EP0BUF)->byte1;
setting_count_b2 = ((const struct cmd_setting_count *)EP0BUF)->byte2;
set_enable = TRUE;
}
command = 0;
break;
}
case CMD_CONTROL:
{
if ((EP0CS & bmEPBUSY) != 0)
break;
if (EP0BCL == sizeof(struct cmd_control))
{
dsoConfig[0] = ((const struct cmd_control *)EP0BUF)->byte0;
dsoConfig[1] = ((const struct cmd_control *)EP0BUF)->byte1;
dsoConfig[2] = ((const struct cmd_control *)EP0BUF)->byte2;
dsoConfig[3] = ((const struct cmd_control *)EP0BUF)->byte3;
set_dso_ctrl = TRUE;
}
command = 0;
break;
}
default:
command = 0;
break;
}
if (set_enable && (GPIFTRIG & 0x80)) { // if GPIF interface IDLE
if (!(EP24FIFOFLGS & 0x02)) {
SYNCDELAY;
GPIFTCB2 = setting_count_b2;
SYNCDELAY;
GPIFTCB1 = setting_count_b1; // fpga setting count
SYNCDELAY;
GPIFTCB0 = setting_count_b0;
SYNCDELAY;
GPIFTRIG = GPIFTRIGWR | GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ); // poll GPIFTRIG.7 GPIF Done bit
SYNCDELAY;
set_enable= FALSE; //end of configuration
/* Put the FX2 into GPIF master mode and setup the GPIF. */
init_capture_intf();
}
}
if (set_dso_ctrl) {
EZUSB_WriteI2C(0x51, 4, dsoConfig);
set_dso_ctrl = FALSE;
}
poll_intf();
}
