/* Initilize dm9000 board
*/
int
eth_init(bd_t * bd)
{
int i, oft;
DM9000_DBG("eth_init()\n");
/* RESET device */
dm9000_reset();
dm9000_probe();
/* NIC Type: FASTETHER, HOMERUN, LONGRUN */
identify_nic();
/* GPIO0 on pre-activate PHY */
DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
/* Set PHY */
set_PHY_mode();
/* Program operating register */
DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */
DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */
DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
DM9000_iow(DM9000_SMCR, 0); /* Special Mode */
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
/* Set Node address */
//HJ_start /* www.embedsky.net */
char *tmp = getenv("ethaddr");
char *end;
for (i = 0; i < 6; i++)
{
bd->bi_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
if(tmp)
tmp = (*end) ? end+1 : end;
}
//HJ_end /* www.embedsky.net */
printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_iow(oft, bd->bi_enetaddr[i]);
for (i = 0, oft = 0x16; i < 8; i++, oft++)
DM9000_iow(oft, 0xff);
/* read back mac, just to be sure */
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_DBG("%02x:", DM9000_ior(oft));
DM9000_DBG("\n");
/* Activate DM9000 */
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
return 0;
}
/* Initilize dm9000 board
*/
int
eth_init(bd_t * bd)
{
int i, oft, lnk;
DM9000_DBG("eth_init()\n");
/* RESET device */
dm9000_reset();
dm9000_probe();
/* NIC Type: FASTETHER, HOMERUN, LONGRUN */
identify_nic();
/* GPIO0 on pre-activate PHY */
DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
/* Set PHY */
set_PHY_mode();
/* Program operating register */
DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */
DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */
DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
DM9000_iow(DM9000_SMCR, 0); /* Special Mode */
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
/* Set Node address */
// for (i = 0; i < 6; i++) //raymanfeng-
// ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_iow(oft, bd->bi_enetaddr[i]);
for (i = 0, oft = 0x16; i < 8; i++, oft++)
DM9000_iow(oft, 0xff);
/* read back mac, just to be sure */
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_DBG("%02x:", DM9000_ior(oft));
DM9000_DBG("\n");
/* Activate DM9000 */
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
/* //raymanfeng-
i = 0;
while (!(phy_read(1) & 0x20)) { // autonegation complete bit
udelay(1000);
i++;
if (i == 10000) {
printf("could not establish link\n");
return 0;
}
}
// see what we've got
lnk = phy_read(17) >> 12;
printf("operating at ");
switch (lnk) {
case 1:
printf("10M half duplex ");
break;
case 2:
printf("10M full duplex ");
break;
case 4:
printf("100M half duplex ");
break;
case 8:
printf("100M full duplex ");
break;
default:
printf("unknown: %d ", lnk);
break;
}
printf("mode\n");
*/
return 0;
}
