DIB dq_dib[] = {
{ &dqdio, DQD },
{ &dqcio, DQC }
};
#define dqd_dib dq_dib[0]
#define dqc_dib dq_dib[1]
UNIT dqd_unit = { UDATA (&dqd_svc, 0, 0) };
REG dqd_reg[] = {
{ ORDATA (IBUF, dqd_ibuf, 16) },
{ ORDATA (OBUF, dqd_obuf, 16) },
{ BRDATA (DBUF, dqxb, 8, 16, DQ_NUMWD) },
{ DRDATA (BPTR, dq_ptr, DQ_N_NUMWD) },
{ FLDATA (CMD, dqd.command, 0) },
{ FLDATA (CTL, dqd.control, 0) },
{ FLDATA (FLG, dqd.flag, 0) },
{ FLDATA (FBF, dqd.flagbuf, 0) },
{ FLDATA (XFER, dqd_xfer, 0) },
{ FLDATA (WVAL, dqd_wval, 0) },
{ ORDATA (SC, dqd_dib.select_code, 6), REG_HRO },
{ ORDATA (DEVNO, dqd_dib.select_code, 6), REG_HRO },
{ NULL }
};
MTAB dqd_mod[] = {
{ MTAB_XTD | MTAB_VDV, 1, "SC", "SC", &hp_setsc, &hp_showsc, &dqd_dev },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "DEVNO", "DEVNO", &hp_setdev, &hp_showdev, &dqd_dev },
{ 0 }
};
ptr_dev PTR device descriptor
ptr_unit PTR unit descriptor
ptr_mod PTR modifiers
ptr_reg PTR register list
*/
DIB ptr_dib = { &ptrio, PTR };
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
REG ptr_reg[] = {
{ ORDATA (BUF, ptr_unit.buf, 8) },
{ FLDATA (CTL, ptr.control, 0) },
{ FLDATA (FLG, ptr.flag, 0) },
{ FLDATA (FBF, ptr.flagbuf, 0) },
{ DRDATA (TRLCTR, ptr_trlcnt, 8), REG_HRO },
{ DRDATA (TRLLIM, ptr_trllim, 8), PV_LEFT },
{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ ORDATA (SC, ptr_dib.select_code, 6), REG_HRO },
{ ORDATA (DEVNO, ptr_dib.select_code, 6), REG_HRO },
{ NULL }
};
MTAB ptr_mod[] = {
{ UNIT_DIAG, UNIT_DIAG, "diagnostic mode", "DIAG", NULL },
{ UNIT_DIAG, 0, "reader mode", "READER", NULL },
void dcs_scan_next (t_bool unlk);
/* DCS data structures
dcs_dev DCS device descriptor
dcs_unit DCS unit descriptor
dcs_reg DCS register list
dcs_mod DCS modifiers list
*/
UNIT dcs_unit = { UDATA (&dcsi_svc, UNIT_ATTABLE, 0) };
REG dcs_reg[] = {
{ BRDATA (BUF, dcs_buf, 8, 8, DCS_LINES) },
{ BRDATA (FLAGS, dcs_flg, 8, 1, DCS_LINES) },
{ FLDATA (SCNF, iosta, IOS_V_DCS) },
{ ORDATA (SCAN, dcs_scan, 5) },
{ ORDATA (SEND, dcs_send, 5) },
{ DRDATA (SBSLVL, dcs_sbs, 4), REG_HRO },
{ NULL }
};
MTAB dcs_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "SBSLVL", "SBSLVL",
&dev_set_sbs, &dev_show_sbs, (void *) &dcs_sbs },
{ MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
&dcs_vlines, &tmxr_show_lines, (void *) &dcs_desc },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, (void *) &dcs_desc },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &dcs_desc },
int32 bcd2asc (int32 c, UNIT *uptr);
char colbin_to_bcd (uint32 cb);
/* Card reader data structures
cdr_dev CDR descriptor
cdr_unit CDR unit descriptor
cdr_reg CDR register list
*/
UNIT cdr_unit = {
UDATA (&cdr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE+UNIT_TEXT, 0), 100
};
REG cdr_reg[] = {
{ FLDATA (LAST, ind[IN_LST], 0) },
{ FLDATA (ERR, ind[IN_READ], 0) },
{ FLDATA (S1, s1sel, 0) },
{ FLDATA (S2, s2sel, 0) },
{ DRDATA (POS, cdr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, cdr_unit.wait, 24), PV_LEFT },
{ BRDATA (BUF, rbuf, 8, 8, CDR_WIDTH) },
{ NULL }
};
DEVICE cdr_dev = {
"CDR", &cdr_unit, cdr_reg, NULL,
1, 10, 31, 1, 8, 7,
NULL, NULL, &cd_reset,
&cdr_boot, &cdr_attach, NULL
};
{ GRDATA (CADL, cmdadl, DEV_RDX, 16, 0) },
{ GRDATA (CADH, cmdadh, DEV_RDX, 16, 0) },
{ GRDATA (CLNT, cmdlnt, DEV_RDX, 16, 0) },
{ GRDATA (MHDR, msghdr, DEV_RDX, 16, 0) },
{ GRDATA (MRFC, msgrfc, DEV_RDX, 16, 0) },
{ GRDATA (MXS0, msgxs0, DEV_RDX, 16, 0) },
{ GRDATA (MXS1, msgxs1, DEV_RDX, 16, 0) },
{ GRDATA (MXS2, msgxs2, DEV_RDX, 16, 0) },
{ GRDATA (MXS3, msgxs3, DEV_RDX, 16, 0) },
{ GRDATA (MSX4, msgxs4, DEV_RDX, 16, 0) },
{ GRDATA (WADL, wchadl, DEV_RDX, 16, 0) },
{ GRDATA (WADH, wchadh, DEV_RDX, 16, 0) },
{ GRDATA (WLNT, wchlnt, DEV_RDX, 16, 0) },
{ GRDATA (WOPT, wchopt, DEV_RDX, 16, 0) },
{ GRDATA (WXOPT, wchxopt, DEV_RDX, 16, 0) },
{ FLDATA (INT, IREQ (TS), INT_V_TS) },
{ FLDATA (ATTN, ts_qatn, 0) },
{ FLDATA (BOOT, ts_bcmd, 0) },
{ FLDATA (OWNC, ts_ownc, 0) },
{ FLDATA (OWNM, ts_ownm, 0) },
{ DRDATA (TIME, ts_time, 24), PV_LEFT + REG_NZ },
{ DRDATA (POS, ts_unit.pos, T_ADDR_W), PV_LEFT + REG_RO },
{ GRDATA (DEVADDR, ts_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, ts_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB ts_mod[] = {
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
ttix_unit TTIx unit descriptor
ttix_reg TTIx register list
ttix_mod TTIx modifiers list
*/
DIB ttix_dib = {
DEV_TTO1, 8, NULL,
{ &ttox, &ttix, &ttox, &ttix, &ttox, &ttix, &ttox, &ttix }
};
UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), KBD_POLL_WAIT };
REG ttix_reg[] = {
{ BRDATA (BUF, ttix_buf, 8, 8, TTX_MAXL) },
{ ORDATA (DONE, ttix_done, TTX_MAXL) },
{ FLDATA (INT, int_hwre[API_TTI1], INT_V_TTI1) },
{ DRDATA (TIME, ttix_unit.wait, 24), REG_NZ + PV_LEFT },
{ ORDATA (DEVNUM, ttix_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB ttix_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
&ttx_vlines, &tmxr_show_lines, (void *) &ttx_desc },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &ttx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
UNIT_ROABLE+(TYPE_5440 << UNIT_V_DTYPE), SIZE_5440) },
{ UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE+(TYPE_5440 << UNIT_V_DTYPE), SIZE_5440) }
};
REG dp_reg[] = {
{ HRDATA (CMD, dp_cmd, 3) },
{ HRDATA (STA, dp_sta, 8) },
{ HRDATA (BUF, dp_db, 8) },
{ HRDATA (PLAT, dp_plat, 1) },
{ HRDATA (HDSC, dp_hdsc, 6) },
{ HRDATA (CYL, dp_cyl, 9) },
{ HRDATA (SVUN, dp_svun, 8), REG_HIDDEN },
{ BRDATA (DBUF, dpxb, 16, 8, DP_NUMBY) },
{ HRDATA (DBPTR, dp_bptr, 9), REG_RO },
{ FLDATA (FIRST, dp_1st, 0) },
{ GRDATA (IREQ, int_req[l_DPC], 16, DP_NUMDR + 1, i_DPC) },
{ GRDATA (IENB, int_enb[l_DPC], 16, DP_NUMDR + 1, i_DPC) },
{ BRDATA (IARM, dpd_arm, 16, 1, DP_NUMDR) },
{ DRDATA (RTIME, dp_rtime, 0), PV_LEFT | REG_NZ },
{ DRDATA (STIME, dp_stime, 0), PV_LEFT | REG_NZ },
{ DRDATA (WTIME, dp_wtime, 0), PV_LEFT | REG_NZ },
{ URDATA (UCYL, dp_unit[0].CYL, 16, 9, 0,
DP_NUMDR, REG_RO) },
{ URDATA (UST, dp_unit[0].STD, 16, 8, 0,
DP_NUMDR, REG_RO) },
{ URDATA (CAPAC, dp_unit[0].capac, 10, T_ADDR_W, 0,
DP_NUMDR, PV_LEFT | REG_HRO) },
{ HRDATA (DEVNO, dp_dib.dno, 8), REG_HRO },
{ HRDATA (SELCH, dp_dib.sch, 2), REG_HRO },
{ NULL }
/* DR15 data structures
dr15_dev DR15 device descriptor
dr15_unit DR15 unit descriptor
dr15_reg DR15 register list
*/
DIB dr15_dib = { DEV_DR, 2 ,NULL, { &dr60, &dr61 } };
UNIT dr15_unit = {
UDATA (&dr15_svc, UNIT_FIX+UNIT_BINK+UNIT_ATTABLE, UC15_STATE_SIZE)
};
REG dr15_reg[] = {
{ ORDATA (TCBP, dr15_tcbp, ADDRSIZE) },
{ FLDATA (TCBACK, dr15_tcb_ack, 0) },
{ FLDATA (IE, dr15_ie, 0) },
{ ORDATA (REQ, dr15_int_req, 4) },
{ FLDATA (API0, int_hwre[API_DR0], INT_V_DR) },
{ FLDATA (API1, int_hwre[API_DR1], INT_V_DR) },
{ FLDATA (API2, int_hwre[API_DR2], INT_V_DR) },
{ FLDATA (API3, int_hwre[API_DR3], INT_V_DR) },
{ ORDATA (APIVEC0, api_vec[API_DR0][INT_V_DR], 7) },
{ ORDATA (APIVEC1, api_vec[API_DR1][INT_V_DR], 7) },
{ ORDATA (APIVEC2, api_vec[API_DR2][INT_V_DR], 7) },
{ ORDATA (APIVEC3, api_vec[API_DR3][INT_V_DR], 7) },
{ DRDATA (POLL, dr15_poll, 10), REG_NZ },
{ ORDATA (DEVNO, dr15_dib.dev, 6), REG_HRO },
{ NULL }
};
t_stat rtc_reset (DEVICE *dhsr);
int32 rtc_tps = 1000;
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
tti_mod TTI modifiers list
*/
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_KSR, 0), KBD_POLL_WAIT };
REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 8) },
{ FLDATA (IRDY, dev_done, INT_V_TTI) },
{ FLDATA (IENB, ISR, INT_V_TTI) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
{ 0 }
};
DEVICE tti_dev = {
/* LPT data structures
lpt_dev LPT device descriptor
lpt_unit LPT unit descriptor
lpt_reg LPT register list
*/
UNIT lpt_unit = {
UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 50)
};
REG lpt_reg[] = {
{ BRDATA (LBUF, lpt_buf, 8, 8, LPT_BSIZE + 1) },
{ DRDATA (BPTR, lpt_bptr, 8) },
{ HRDATA (PCTL, lpt_savctrl, 8) },
{ FLDATA (PRCHK, ind[IN_PRCHK], 0) },
{ FLDATA (PRCH9, ind[IN_PRCH9], 0) },
{ FLDATA (PRCH12, ind[IN_PRCH12], 0) },
{ FLDATA (PRBSY, ind[IN_PRBSY], 0) },
{ DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
{ BRDATA (CCT, cct, 8, 32, CCT_LNT) },
{ DRDATA (CCTP, cct_ptr, 8), PV_LEFT },
{ DRDATA (CCTL, cct_lnt, 8), REG_RO + PV_LEFT },
{ NULL }
};
DEVICE lpt_dev = {
"LPT", &lpt_unit, lpt_reg, NULL,
1, 10, 31, 1, 8, 7,
NULL, NULL, &lpt_reset,
NULL, &lpt_attach, NULL
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) },
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, RP_SIZE) }
};
REG rp_reg[] = {
{ ORDATA (STA, rp_sta, 18) },
{ ORDATA (STB, rp_stb, 18) },
{ ORDATA (DA, rp_da, 18) },
{ ORDATA (MA, rp_ma, 18) },
{ ORDATA (WC, rp_wc, 18) },
{ FLDATA (INT, int_hwre[API_RP], INT_V_RP) },
{ FLDATA (BUSY, rp_busy, 0) },
{ FLDATA (STOP_IOE, rp_stopioe, 0) },
{ DRDATA (STIME, rp_swait, 24), PV_LEFT },
{ DRDATA (RTIME, rp_rwait, 24), PV_LEFT },
{ ORDATA (DEVNO, rp_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB rp_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },
{ 0 }
};
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) },
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) },
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) },
{ UDATA (&rk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, RK_SIZE) }
};
REG rk_reg[] = {
{ ORDATA (RKSTA, rk_sta, 12) },
{ ORDATA (RKCMD, rk_cmd, 12) },
{ ORDATA (RKDA, rk_da, 12) },
{ ORDATA (RKMA, rk_ma, 12) },
{ FLDATA (BUSY, rk_busy, 0) },
{ FLDATA (INT, int_req, INT_V_RK) },
{ DRDATA (STIME, rk_swait, 24), PV_LEFT },
{ DRDATA (RTIME, rk_rwait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, rk_stopioe, 0) },
{ ORDATA (DEVNUM, rk_dib.dev, 6), REG_HRO },
{ NULL }
};
MTAB rk_mod[] = {
{ UNIT_HWLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_HWLK, UNIT_HWLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
&set_dev, &show_dev, NULL },
{ 0 }
};
mux_unit MUX unit descriptor
mux_reg MUX register list
mux_mod MUX modifiers list
*/
DIB mux_dib = { -1, DEV3_GMUX, 0, NULL, &mux };
UNIT mux_unit = { UDATA (&muxi_svc, UNIT_ATTABLE, 0), MUX_INIT_POLL };
REG mux_reg[] = {
{ BRDATA (STA, mux_sta, 8, 6, MUX_LINES) },
{ BRDATA (RBUF, mux_rbuf, 8, 8, MUX_LINES) },
{ BRDATA (XBUF, mux_xbuf, 8, 8, MUX_LINES) },
{ BRDATA (INT, mux_flags, 8, 1, MUX_SCANMAX) },
{ ORDATA (SCAN, mux_scan, 7) },
{ FLDATA (SLCK, mux_slck, 0) },
{ DRDATA (TPS, mux_tps, 8), REG_NZ + PV_LEFT },
{ NULL }
};
MTAB mux_mod[] = {
{ MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
&mux_vlines, tmxr_show_lines, (void *) &mux_desc },
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &mux_desc },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &mux_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &mux_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &tmxr_show_cstat, (void *) &mux_desc },
int32 cdp_ebcdic = 0; /* EBCDIC mode on punch */
extern int32 GetMem(int32 addr);
extern int32 PutMem(int32 addr, int32 data);
/* Card reader data structures
cdr_dev CDR descriptor
cdr_unit CDR unit descriptor
cdr_reg CDR register list
*/
UNIT cdr_unit = { UDATA (&cdr_svc, UNIT_SEQ+UNIT_ATTABLE, 0), 100 };
REG cdr_reg[] = {
{ FLDATA (LAST, lastcard, 0) },
{ FLDATA (ERR, carderr, 0) },
{ FLDATA (NOTRDY, notready, 0) },
{ HRDATA (DAR, DAR, 16) },
{ HRDATA (LCR, LCR, 16) },
{ FLDATA (EBCDIC, cdr_ebcdic, 0) },
{ FLDATA (S2, s2sel, 0) },
{ DRDATA (POS, cdr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, cdr_unit.wait, 24), PV_LEFT },
{ BRDATA (BUF, rbuf, 8, 8, CDR_WIDTH) },
{ NULL }
};
DEVICE cdr_dev = {
"CDR", &cdr_unit, cdr_reg, NULL,
1, 10, 31, 1, 8, 7,
{ UDATA (&mtr_svc, UNIT_DIS, 0) }
};
REG mt_reg[] = {
{ BRDATA (BUF, mt_xb, 16, 8, MT_MAXFR) },
{ DRDATA (BPTR, mt_bptr, 17) },
{ DRDATA (BLNT, mt_blim, 17) },
{ HRDATA (RWINT, mt_rwi, MT_NUMDR) },
{ DRDATA (TIME, mt_time, 24), PV_LEFT+REG_NZ },
{ DRDATA (CTIME, mt_ctime, 24), PV_LEFT+REG_NZ },
{ DRDATA (RWTIME, mt_rwtime, 24), PV_LEFT+REG_NZ },
{ URDATA (UST, mt_unit[0].UST, 16, 8, 0, MT_NUMDR, 0) },
{ URDATA (UCMD, mt_unit[0].UCMD, 16, 8, 0, 2 * MT_NUMDR, 0) },
{ URDATA (POS, mt_unit[0].pos, 10, T_ADDR_W, 0,
MT_NUMDR, PV_LEFT | REG_RO) },
{ FLDATA (STOP_IOE, mt_stopioe, 0) },
{ HRDATA (DEVNO, mt_dib.dva, 12), REG_HRO },
{ NULL }
};
MTAB mt_mod[] = {
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL },
{ MTAB_XTD|MTAB_VUN, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "CHAN", "CHAN",
&io_set_dvc, &io_show_dvc, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DVA", "DVA",
&io_set_dva, &io_show_dva, NULL },
*/
#define IOLN_PCLK 006
DIB pclk_dib = {
IOBA_AUTO, IOLN_PCLK, &pclk_rd, &pclk_wr,
1, IVCL (PCLK), VEC_AUTO, { NULL }
};
UNIT pclk_unit = { UDATA (&pclk_svc, UNIT_IDLE, 0) };
REG pclk_reg[] = {
{ ORDATA (CSR, pclk_csr, 16) },
{ ORDATA (CSB, pclk_csb, 16) },
{ ORDATA (CNT, pclk_ctr, 16) },
{ FLDATA (INT, IREQ (PCLK), INT_V_PCLK) },
{ FLDATA (OVFL, pclk_csr, CSR_V_ERR) },
{ FLDATA (DONE, pclk_csr, CSR_V_DONE) },
{ FLDATA (IE, pclk_csr, CSR_V_IE) },
{ FLDATA (UPDN, pclk_csr, CSR_V_UPDN) },
{ FLDATA (MODE, pclk_csr, CSR_V_MODE) },
{ FLDATA (RUN, pclk_csr, CSR_V_GO) },
{ BRDATA (TIME, xtim, 10, 32, 4), REG_NZ + PV_LEFT },
{ BRDATA (TPS, rate, 10, 32, 4), REG_NZ + PV_LEFT },
{ ORDATA (DEVADDR, pclk_dib.ba, 32), REG_HRO },
{ ORDATA (DEVVEC, pclk_dib.vec, 16), REG_HRO },
{ NULL }
};
MTAB pclk_mod[] = {
{ UNIT_LINE50HZ, UNIT_LINE50HZ, "50 Hz Line Frequency", "50HZ", &pclk_set_line },
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
DIB tti_dib = {
IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr,
1, IVCL (TTI), VEC_TTI, { NULL }
};
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), 0 };
REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 8) },
{ ORDATA (CSR, tti_csr, 16) },
{ FLDATA (INT, IREQ (TTI), INT_V_TTI) },
{ FLDATA (ERR, tti_csr, CSR_V_ERR) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, NULL },
*/
DIB mba0_dib = { TR_MBA0, 0, &mba_rdreg, &mba_wrreg, 0, NVCL (MBA0) };
UNIT mba0_unit = { UDATA (NULL, 0, 0) };
REG mba0_reg[] = {
{ HRDATA (CNFR, mba_cnf[0], 32) },
{ HRDATA (CR, mba_cr[0], 4) },
{ HRDATA (SR, mba_sr[0], 32) },
{ HRDATA (VA, mba_va[0], 17) },
{ HRDATA (BC, mba_bc[0], 16) },
{ HRDATA (DR, mba_dr[0], 32) },
{ HRDATA (SMR, mba_dr[0], 32) },
{ BRDATA (MAP, mba_map[0], 16, 32, MBA_NMAPR) },
{ FLDATA (NEXINT, nexus_req[IPL_MBA0], TR_MBA0) },
{ NULL }
};
MTAB mba0_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_MBA0, "NEXUS", NULL,
NULL, &show_nexus },
{ 0 }
};
DIB mba1_dib = { TR_MBA1, 0, &mba_rdreg, &mba_wrreg, 0, NVCL (MBA1) };
UNIT mba1_unit = { UDATA (NULL, 0, 0) };
MTAB mba1_mod[] = {
{ MTAB_XTD|MTAB_VDV, TR_MBA1, "NEXUS", NULL,
{ UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, CAP_4651) },
{ UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, CAP_4651) },
{ UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE, CAP_4651) }
};
REG dp_reg[] = {
{ ORDATA (STA, dp_sta, 16) },
{ ORDATA (BUF, dp_buf, 16) },
{ ORDATA (FNC, dp_fnc, 4) },
{ ORDATA (CW1, dp_cw1, 16) },
{ ORDATA (CW2, dp_cw2, 16) },
{ ORDATA (CSUM, dp_csum, 16) },
{ FLDATA (BUSY, dp_sta, 15) },
{ FLDATA (RDY, dp_sta, 14) },
{ FLDATA (EOR, dp_eor, 0) },
{ FLDATA (DEFINT, dp_defint, 0) },
{ FLDATA (INTREQ, dev_int, INT_V_DP) },
{ FLDATA (ENABLE, dev_enb, INT_V_DP) },
{ BRDATA (TBUF, dpxb, 8, 16, DP_TRKLEN) },
{ ORDATA (RPTR, dp_rptr, 11), REG_RO },
{ ORDATA (WPTR, dp_wptr, 11), REG_RO },
{ ORDATA (BCTR, dp_bctr, 15), REG_RO },
{ ORDATA (GAP, dp_gap, 16), REG_RO },
{ DRDATA (STIME, dp_stime, 24), REG_NZ + PV_LEFT },
{ DRDATA (XTIME, dp_xtime, 24), REG_NZ + PV_LEFT },
{ DRDATA (BTIME, dp_btime, 24), REG_NZ + PV_LEFT },
{ FLDATA (CTYPE, dp_ctype, 0), REG_HRO },
{ URDATA (UCYL, dp_unit[0].CYL, 10, 8, 0,
/* LPT data structures
lpt_dev LPT device descriptor
lpt_unit LPT unit descriptor
lpt_reg LPT register list
*/
DIB lpt_dib = { DEV_LPT, INT_LPT, PI_LPT, &lpt };
UNIT lpt_unit = { /* 2007-May-30, bkr */
UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 0), SERIAL_OUT_WAIT
};
REG lpt_reg[] = {
{ ORDATA (BUF, lpt_unit.buf, 8) },
{ FLDATA (BUSY, dev_busy, INT_V_LPT) },
{ FLDATA (DONE, dev_done, INT_V_LPT) },
{ FLDATA (DISABLE, dev_disable, INT_V_LPT) },
{ FLDATA (INT, int_req, INT_V_LPT) },
{ DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, lpt_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, lpt_stopioe, 0) },
{ NULL }
};
DEVICE lpt_dev = {
"LPT", &lpt_unit, lpt_reg, NULL,
1, 10, 31, 1, 8, 8,
NULL, NULL, &lpt_reset,
NULL, NULL, NULL,
&lpt_dib, DEV_DISABLE
ptr_dev PTR device descriptor
ptr_unit PTR unit
ptr_reg PTR register list
*/
DIB ptr_dib = { CHAN_W, DEV_PTR, XFR_PTR, std_tplt, &ptr };
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
REG ptr_reg[] = {
{ ORDATA (BUF, ptr_unit.buf, 7) },
{ FLDATA (XFR, xfr_req, XFR_V_PTR) },
{ FLDATA (SOR, ptr_sor, 0) },
{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), REG_NZ + PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ NULL }
};
MTAB ptr_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "CHANNEL", "CHANNEL",
&set_chan, &show_chan, NULL },
{ 0 }
};
DEVICE ptr_dev = {
"PTR", &ptr_unit, ptr_reg, ptr_mod,
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
tti_mod TTI modifiers list
*/
DIB tti_dib = { DEV_TTI, 1, { &tti } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_KSR, 0), 0 };
REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, 8) },
{ FLDATA (DONE, dev_done, INT_V_TTI) },
{ FLDATA (ENABLE, int_enable, INT_V_TTI) },
{ FLDATA (INT, int_req, INT_V_TTI) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_KSR, "KSR", "KSR", &tty_set_mode },
{ TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },
{ TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },
{ TT_MODE, TT_MODE_7P, "7b", NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", NULL, NULL, &show_dev, NULL },
{ 0 }
};
t_bool fl_test_xfr (UNIT *uptr, t_bool wr);
void fl_protocol_error (void);
/* TTI data structures
tti_dev TTI device descriptor
tti_unit TTI unit descriptor
tti_reg TTI register list
*/
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 };
REG tti_reg[] = {
{ HRDATA (RXDB, tti_buf, 16) },
{ HRDATA (RXCS, tti_csr, 16) },
{ FLDATA (INT, tti_int, 0) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ NULL }
};
MTAB tti_mod[] = {
{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
{ 0 }
};
DEVICE tti_dev = {
"TTI", &tti_unit, tti_reg, tti_mod,
t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);
/* CLK data structures
clk_dev CLK device descriptor
clk_unit CLK unit descriptor
clk_reg CLK register list
*/
DIB clk_dib = { DEV_CLK, INT_CLK, PI_CLK, &clk };
UNIT clk_unit = { UDATA (&clk_svc, 0, 0) };
REG clk_reg[] = {
{ ORDATA (SELECT, clk_sel, 2) },
{ FLDATA (BUSY, dev_busy, INT_V_CLK) },
{ FLDATA (DONE, dev_done, INT_V_CLK) },
{ FLDATA (DISABLE, dev_disable, INT_V_CLK) },
{ FLDATA (INT, int_req, INT_V_CLK) },
{ DRDATA (TIME0, clk_time[0], 24), REG_NZ + PV_LEFT },
{ DRDATA (TIME1, clk_time[1], 24), REG_NZ + PV_LEFT },
{ DRDATA (TIME2, clk_time[2], 24), REG_NZ + PV_LEFT },
{ DRDATA (TIME3, clk_time[3], 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS0, clk_tps[0], 6), PV_LEFT + REG_HRO },
{ NULL }
};
MTAB clk_mod[] = {
{ MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",
&clk_set_freq, NULL, NULL },
{ MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",
UNIT rx_unit[] = {
{ UDATA (&rx_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) },
{ UDATA (&rx_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) } };
REG rx_reg[] = {
{ ORDATA (RXCS, rx_csr, 16) },
{ ORDATA (RXDB, rx_dbr, 8) },
{ ORDATA (RXES, rx_esr, 8) },
{ ORDATA (RXERR, rx_ecode, 8) },
{ ORDATA (RXTA, rx_track, 8) },
{ ORDATA (RXSA, rx_sector, 8) },
{ ORDATA (STAPTR, rx_state, 3), REG_RO },
{ ORDATA (BUFPTR, bptr, 7) },
{ FLDATA (INT, int_req, INT_V_RX) },
{ FLDATA (ERR, rx_csr, CSR_V_ERR) },
{ FLDATA (TR, rx_csr, RXCS_V_TR) },
{ FLDATA (IE, rx_csr, CSR_V_IE) },
{ FLDATA (DONE, rx_csr, RXCS_V_DONE) },
{ DRDATA (CTIME, rx_cwait, 24), PV_LEFT },
{ DRDATA (STIME, rx_swait, 24), PV_LEFT },
{ DRDATA (XTIME, rx_xwait, 24), PV_LEFT },
{ FLDATA (FLG0, rx_unit[0].flags, UNIT_V_WLK), REG_HRO },
{ FLDATA (FLG1, rx_unit[1].flags, UNIT_V_WLK), REG_HRO },
{ FLDATA (STOP_IOE, rx_stopioe, 0) },
{ BRDATA (**BUF, buf, 8, 8, RX_NUMBY), REG_HRO },
{ NULL } };
MTAB rx_mod[] = {
{ UNIT_WLK, 0, "write enabled", "ENABLED", NULL },
/* TTP data structures */
DIB ttp_dib = { d_TTP, -1, v_TTP, ttp_tplte, &ttp, NULL };
UNIT ttp_unit[] = {
{ UDATA (&ttpi_svc, UNIT_IDLE, 0), 0 },
{ UDATA (&ttpo_svc, 0, 0), SERIAL_OUT_WAIT }
};
REG ttp_reg[] = {
{ HRDATA (CMD, ttp_cmd, 16) },
{ HRDATA (KBUF, ttp_unit[TTI].buf, 8) },
{ DRDATA (KPOS, ttp_unit[TTI].pos, T_ADDR_W), PV_LEFT },
{ DRDATA (KTIME, ttp_unit[TTI].wait, 24), REG_NZ + PV_LEFT + REG_HRO },
{ FLDATA (KIREQ, int_req[l_TTP], i_TTP) },
{ FLDATA (KIENB, int_enb[l_TTP], i_TTP) },
{ FLDATA (KARM, ttp_karm, 0) },
{ FLDATA (CHP, ttp_kchp, 0) },
{ HRDATA (TBUF, ttp_unit[TTO].buf, 8) },
{ DRDATA (TPOS, ttp_unit[TTO].pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TTIME, ttp_unit[TTO].wait, 24), REG_NZ + PV_LEFT },
{ FLDATA (TIREQ, int_req[l_TTP], i_TTP + 1) },
{ FLDATA (TIENB, int_enb[l_TTP], i_TTP + 1) },
{ FLDATA (TARM, ttp_tarm, 0) },
{ HRDATA (DEVNO, ttp_dib.dno, 8), REG_HRO },
{ NULL }
};
MTAB ttp_mod[] = {
{ TT_MODE, TT_MODE_UC, "UC", "UC", &ttp_set_mode },
{ BRDATA (DS, rpds, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (ER1, rper1, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (HR, rmhr, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (OF, rpof, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (DC, rpdc, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (ER2, rper2, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (ER3, rper3, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (EC1, rpec1, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (EC2, rpec2, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (MR, rpmr, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (MR2, rmmr2, DEV_RDX, 16, RP_NUMDR) },
{ DRDATA (STIME, rp_swait, 24), REG_NZ + PV_LEFT },
{ DRDATA (RTIME, rp_rwait, 24), REG_NZ + PV_LEFT },
{ URDATA (CAPAC, rp_unit[0].capac, 10, T_ADDR_W, 0,
RP_NUMDR, PV_LEFT | REG_HRO) },
{ FLDATA (STOP_IOE, rp_stopioe, 0) },
{ GRDATA (CTRLTYPE, rp_dib.lnt, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB rp_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "MASSBUS", "MASSBUS", NULL, &mba_show_num },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK", &rp_set_bad },
{ (UNIT_DTYPE+UNIT_ATT), (RM03_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RM03", NULL, NULL },
{ (UNIT_DTYPE+UNIT_ATT), (RP04_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RP04", NULL, NULL },
{ (UNIT_DTYPE+UNIT_ATT), (RM80_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RM80", NULL, NULL },
t_stat inq_reset (DEVICE *dptr);
void inq_puts (char *cptr);
/* INQ data structures
inq_dev INQ device descriptor
inq_unit INQ unit descriptor
inq_reg INQ register list
*/
UNIT inq_unit = { UDATA (&inq_svc, 0, 0), KBD_POLL_WAIT };
REG inq_reg[] = {
{ ORDATA (INQC, inq_char, 7) },
{ FLDATA (INR, ind[IN_INR], 0) },
{ FLDATA (INC, ind[IN_INC], 0) },
{ DRDATA (TIME, inq_unit.wait, 24), REG_NZ + PV_LEFT },
{ NULL }
};
MTAB inq_mod[] = {
{ UNIT_PCH, 0, "business set", "BUSINESS" },
{ UNIT_PCH, UNIT_PCH, "Fortran set", "FORTRAN" },
{ 0 }
};
DEVICE inq_dev = {
"INQ", &inq_unit, inq_reg, inq_mod,
1, 10, 31, 1, 8, 7,
NULL, NULL, &inq_reset,
/* CPU data structures
cpu_dev CPU device descriptor
cpu_unit CPU unit descriptor
cpu_reg CPU register list
cpu_mod CPU modifiers list
*/
UNIT cpu_unit = { UDATA (NULL, UNIT_FIX+UNIT_IN4B+UNIT_TTSS_D, MEMSIZE) };
REG cpu_reg[] = {
{ DRDATA (C, PC, 12), REG_VMAD },
{ HRDATA (A, A, 32), REG_VMIO },
{ HRDATA (IR, IR, 32), REG_VMIO },
{ FLDATA (OVF, OVF, 0) },
{ FLDATA (TSW, t_switch, 0) },
{ FLDATA (BP32, bp32, 0) },
{ FLDATA (BP16, bp16, 0) },
{ FLDATA (BP8, bp8, 0) },
{ FLDATA (BP4, bp4, 0) },
{ FLDATA (INPST, inp_strt, 0) },
{ FLDATA (INPDN, inp_done, 0) },
{ FLDATA (OUTST, out_strt, 0) },
{ FLDATA (OUTDN, out_done, 0) },
{ DRDATA (DELAY, delay, 7) },
{ BRDATA (CQ, pcq, 16, 12, PCQ_SIZE), REG_RO + REG_CIRC },
{ HRDATA (CQP, pcq_p, 6), REG_HRO },
{ HRDATA (WRU, sim_int_char, 8) },
{ NULL }
};
{ UDATA (&rx_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) },
{ UDATA (&rx_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, RX_SIZE) }
};
REG rx_reg[] = {
{ ORDATA (RXCS, rx_csr, 16) },
{ ORDATA (RXDB, rx_dbr, 8) },
{ ORDATA (RXES, rx_esr, 8) },
{ ORDATA (RXERR, rx_ecode, 8) },
{ ORDATA (RXTA, rx_track, 8) },
{ ORDATA (RXSA, rx_sector, 8) },
{ DRDATA (STAPTR, rx_state, 3), REG_RO },
{ DRDATA (BUFPTR, rx_bptr, 7) },
{ FLDATA (INT, IREQ (RX), INT_V_RX) },
{ FLDATA (ERR, rx_csr, RXCS_V_ERR) },
{ FLDATA (TR, rx_csr, RXCS_V_TR) },
{ FLDATA (IE, rx_csr, RXCS_V_IE) },
{ FLDATA (DONE, rx_csr, RXCS_V_DONE) },
{ DRDATA (CTIME, rx_cwait, 24), PV_LEFT },
{ DRDATA (STIME, rx_swait, 24), PV_LEFT },
{ DRDATA (XTIME, rx_xwait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, rx_stopioe, 0) },
{ BRDATA (SBUF, rx_buf, 8, 8, RX_NUMBY) },
{ ORDATA (DEVADDR, rx_dib.ba, 32), REG_HRO },
{ ORDATA (DEVVEC, rx_dib.vec, 16), REG_HRO },
{ NULL }
};
MTAB rx_mod[] = {
