/** * fm10k_disable_queues_generic - Stop Tx/Rx queues * @hw: pointer to hardware structure * @q_cnt: number of queues to be disabled * **/ s32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt) { u32 reg; u16 i, time; /* clear tx_ready to prevent any false hits for reset */ hw->mac.tx_ready = false; if (FM10K_REMOVED(hw->hw_addr)) return 0; /* clear the enable bit for all rings */ for (i = 0; i < q_cnt; i++) { reg = fm10k_read_reg(hw, FM10K_TXDCTL(i)); fm10k_write_reg(hw, FM10K_TXDCTL(i), reg & ~FM10K_TXDCTL_ENABLE); reg = fm10k_read_reg(hw, FM10K_RXQCTL(i)); fm10k_write_reg(hw, FM10K_RXQCTL(i), reg & ~FM10K_RXQCTL_ENABLE); } fm10k_write_flush(hw); udelay(1); /* loop through all queues to verify that they are all disabled */ for (i = 0, time = FM10K_QUEUE_DISABLE_TIMEOUT; time;) { /* if we are at end of rings all rings are disabled */ if (i == q_cnt) return 0; /* if queue enables cleared, then move to next ring pair */ reg = fm10k_read_reg(hw, FM10K_TXDCTL(i)); if (!~reg || !(reg & FM10K_TXDCTL_ENABLE)) { reg = fm10k_read_reg(hw, FM10K_RXQCTL(i)); if (!~reg || !(reg & FM10K_RXQCTL_ENABLE)) { i++; continue; } } /* decrement time and wait 1 usec */ time--; if (time) udelay(1); } return FM10K_ERR_REQUESTS_PENDING; }
/** * fm10k_get_host_state_generic - Returns the state of the host * @hw: pointer to hardware structure * @host_ready: pointer to boolean value that will record host state * * This function will check the health of the mailbox and Tx queue 0 * in order to determine if we should report that the link is up or not. **/ s32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready) { struct fm10k_mbx_info *mbx = &hw->mbx; struct fm10k_mac_info *mac = &hw->mac; s32 ret_val = 0; u32 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(0)); /* process upstream mailbox in case interrupts were disabled */ mbx->ops.process(hw, mbx); /* If Tx is no longer enabled link should come down */ if (!(~txdctl) || !(txdctl & FM10K_TXDCTL_ENABLE)) mac->get_host_state = true; /* exit if not checking for link, or link cannot be changed */ if (!mac->get_host_state || !(~txdctl)) goto out; /* if we somehow dropped the Tx enable we should reset */ if (mac->tx_ready && !(txdctl & FM10K_TXDCTL_ENABLE)) { ret_val = FM10K_ERR_RESET_REQUESTED; goto out; } /* if Mailbox timed out we should request reset */ if (!mbx->timeout) { ret_val = FM10K_ERR_RESET_REQUESTED; goto out; } /* verify Mailbox is still open */ if (mbx->state != FM10K_STATE_OPEN) goto out; /* interface cannot receive traffic without logical ports */ if (mac->dglort_map == FM10K_DGLORTMAP_NONE) { if (mac->ops.request_lport_map) ret_val = mac->ops.request_lport_map(hw); goto out; } /* if we passed all the tests above then the switch is ready and we no * longer need to check for link */ mac->get_host_state = false; out: *host_ready = !mac->get_host_state; return ret_val; }
static void fm10k_get_reg_q(struct fm10k_hw *hw, u32 *buff, int i) { int idx = 0; buff[idx++] = fm10k_read_reg(hw, FM10K_RDBAL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RDBAH(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RDLEN(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TPH_RXCTRL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RDH(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RDT(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RXQCTL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RXDCTL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_RXINT(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_SRRCTL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QPRC(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QPRDC(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QBRC_L(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QBRC_H(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TDBAL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TDBAH(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TDLEN(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TPH_TXCTRL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TDH(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TDT(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TXDCTL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TXQCTL(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TXINT(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QPTC(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QBTC_L(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_QBTC_H(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TQDLOC(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_TX_SGLORT(i)); buff[idx++] = fm10k_read_reg(hw, FM10K_PFVTCTL(i)); BUG_ON(idx != FM10K_REGS_LEN_Q); }