void op_ldf()
{
unsigned char ra, rb;
PCInc(1);
ra = Fetch8();
PCInc(1);
rb = Fetch8();
PCInc(1);
*(float*)&Registers[ra] = *(float*)&VmMemory[Registers[rb]];
}
void op_not()
{
unsigned char ra, rb;
PCInc(1);
ra = Fetch8();
PCInc(1);
rb = Fetch8();
PCInc(1);
Registers[ra] = ~Registers[rb];
}
void op_sth()
{
unsigned char ra, rb;
PCInc(1);
ra = Fetch8();
PCInc(1);
rb = Fetch8();
PCInc(1);
*(unsigned short*)&VmMemory[Registers[rb]] = Registers[ra] & 0xFFFF;
}
void op_ldw()
{
unsigned char ra, rb;
PCInc(1);
ra = Fetch8();
PCInc(1);
rb = Fetch8();
PCInc(1);
Registers[ra] = *(unsigned int*)&VmMemory[Registers[rb]];
}
void op_movf()
{
unsigned char ra, rb;
PCInc(1);
ra = Fetch8();
PCInc(1);
rb = Fetch8();
PCInc(1);
*(float*)&Registers[ra] = *(float*)&Registers[rb];
}
void op_mulf()
{
unsigned char ra, rb, rc;
PCInc(1);
ra = Fetch8();
PCInc(1);
rb = Fetch8();
PCInc(1);
rc = Fetch8();
PCInc(1);
*(float*)&Registers[ra] = *(float*)&Registers[rb] * *(float*)&Registers[rc];
}
void op_shl()
{
unsigned char ra, rb, rc;
PCInc(1);
ra = Fetch8();
PCInc(1);
rb = Fetch8();
PCInc(1);
rc = Fetch8();
PCInc(1);
Registers[ra] = Registers[rb] << Registers[rc];
}
void op_cmp()
{
unsigned char ra, rb;
PCInc(1);
ra = Fetch8();
PCInc(1);
rb = Fetch8();
PCInc(1);
Registers[ctr0] = ctr0_null;
Registers[ctr0] |= (Registers[ra] == Registers[rb]) ? ctr0_eq : ctr0_ne;
Registers[ctr0] |= (Registers[ra] > Registers[rb]) ? ctr0_gt : ctr0_null;
Registers[ctr0] |= (Registers[ra] < Registers[rb]) ? ctr0_lt : ctr0_null;
}
void op_divf()
{
unsigned char ra, rb, rc;
unsigned int pre = *(float*)&Registers[pc];
PCInc(1);
ra = Fetch8();
PCInc(1);
rb = Fetch8();
PCInc(1);
rc = Fetch8();
PCInc(1);
if (Registers[rc] == 0)
Error("Divide By Zero PC = %s\n", pre);
*(float*)&Registers[ra] = *(float*)&Registers[rb] / *(float*)&Registers[rc];
}
void op_dec()
{
unsigned char ra;
PCInc(1);
ra = Fetch8();
PCInc(1);
Registers[ra] = Registers[ra] - 1;
}
void op_pop()
{
unsigned char ra;
PCInc(1);
ra = Fetch8();
PCInc(1);
Registers[ra] = *(unsigned int*)&VmMemory[Registers[sp]];
Registers[sp] -= 4;
}
int MinxCPU_ExecSPCE(void)
{
// Read IR
MinxCPU.IR = Fetch8();
// Process instruction
switch(MinxCPU.IR) {
// TODO!
default:
MinxCPU_OnException(EXCEPTION_UNKNOWN_INSTRUCTION, (MinxCPU.IR << 16) + 0xCEFF);
return 64;
}
}
void op_lif()
{
unsigned char ra;
unsigned int rb;
PCInc(1);
ra = Fetch8();
PCInc(1);
rb = Fetch32();
PCInc(4);
*(float*)&Registers[ra] = *(float*)&rb;
}
void op_push()
{
unsigned char ra;
PCInc(1);
ra = Fetch8();
PCInc(1);
if (Registers[sp] >= VmMemorySize)
Error("Stack gone beyond memory limits");
Registers[sp] += 4;
*(unsigned int*)&VmMemory[Registers[sp]] = Registers[ra];
}
void op_li()
{
unsigned char ra;
unsigned int rb;
PCInc(1);
ra = Fetch8();
PCInc(1);
rb = Fetch32();
PCInc(4);
Registers[ra] = rb;
}
void Step()
{
Opcodes OP = (Opcodes)Fetch8();
//printf("%08X:%08X\n", Registers[sp], Registers[pc]);
switch (OP)
{
case O_NOP:
op_nop();
break;
case O_MOV:
op_mov();
break;
case O_ADD:
op_add();
break;
case O_SUB:
op_sub();
break;
case O_MUL:
op_mul();
break;
case O_DIV:
op_div();
break;
case O_LI:
op_li();
break;
case O_MOVF:
op_movf();
break;
case O_ADDF:
op_addf();
break;
case O_SUBF:
op_subf();
break;
case O_MULF:
op_mulf();
break;
case O_DIVF:
op_divf();
break;
case O_LIF:
op_lif();
break;
case O_XOR:
op_xor();
break;
case O_AND:
op_and();
break;
case O_MOD:
op_mod();
break;
case O_OR:
op_or();
break;
case O_NOT:
op_not();
break;
case O_SHR:
op_shr();
break;
case O_SHL:
op_shl();
break;
case O_PUSH:
op_push();
break;
case O_POP:
op_pop();
break;
case O_STB:
op_stb();
break;
case O_LDB:
op_ldb();
break;
case O_STH:
op_sth();
break;
case O_LDH:
op_ldh();
break;
case O_STW:
op_stw();
break;
case O_LDW:
op_ldw();
break;
case O_LDF:
op_ldf();
break;
case O_STF:
op_stf();
break;
case O_CMP:
op_cmp();
break;
case O_B:
op_b(0);
break;
case O_BC:
op_b(1);
break;
case O_BEQ:
op_bcond(ctr0_eq);
break;
case O_BNE:
op_bcond(ctr0_ne);
break;
case O_BGT:
op_bcond(ctr0_gt);
break;
case O_BLT:
op_bcond(ctr0_lt);
break;
case O_BTC:
op_btc();
break;
case O_INC:
op_inc();
break;
case O_DEC:
op_dec();
break;
default:
Error("Error: Unknown Opcode PC = %d OP = %08X\n", Registers[pc], OP);
}
Ticks++;
}
int MinxCPU_ExecSPCF(void)
{
// Read IR
MinxCPU.IR = Fetch8();
// Process instruction
switch(MinxCPU.IR) {
case 0x00: case 0x01: case 0x02: case 0x03: // Decrement BA
MinxCPU.BA.W.L = DEC16(MinxCPU.BA.W.L);
return 16;
case 0x04: case 0x05: case 0x06: case 0x07: // Decrement BA if Carry = 0
if (!(MinxCPU.F & MINX_FLAG_CARRY)) MinxCPU.BA.W.L = DEC16(MinxCPU.BA.W.L);
return 16;
case 0x08: case 0x09: case 0x0A: case 0x0B: // Increment BA
MinxCPU.BA.W.L = INC16(MinxCPU.BA.W.L);
return 16;
case 0x0C: case 0x0D: case 0x0E: case 0x0F: // Increment BA if Carry = 0
if (!(MinxCPU.F & MINX_FLAG_CARRY)) MinxCPU.BA.W.L = INC16(MinxCPU.BA.W.L);
return 16;
case 0x10: case 0x11: case 0x12: case 0x13: // Decrement BA
MinxCPU.BA.W.L = DEC16(MinxCPU.BA.W.L);
return 16;
case 0x14: case 0x15: case 0x16: case 0x17: // Decrement BA if Carry = 0
if (!(MinxCPU.F & MINX_FLAG_CARRY)) MinxCPU.BA.W.L = DEC16(MinxCPU.BA.W.L);
return 16;
case 0x18: case 0x19: case 0x1A: case 0x1B: // Increment BA (Doesn't save result!!)
INC16(MinxCPU.BA.W.L);
return 16;
case 0x1C: case 0x1D: case 0x1E: case 0x1F: // Increment BA if Carry = 0
if (!(MinxCPU.F & MINX_FLAG_CARRY)) MinxCPU.BA.W.L = INC16(MinxCPU.BA.W.L);
return 16;
case 0x20: case 0x21: case 0x22: case 0x23: // Decrement HL
MinxCPU.HL.W.L = DEC16(MinxCPU.HL.W.L);
return 16;
case 0x24: case 0x25: case 0x26: case 0x27: // Decrement HL if Carry = 0
if (!(MinxCPU.F & MINX_FLAG_CARRY)) MinxCPU.HL.W.L = DEC16(MinxCPU.HL.W.L);
return 16;
case 0x28: case 0x29: case 0x2A: case 0x2B: // Increment HL
MinxCPU.HL.W.L = INC16(MinxCPU.HL.W.L);
return 16;
case 0x2C: case 0x2D: case 0x2E: case 0x2F: // Increment HL if Carry = 0
if (!(MinxCPU.F & MINX_FLAG_CARRY)) MinxCPU.HL.W.L = INC16(MinxCPU.HL.W.L);
return 16;
case 0x30: case 0x31: case 0x32: case 0x33: // Decrement HL
MinxCPU.HL.W.L = DEC16(MinxCPU.HL.W.L);
return 16;
case 0x34: case 0x35: case 0x36: case 0x37: // Decrement HL if Carry = 0
if (!(MinxCPU.F & MINX_FLAG_CARRY)) MinxCPU.HL.W.L = DEC16(MinxCPU.HL.W.L);
return 16;
case 0x38: case 0x39: case 0x3A: case 0x3B: // Increment HL (Doesn't save result!!)
INC16(MinxCPU.HL.W.L);
return 16;
case 0x3C: case 0x3D: case 0x3E: case 0x3F: // Increment HL if Carry = 0
if (!(MinxCPU.F & MINX_FLAG_CARRY)) MinxCPU.HL.W.L = INC16(MinxCPU.HL.W.L);
return 16;
case 0x40: case 0x41: // Decrement X
MinxCPU.X.W.L = DEC16(MinxCPU.X.W.L);
return 16;
case 0x42: case 0x43: // Decrement Y
MinxCPU.X.W.L = DEC16(MinxCPU.X.W.L);
return 16;
case 0x44: case 0x45: // Decrement SP
MinxCPU.SP.W.L = DEC16(MinxCPU.SP.W.L);
return 16;
case 0x46: case 0x47: // CRASH
MinxCPU_OnException(EXCEPTION_CRASH_INSTRUCTION, (MinxCPU.IR << 16) | 0xBFCF);
return 16;
case 0x48: case 0x49: // Increment X
MinxCPU.X.W.L = INC16(MinxCPU.X.W.L);
return 16;
case 0x4A: case 0x4B: // Increment Y
MinxCPU.X.W.L = INC16(MinxCPU.X.W.L);
return 16;
case 0x4C: case 0x4D: // Increment SP
MinxCPU.SP.W.L = INC16(MinxCPU.SP.W.L);
return 16;
case 0x4E: case 0x4F: // CRASH
MinxCPU_OnException(EXCEPTION_CRASH_INSTRUCTION, (MinxCPU.IR << 16) | 0xBFCF);
return 16;
case 0x50: case 0x51: // Decrement X
MinxCPU.X.W.L = DEC16(MinxCPU.X.W.L);
return 16;
case 0x52: case 0x53: // Decrement Y
MinxCPU.X.W.L = DEC16(MinxCPU.X.W.L);
return 16;
case 0x54: case 0x55: // Decrement SP
MinxCPU.SP.W.L = DEC16(MinxCPU.SP.W.L);
return 16;
case 0x56: case 0x57: // CRASH
MinxCPU_OnException(EXCEPTION_CRASH_INSTRUCTION, (MinxCPU.IR << 16) | 0xBFCF);
return 16;
case 0x58: case 0x59: // Increment X
MinxCPU.X.W.L = INC16(MinxCPU.X.W.L);
return 16;
case 0x5A: case 0x5B: // Increment Y
MinxCPU.X.W.L = INC16(MinxCPU.X.W.L);
return 16;
case 0x5C: case 0x5D: // Increment SP
MinxCPU.SP.W.L = INC16(MinxCPU.SP.W.L);
return 16;
case 0x5E: case 0x5F: // CRASH
MinxCPU_OnException(EXCEPTION_CRASH_INSTRUCTION, (MinxCPU.IR << 16) | 0xBFCF);
return 16;
case 0x60: case 0x61: case 0x62: case 0x63: // CRASH
case 0x64: case 0x65: case 0x66: case 0x67:
case 0x68: case 0x69: case 0x6A: case 0x6B:
case 0x6C: case 0x6D: case 0x6E: case 0x6F:
MinxCPU_OnException(EXCEPTION_CRASH_INSTRUCTION, (MinxCPU.IR << 16) | 0xBFCF);
return 16;
case 0x70: // BA = (0x4D << 8) | V
MinxCPU.BA.W.L = 0x4D00 | MinxCPU.PC.B.I;
return 24;
case 0x71: // HL = (0x4D << 8) | V
MinxCPU.HL.W.L = 0x4D00 | MinxCPU.PC.B.I;
return 24;
case 0x72: // X = (0x4D << 8) | V
MinxCPU.X.W.L = 0x4D00 | MinxCPU.PC.B.I;
return 24;
case 0x73: // Y = (0x4D << 8) | V
MinxCPU.Y.W.L = 0x4D00 | MinxCPU.PC.B.I;
return 24;
case 0x74: case 0x75: case 0x76: case 0x77: // NOTHING
return 24;
case 0x78: case 0x79: case 0x7A: case 0x7B: // CRASH
case 0x7C: case 0x7D: case 0x7E: case 0x7F:
case 0x80: case 0x81: case 0x82: case 0x83:
case 0x84: case 0x85: case 0x86: case 0x87:
case 0x88: case 0x89: case 0x8A: case 0x8B:
case 0x8C: case 0x8D: case 0x8E: case 0x8F:
case 0x90: case 0x91: case 0x92: case 0x93:
case 0x94: case 0x95: case 0x96: case 0x97:
case 0x98: case 0x99: case 0x9A: case 0x9B:
case 0x9C: case 0x9D: case 0x9E: case 0x9F:
case 0xA0: case 0xA1: case 0xA2: case 0xA3:
case 0xA4: case 0xA5: case 0xA6: case 0xA7:
case 0xA8: case 0xA9: case 0xAA: case 0xAB:
case 0xAC: case 0xAD: case 0xAE: case 0xAF:
MinxCPU_OnException(EXCEPTION_CRASH_INSTRUCTION, (MinxCPU.IR << 16) | 0xBFCF);
return 24;
case 0xB0: case 0xB1: case 0xB2: case 0xB3: // NOTHING
return 12;
case 0xB4: case 0xB5: case 0xB6: case 0xB7: // CRASH
case 0xB8: case 0xB9: case 0xBA: case 0xBB:
case 0xBC: case 0xBD: case 0xBE: case 0xBF:
MinxCPU_OnException(EXCEPTION_CRASH_INSTRUCTION, (MinxCPU.IR << 16) | 0xBFCF);
return 12;
case 0xC0: // BA = (0x20 << 8) | V
MinxCPU.BA.W.L = 0x2000 | MinxCPU.PC.B.I;
return 20;
case 0xC1: // HL = (0x20 << 8) | V
MinxCPU.HL.W.L = 0x2000 | MinxCPU.PC.B.I;
return 20;
case 0xC2: // X = (0x20 << 8) | V
MinxCPU.X.W.L = 0x2000 | MinxCPU.PC.B.I;
return 20;
case 0xC3: // Y = (0x20 << 8) | V
MinxCPU.Y.W.L = 0x2000 | MinxCPU.PC.B.I;
return 20;
case 0xC4: case 0xC5: case 0xC6: case 0xC7: // NOTHING
return 20;
case 0xC8: case 0xC9: case 0xCA: case 0xCB: // CRASH
case 0xCC: case 0xCD: case 0xCE: case 0xCF:
MinxCPU_OnException(EXCEPTION_CRASH_INSTRUCTION, (MinxCPU.IR << 16) | 0xBFCF);
return 20;
case 0xD0: // BA = (0x20 << 8) | V
MinxCPU.BA.W.L = 0x2000 | MinxCPU.PC.B.I;
return 20;
case 0xD1: // HL = (0x20 << 8) | V
MinxCPU.HL.W.L = 0x2000 | MinxCPU.PC.B.I;
return 20;
case 0xD2: // X = (0x20 << 8) | V
MinxCPU.X.W.L = 0x2000 | MinxCPU.PC.B.I;
return 20;
case 0xD3: // Y = (0x00 << 8) | V ? (EH!?)
MinxCPU.Y.W.L = 0x0000 | MinxCPU.PC.B.I;
return 20;
case 0xD4: case 0xD5: case 0xD6: case 0xD7: // NOTHING
return 20;
case 0xD8: // BA = (0x20 << 8) | V
MinxCPU.BA.W.L = 0x2000 | MinxCPU.PC.B.I;
return 20;
case 0xD9: // HL = (0x20 << 8) | V
MinxCPU.HL.W.L = 0x2000 | MinxCPU.PC.B.I;
return 20;
case 0xDA: // X = (0x20 << 8) | V
MinxCPU.X.W.L = 0x2000 | MinxCPU.PC.B.I;
return 20;
case 0xDB: // Y = (0x20 << 8) | V
MinxCPU.Y.W.L = 0x2000 | MinxCPU.PC.B.I;
return 20;
case 0xDC: case 0xDD: case 0xDE: case 0xDF: // NOTHING
return 20;
case 0xE0: case 0xE1: case 0xE2: case 0xE3: // CRASH
case 0xE4: case 0xE5: case 0xE6: case 0xE7:
case 0xE8: case 0xE9: case 0xEA: case 0xEB:
case 0xEC: case 0xED: case 0xEE: case 0xEF:
case 0xF0: case 0xF1: case 0xF2: case 0xF3:
case 0xF4: case 0xF5: case 0xF6: case 0xF7:
case 0xF8: case 0xF9: case 0xFA: case 0xFB:
case 0xFC: case 0xFD: case 0xFE: case 0xFF:
MinxCPU_OnException(EXCEPTION_CRASH_INSTRUCTION, (MinxCPU.IR << 16) | 0xBFCF);
return 24;
default:
MinxCPU_OnException(EXCEPTION_UNKNOWN_INSTRUCTION, (MinxCPU.IR << 16) + 0xBFCF);
return 64;
}
}
int MinxCPU_Exec(void)
{
uint8_t I8A, I8B;
uint16_t I16;
// Shift U
if (MinxCPU.Shift_U) {
MinxCPU.U1 = MinxCPU.U2;
MinxCPU.U2 = MinxCPU.PC.B.I;
MinxCPU.Shift_U--;
MinxCPU_OnIRQHandle(MinxCPU.F, MinxCPU.Shift_U);
}
// Check HALT or STOP status
if (MinxCPU.Status != MINX_STATUS_NORMAL) {
if (MinxCPU.Status == MINX_STATUS_IRQ) {
MinxCPU.Status = MINX_STATUS_NORMAL; // Return to normal
CALLI(MinxCPU.IRQ_Vector); // Jump to IRQ vector
return 20;
} else {
return 8; // Cause short NOPs
}
}
// Read IR
MinxCPU.IR = Fetch8();
// Process instruction
switch(MinxCPU.IR) {
case 0x00: // ADD A, A
MinxCPU.BA.B.L = ADD8(MinxCPU.BA.B.L, MinxCPU.BA.B.L);
return 8;
case 0x01: // ADD A, B
MinxCPU.BA.B.L = ADD8(MinxCPU.BA.B.L, MinxCPU.BA.B.H);
return 8;
case 0x02: // ADD A, #nn
I8A = Fetch8();
MinxCPU.BA.B.L = ADD8(MinxCPU.BA.B.L, I8A);
return 8;
case 0x03: // ADD A, [HL]
MinxCPU.BA.B.L = ADD8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 8;
case 0x04: // ADD A, [N+#nn]
I8A = Fetch8();
MinxCPU.BA.B.L = ADD8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.N.D + I8A));
return 12;
case 0x05: // ADD A, [#nnnn]
I16 = Fetch16();
MinxCPU.BA.B.L = ADD8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16));
return 16;
case 0x06: // ADD A, [X]
MinxCPU.BA.B.L = ADD8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.X.D));
return 8;
case 0x07: // ADD A, [Y]
MinxCPU.BA.B.L = ADD8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 8;
case 0x08: // ADC A, A
MinxCPU.BA.B.L = ADC8(MinxCPU.BA.B.L, MinxCPU.BA.B.L);
return 8;
case 0x09: // ADC A, B
MinxCPU.BA.B.L = ADC8(MinxCPU.BA.B.L, MinxCPU.BA.B.H);
return 8;
case 0x0A: // ADC A, #nn
I8A = Fetch8();
MinxCPU.BA.B.L = ADC8(MinxCPU.BA.B.L, I8A);
return 8;
case 0x0B: // ADC A, [HL]
MinxCPU.BA.B.L = ADC8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 8;
case 0x0C: // ADC A, [N+#nn]
I8A = Fetch8();
MinxCPU.BA.B.L = ADC8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.N.D + I8A));
return 12;
case 0x0D: // ADC A, [#nnnn]
I16 = Fetch16();
MinxCPU.BA.B.L = ADC8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16));
return 16;
case 0x0E: // ADC A, [X]
MinxCPU.BA.B.L = ADC8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.X.D));
return 8;
case 0x0F: // ADC A, [Y]
MinxCPU.BA.B.L = ADC8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 8;
case 0x10: // SUB A, A
MinxCPU.BA.B.L = SUB8(MinxCPU.BA.B.L, MinxCPU.BA.B.L);
return 8;
case 0x11: // SUB A, B
MinxCPU.BA.B.L = SUB8(MinxCPU.BA.B.L, MinxCPU.BA.B.H);
return 8;
case 0x12: // SUB A, #nn
I8A = Fetch8();
MinxCPU.BA.B.L = SUB8(MinxCPU.BA.B.L, I8A);
return 8;
case 0x13: // SUB A, [HL]
MinxCPU.BA.B.L = SUB8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 8;
case 0x14: // SUB A, [N+#nn]
I8A = Fetch8();
MinxCPU.BA.B.L = SUB8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.N.D + I8A));
return 12;
case 0x15: // SUB A, [#nnnn]
I16 = Fetch16();
MinxCPU.BA.B.L = SUB8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16));
return 16;
case 0x16: // SUB A, [X]
MinxCPU.BA.B.L = SUB8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.X.D));
return 8;
case 0x17: // SUB A, [Y]
MinxCPU.BA.B.L = SUB8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 8;
case 0x18: // SBC A, A
MinxCPU.BA.B.L = SBC8(MinxCPU.BA.B.L, MinxCPU.BA.B.L);
return 8;
case 0x19: // SBC A, B
MinxCPU.BA.B.L = SBC8(MinxCPU.BA.B.L, MinxCPU.BA.B.H);
return 8;
case 0x1A: // SBC A, #nn
I8A = Fetch8();
MinxCPU.BA.B.L = SBC8(MinxCPU.BA.B.L, I8A);
return 8;
case 0x1B: // SBC A, [HL]
MinxCPU.BA.B.L = SBC8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 8;
case 0x1C: // SBC A, [N+#nn]
I8A = Fetch8();
MinxCPU.BA.B.L = SBC8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.N.D + I8A));
return 12;
case 0x1D: // SBC A, [#nnnn]
I16 = Fetch16();
MinxCPU.BA.B.L = SBC8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16));
return 16;
case 0x1E: // SBC A, [X]
MinxCPU.BA.B.L = SBC8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.X.D));
return 8;
case 0x1F: // SBC A, [Y]
MinxCPU.BA.B.L = SBC8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 8;
case 0x20: // AND A, A
MinxCPU.BA.B.L = AND8(MinxCPU.BA.B.L, MinxCPU.BA.B.L);
return 8;
case 0x21: // AND A, B
MinxCPU.BA.B.L = AND8(MinxCPU.BA.B.L, MinxCPU.BA.B.H);
return 8;
case 0x22: // AND A, #nn
I8A = Fetch8();
MinxCPU.BA.B.L = AND8(MinxCPU.BA.B.L, I8A);
return 8;
case 0x23: // AND A, [HL]
MinxCPU.BA.B.L = AND8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 8;
case 0x24: // AND A, [N+#nn]
I8A = Fetch8();
MinxCPU.BA.B.L = AND8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.N.D + I8A));
return 12;
case 0x25: // AND A, [#nnnn]
I16 = Fetch16();
MinxCPU.BA.B.L = AND8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16));
return 16;
case 0x26: // AND A, [X]
MinxCPU.BA.B.L = AND8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.X.D));
return 8;
case 0x27: // AND A, [Y]
MinxCPU.BA.B.L = AND8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 8;
case 0x28: // OR A, A
MinxCPU.BA.B.L = OR8(MinxCPU.BA.B.L, MinxCPU.BA.B.L);
return 8;
case 0x29: // OR A, B
MinxCPU.BA.B.L = OR8(MinxCPU.BA.B.L, MinxCPU.BA.B.H);
return 8;
case 0x2A: // OR A, #nn
I8A = Fetch8();
MinxCPU.BA.B.L = OR8(MinxCPU.BA.B.L, I8A);
return 8;
case 0x2B: // OR A, [HL]
MinxCPU.BA.B.L = OR8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 8;
case 0x2C: // OR A, [N+#nn]
I8A = Fetch8();
MinxCPU.BA.B.L = OR8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.N.D + I8A));
return 12;
case 0x2D: // OR A, [#nnnn]
I16 = Fetch16();
MinxCPU.BA.B.L = OR8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16));
return 16;
case 0x2E: // OR A, [X]
MinxCPU.BA.B.L = OR8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.X.D));
return 8;
case 0x2F: // OR A, [Y]
MinxCPU.BA.B.L = OR8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 8;
case 0x30: // CMP A, A
SUB8(MinxCPU.BA.B.L, MinxCPU.BA.B.L);
return 8;
case 0x31: // CMP A, B
SUB8(MinxCPU.BA.B.L, MinxCPU.BA.B.H);
return 8;
case 0x32: // CMP A, #nn
I8A = Fetch8();
SUB8(MinxCPU.BA.B.L, I8A);
return 8;
case 0x33: // CMP A, [HL]
SUB8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 8;
case 0x34: // CMP A, [N+#nn]
I8A = Fetch8();
SUB8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.N.D + I8A));
return 12;
case 0x35: // CMP A, [#nnnn]
I16 = Fetch16();
SUB8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16));
return 16;
case 0x36: // CMP A, [X]
SUB8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.X.D));
return 8;
case 0x37: // CMP A, [Y]
SUB8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 8;
case 0x38: // XOR A, A
MinxCPU.BA.B.L = XOR8(MinxCPU.BA.B.L, MinxCPU.BA.B.L);
return 8;
case 0x39: // XOR A, B
MinxCPU.BA.B.L = XOR8(MinxCPU.BA.B.L, MinxCPU.BA.B.H);
return 8;
case 0x3A: // XOR A, #nn
I8A = Fetch8();
MinxCPU.BA.B.L = XOR8(MinxCPU.BA.B.L, I8A);
return 8;
case 0x3B: // XOR A, [HL]
MinxCPU.BA.B.L = XOR8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 8;
case 0x3C: // XOR A, [N+#nn]
I8A = Fetch8();
MinxCPU.BA.B.L = XOR8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.N.D + I8A));
return 12;
case 0x3D: // XOR A, [#nnnn]
I16 = Fetch16();
MinxCPU.BA.B.L = XOR8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16));
return 16;
case 0x3E: // XOR A, [X]
MinxCPU.BA.B.L = XOR8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.X.D));
return 8;
case 0x3F: // XOR A, [Y]
MinxCPU.BA.B.L = XOR8(MinxCPU.BA.B.L, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 8;
case 0x40: // MOV A, A
return 4;
case 0x41: // MOV A, B
MinxCPU.BA.B.L = MinxCPU.BA.B.H;
return 4;
case 0x42: // MOV A, L
MinxCPU.BA.B.L = MinxCPU.HL.B.L;
return 4;
case 0x43: // MOV A, H
MinxCPU.BA.B.L = MinxCPU.HL.B.H;
return 4;
case 0x44: // MOV A, [N+#nn]
I8A = Fetch8();
MinxCPU.BA.B.L = MinxCPU_OnRead(1, MinxCPU.N.D + I8A);
return 12;
case 0x45: // MOV A, [HL]
MinxCPU.BA.B.L = MinxCPU_OnRead(1, MinxCPU.HL.D);
return 8;
case 0x46: // MOV A, [X]
MinxCPU.BA.B.L = MinxCPU_OnRead(1, MinxCPU.X.D);
return 8;
case 0x47: // MOV A, [Y]
MinxCPU.BA.B.L = MinxCPU_OnRead(1, MinxCPU.Y.D);
return 8;
case 0x48: // MOV B, A
MinxCPU.BA.B.H = MinxCPU.BA.B.L;
return 4;
case 0x49: // MOV B, B
return 4;
case 0x4A: // MOV B, L
MinxCPU.BA.B.H = MinxCPU.HL.B.L;
return 4;
case 0x4B: // MOV B, H
MinxCPU.BA.B.H = MinxCPU.HL.B.H;
return 4;
case 0x4C: // MOV B, [N+#nn]
I8A = Fetch8();
MinxCPU.BA.B.H = MinxCPU_OnRead(1, MinxCPU.N.D + I8A);
return 12;
case 0x4D: // MOV B, [HL]
MinxCPU.BA.B.H = MinxCPU_OnRead(1, MinxCPU.HL.D);
return 8;
case 0x4E: // MOV B, [X]
MinxCPU.BA.B.H = MinxCPU_OnRead(1, MinxCPU.X.D);
return 8;
case 0x4F: // MOV B, [Y]
MinxCPU.BA.B.H = MinxCPU_OnRead(1, MinxCPU.Y.D);
return 8;
case 0x50: // MOV L, A
MinxCPU.HL.B.L = MinxCPU.BA.B.L;
return 4;
case 0x51: // MOV L, B
MinxCPU.HL.B.L = MinxCPU.BA.B.H;
return 4;
case 0x52: // MOV L, L
return 4;
case 0x53: // MOV L, H
MinxCPU.HL.B.L = MinxCPU.HL.B.H;
return 4;
case 0x54: // MOV L, [N+#nn]
I8A = Fetch8();
MinxCPU.HL.B.L = MinxCPU_OnRead(1, MinxCPU.N.D + I8A);
return 12;
case 0x55: // MOV L, [HL]
MinxCPU.HL.B.L = MinxCPU_OnRead(1, MinxCPU.HL.D);
return 8;
case 0x56: // MOV L, [X]
MinxCPU.HL.B.L = MinxCPU_OnRead(1, MinxCPU.X.D);
return 8;
case 0x57: // MOV L, [Y]
MinxCPU.HL.B.L = MinxCPU_OnRead(1, MinxCPU.Y.D);
return 8;
case 0x58: // MOV H, A
MinxCPU.HL.B.H = MinxCPU.BA.B.L;
return 4;
case 0x59: // MOV H, B
MinxCPU.HL.B.H = MinxCPU.BA.B.H;
return 4;
case 0x5A: // MOV H, L
MinxCPU.HL.B.H = MinxCPU.HL.B.L;
return 4;
case 0x5B: // MOV H, H
return 4;
case 0x5C: // MOV H, [N+#nn]
I8A = Fetch8();
MinxCPU.HL.B.H = MinxCPU_OnRead(1, MinxCPU.N.D + I8A);
return 12;
case 0x5D: // MOV H, [HL]
MinxCPU.HL.B.H = MinxCPU_OnRead(1, MinxCPU.HL.D);
return 8;
case 0x5E: // MOV H, [X]
MinxCPU.HL.B.H = MinxCPU_OnRead(1, MinxCPU.X.D);
return 8;
case 0x5F: // MOV H, [Y]
MinxCPU.HL.B.H = MinxCPU_OnRead(1, MinxCPU.Y.D);
return 8;
case 0x60: // MOV [X], A
MinxCPU_OnWrite(1, MinxCPU.X.D, MinxCPU.BA.B.L);
return 8;
case 0x61: // MOV [X], B
MinxCPU_OnWrite(1, MinxCPU.X.D, MinxCPU.BA.B.H);
return 8;
case 0x62: // MOV [X], L
MinxCPU_OnWrite(1, MinxCPU.X.D, MinxCPU.HL.B.L);
return 8;
case 0x63: // MOV [X], H
MinxCPU_OnWrite(1, MinxCPU.X.D, MinxCPU.HL.B.H);
return 8;
case 0x64: // MOV [X], [N+#nn]
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.X.D, MinxCPU_OnRead(1, MinxCPU.N.D + I8A));
return 16;
case 0x65: // MOV [X], [HL]
MinxCPU_OnWrite(1, MinxCPU.X.D, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 12;
case 0x66: // MOV [X], [X]
MinxCPU_OnWrite(1, MinxCPU.X.D, MinxCPU_OnRead(1, MinxCPU.X.D));
return 12;
case 0x67: // MOV [X], [Y]
MinxCPU_OnWrite(1, MinxCPU.X.D, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 12;
case 0x68: // MOV [HL], A
MinxCPU_OnWrite(1, MinxCPU.HL.D, MinxCPU.BA.B.L);
return 8;
case 0x69: // MOV [HL], B
MinxCPU_OnWrite(1, MinxCPU.HL.D, MinxCPU.BA.B.H);
return 8;
case 0x6A: // MOV [HL], L
MinxCPU_OnWrite(1, MinxCPU.HL.D, MinxCPU.HL.B.L);
return 8;
case 0x6B: // MOV [HL], H
MinxCPU_OnWrite(1, MinxCPU.HL.D, MinxCPU.HL.B.H);
return 8;
case 0x6C: // MOV [HL], [N+#nn]
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.HL.D, MinxCPU_OnRead(1, MinxCPU.N.D + I8A));
return 16;
case 0x6D: // MOV [HL], [HL]
MinxCPU_OnWrite(1, MinxCPU.HL.D, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 12;
case 0x6E: // MOV [HL], [X]
MinxCPU_OnWrite(1, MinxCPU.HL.D, MinxCPU_OnRead(1, MinxCPU.X.D));
return 12;
case 0x6F: // MOV [HL], [Y]
MinxCPU_OnWrite(1, MinxCPU.HL.D, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 12;
case 0x70: // MOV [Y], A
MinxCPU_OnWrite(1, MinxCPU.Y.D, MinxCPU.BA.B.L);
return 8;
case 0x71: // MOV [Y], B
MinxCPU_OnWrite(1, MinxCPU.Y.D, MinxCPU.BA.B.H);
return 8;
case 0x72: // MOV [Y], L
MinxCPU_OnWrite(1, MinxCPU.Y.D, MinxCPU.HL.B.L);
return 8;
case 0x73: // MOV [Y], H
MinxCPU_OnWrite(1, MinxCPU.Y.D, MinxCPU.HL.B.H);
return 8;
case 0x74: // MOV [Y], [N+#nn]
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.Y.D, MinxCPU_OnRead(1, MinxCPU.N.D + I8A));
return 16;
case 0x75: // MOV [Y], [HL]
MinxCPU_OnWrite(1, MinxCPU.Y.D, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 12;
case 0x76: // MOV [Y], [X]
MinxCPU_OnWrite(1, MinxCPU.Y.D, MinxCPU_OnRead(1, MinxCPU.X.D));
return 12;
case 0x77: // MOV [Y], [Y]
MinxCPU_OnWrite(1, MinxCPU.Y.D, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 12;
case 0x78: // MOV [N+#nn], A
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, MinxCPU.BA.B.L);
return 8;
case 0x79: // MOV [N+#nn], B
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, MinxCPU.BA.B.H);
return 8;
case 0x7A: // MOV [N+#nn], L
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, MinxCPU.HL.B.L);
return 8;
case 0x7B: // MOV [N+#nn], H
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, MinxCPU.HL.B.H);
return 8;
case 0x7C: // NOTHING #nn
I8A = Fetch8();
return 64;
case 0x7D: // MOV [N+#nn], [HL]
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, MinxCPU_OnRead(1, MinxCPU.HL.D));
return 16;
case 0x7E: // MOV [N+#nn], [X]
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, MinxCPU_OnRead(1, MinxCPU.X.D));
return 16;
case 0x7F: // MOV [N+#nn], [Y]
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, MinxCPU_OnRead(1, MinxCPU.Y.D));
return 16;
case 0x80: // INC A
MinxCPU.BA.B.L = INC8(MinxCPU.BA.B.L);
return 8;
case 0x81: // INC B
MinxCPU.BA.B.H = INC8(MinxCPU.BA.B.H);
return 8;
case 0x82: // INC L
MinxCPU.HL.B.L = INC8(MinxCPU.HL.B.L);
return 8;
case 0x83: // INC H
MinxCPU.HL.B.H = INC8(MinxCPU.HL.B.H);
return 8;
case 0x84: // INC N
MinxCPU.N.B.H = INC8(MinxCPU.N.B.H);
return 8;
case 0x85: // INC [N+#nn]
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, INC8(MinxCPU_OnRead(1, MinxCPU.N.D + I8A)));
return 16;
case 0x86: // INC [HL]
MinxCPU_OnWrite(1, MinxCPU.HL.D, INC8(MinxCPU_OnRead(1, MinxCPU.HL.D)));
return 12;
case 0x87: // INC SP
MinxCPU.SP.W.L = INC16(MinxCPU.SP.W.L);
return 8;
case 0x88: // DEC A
MinxCPU.BA.B.L = DEC8(MinxCPU.BA.B.L);
return 8;
case 0x89: // DEC B
MinxCPU.BA.B.H = DEC8(MinxCPU.BA.B.H);
return 8;
case 0x8A: // DEC L
MinxCPU.HL.B.L = DEC8(MinxCPU.HL.B.L);
return 8;
case 0x8B: // DEC H
MinxCPU.HL.B.H = DEC8(MinxCPU.HL.B.H);
return 8;
case 0x8C: // DEC N
MinxCPU.N.B.H = DEC8(MinxCPU.N.B.H);
return 8;
case 0x8D: // DEC [N+#nn]
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, DEC8(MinxCPU_OnRead(1, MinxCPU.N.D + I8A)));
return 16;
case 0x8E: // DEC [HL]
MinxCPU_OnWrite(1, MinxCPU.HL.D, DEC8(MinxCPU_OnRead(1, MinxCPU.HL.D)));
return 12;
case 0x8F: // DEC SP
MinxCPU.SP.W.L = DEC16(MinxCPU.SP.W.L);
return 8;
case 0x90: // INC BA
MinxCPU.BA.W.L = INC16(MinxCPU.BA.W.L);
return 8;
case 0x91: // INC HL
MinxCPU.HL.W.L = INC16(MinxCPU.HL.W.L);
return 8;
case 0x92: // INC X
MinxCPU.X.W.L = INC16(MinxCPU.X.W.L);
return 8;
case 0x93: // INC Y
MinxCPU.Y.W.L = INC16(MinxCPU.Y.W.L);
return 8;
case 0x94: // TST A, B
AND8(MinxCPU.BA.B.L, MinxCPU.BA.B.H);
return 8;
case 0x95: // TST [HL], #nn
I8A = Fetch8();
AND8(MinxCPU_OnRead(1, MinxCPU.HL.D), I8A);
return 12;
case 0x96: // TST A, #nn
I8A = Fetch8();
AND8(MinxCPU.BA.B.L, I8A);
return 8;
case 0x97: // TST B, #nn
I8A = Fetch8();
AND8(MinxCPU.BA.B.H, I8A);
return 8;
case 0x98: // DEC BA
MinxCPU.BA.W.L = DEC16(MinxCPU.BA.W.L);
return 8;
case 0x99: // DEC HL
MinxCPU.HL.W.L = DEC16(MinxCPU.HL.W.L);
return 8;
case 0x9A: // DEC X
MinxCPU.X.W.L = DEC16(MinxCPU.X.W.L);
return 8;
case 0x9B: // DEC Y
MinxCPU.Y.W.L = DEC16(MinxCPU.Y.W.L);
return 8;
case 0x9C: // AND F, #nn
I8A = Fetch8();
MinxCPU.F = MinxCPU.F & I8A;
MinxCPU_OnIRQHandle(MinxCPU.F, MinxCPU.Shift_U);
return 12;
case 0x9D: // OR F, #nn
I8A = Fetch8();
MinxCPU.F = MinxCPU.F | I8A;
MinxCPU_OnIRQHandle(MinxCPU.F, MinxCPU.Shift_U);
return 12;
case 0x9E: // XOR F, #nn
I8A = Fetch8();
MinxCPU.F = MinxCPU.F ^ I8A;
MinxCPU_OnIRQHandle(MinxCPU.F, MinxCPU.Shift_U);
return 12;
case 0x9F: // MOV F, #nn
I8A = Fetch8();
MinxCPU.F = I8A;
MinxCPU_OnIRQHandle(MinxCPU.F, MinxCPU.Shift_U);
return 12;
case 0xA0: // PUSH BA
PUSH(MinxCPU.BA.B.H);
PUSH(MinxCPU.BA.B.L);
return 16;
case 0xA1: // PUSH HL
PUSH(MinxCPU.HL.B.H);
PUSH(MinxCPU.HL.B.L);
return 16;
case 0xA2: // PUSH X
PUSH(MinxCPU.X.B.H);
PUSH(MinxCPU.X.B.L);
return 16;
case 0xA3: // PUSH Y
PUSH(MinxCPU.Y.B.H);
PUSH(MinxCPU.Y.B.L);
return 16;
case 0xA4: // PUSH N
PUSH(MinxCPU.N.B.H);
return 12;
case 0xA5: // PUSH I
PUSH(MinxCPU.HL.B.I);
return 12;
case 0xA6: // PUSHX
PUSH(MinxCPU.X.B.I);
PUSH(MinxCPU.Y.B.I);
return 16;
case 0xA7: // PUSH F
PUSH(MinxCPU.F);
return 12;
case 0xA8: // POP BA
MinxCPU.BA.B.L = POP();
MinxCPU.BA.B.H = POP();
return 12;
case 0xA9: // POP HL
MinxCPU.HL.B.L = POP();
MinxCPU.HL.B.H = POP();
return 12;
case 0xAA: // POP X
MinxCPU.X.B.L = POP();
MinxCPU.X.B.H = POP();
return 12;
case 0xAB: // POP Y
MinxCPU.Y.B.L = POP();
MinxCPU.Y.B.H = POP();
return 12;
case 0xAC: // POP N
MinxCPU.N.B.H = POP();
return 8;
case 0xAD: // POP I
MinxCPU.HL.B.I = POP();
MinxCPU.N.B.I = MinxCPU.HL.B.I;
return 8;
case 0xAE: // POPX
MinxCPU.Y.B.I = POP();
MinxCPU.X.B.I = POP();
return 12;
case 0xAF: // POP F
MinxCPU.F = POP();
MinxCPU_OnIRQHandle(MinxCPU.F, MinxCPU.Shift_U);
return 8;
case 0xB0: // MOV A, #nn
I8A = Fetch8();
MinxCPU.BA.B.L = I8A;
return 8;
case 0xB1: // MOV B, #nn
I8A = Fetch8();
MinxCPU.BA.B.H = I8A;
return 8;
case 0xB2: // MOV L, #nn
I8A = Fetch8();
MinxCPU.HL.B.L = I8A;
return 8;
case 0xB3: // MOV H, #nn
I8A = Fetch8();
MinxCPU.HL.B.H = I8A;
return 8;
case 0xB4: // MOV N, #nn
I8A = Fetch8();
MinxCPU.N.B.H = I8A;
return 8;
case 0xB5: // MOV [HL], #nn
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.HL.D, I8A);
return 12;
case 0xB6: // MOV [X], #nn
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.X.D, I8A);
return 12;
case 0xB7: // MOV [Y], #nn
I8A = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.Y.D, I8A);
return 12;
case 0xB8: // MOV BA, [#nnnn]
I16 = Fetch16();
MinxCPU.BA.B.L = MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16++);
MinxCPU.BA.B.H = MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16);
return 20;
case 0xB9: // MOV HL, [#nnnn]
I16 = Fetch16();
MinxCPU.HL.B.L = MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16++);
MinxCPU.HL.B.H = MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16);
return 20;
case 0xBA: // MOV X, [#nnnn]
I16 = Fetch16();
MinxCPU.X.B.L = MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16++);
MinxCPU.X.B.H = MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16);
return 20;
case 0xBB: // MOV Y, [#nnnn]
I16 = Fetch16();
MinxCPU.Y.B.L = MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16++);
MinxCPU.Y.B.H = MinxCPU_OnRead(1, (MinxCPU.HL.B.I << 16) | I16);
return 20;
case 0xBC: // MOV [#nnnn], BA
I16 = Fetch16();
MinxCPU_OnWrite(1, (MinxCPU.HL.B.I << 16) | I16++, MinxCPU.BA.B.L);
MinxCPU_OnWrite(1, (MinxCPU.HL.B.I << 16) | I16, MinxCPU.BA.B.H);
return 20;
case 0xBD: // MOV [#nnnn], HL
I16 = Fetch16();
MinxCPU_OnWrite(1, (MinxCPU.HL.B.I << 16) | I16++, MinxCPU.HL.B.L);
MinxCPU_OnWrite(1, (MinxCPU.HL.B.I << 16) | I16, MinxCPU.HL.B.H);
return 20;
case 0xBE: // MOV [#nnnn], X
I16 = Fetch16();
MinxCPU_OnWrite(1, (MinxCPU.HL.B.I << 16) | I16++, MinxCPU.X.B.L);
MinxCPU_OnWrite(1, (MinxCPU.HL.B.I << 16) | I16, MinxCPU.X.B.H);
return 20;
case 0xBF: // MOV [#nnnn], Y
I16 = Fetch16();
MinxCPU_OnWrite(1, (MinxCPU.HL.B.I << 16) | I16++, MinxCPU.Y.B.L);
MinxCPU_OnWrite(1, (MinxCPU.HL.B.I << 16) | I16, MinxCPU.Y.B.H);
return 20;
case 0xC0: // ADD BA, #nnnn
I16 = Fetch16();
MinxCPU.BA.W.L = ADD16(MinxCPU.BA.W.L, I16);
return 12;
case 0xC1: // ADD HL, #nnnn
I16 = Fetch16();
MinxCPU.HL.W.L = ADD16(MinxCPU.HL.W.L, I16);
return 12;
case 0xC2: // ADD X, #nnnn
I16 = Fetch16();
MinxCPU.X.W.L = ADD16(MinxCPU.X.W.L, I16);
return 12;
case 0xC3: // ADD Y, #nnnn
I16 = Fetch16();
MinxCPU.Y.W.L = ADD16(MinxCPU.Y.W.L, I16);
return 12;
case 0xC4: // MOV BA, #nnnn
I16 = Fetch16();
MinxCPU.BA.W.L = I16;
return 12;
case 0xC5: // MOV HL, #nnnn
I16 = Fetch16();
MinxCPU.HL.W.L = I16;
return 12;
case 0xC6: // MOV X, #nnnn
I16 = Fetch16();
MinxCPU.X.W.L = I16;
return 12;
case 0xC7: // MOV Y, #nnnn
I16 = Fetch16();
MinxCPU.Y.W.L = I16;
return 12;
case 0xC8: // XCHG BA, HL
I16 = MinxCPU.HL.W.L;
MinxCPU.HL.W.L = MinxCPU.BA.W.L;
MinxCPU.BA.W.L = I16;
return 12;
case 0xC9: // XCHG BA, X
I16 = MinxCPU.X.W.L;
MinxCPU.X.W.L = MinxCPU.BA.W.L;
MinxCPU.BA.W.L = I16;
return 12;
case 0xCA: // XCHG BA, Y
I16 = MinxCPU.Y.W.L;
MinxCPU.Y.W.L = MinxCPU.BA.W.L;
MinxCPU.BA.W.L = I16;
return 12;
case 0xCB: // XCHG BA, SP
I16 = MinxCPU.SP.W.L;
MinxCPU.SP.W.L = MinxCPU.BA.W.L;
MinxCPU.BA.W.L = I16;
return 12;
case 0xCC: // XCHG A, B
I8A = MinxCPU.BA.B.H;
MinxCPU.BA.B.H = MinxCPU.BA.B.L;
MinxCPU.BA.B.L = I8A;
return 8;
case 0xCD: // XCHG A, [HL]
I8A = MinxCPU_OnRead(1, MinxCPU.HL.D);
MinxCPU_OnWrite(1, MinxCPU.HL.D, MinxCPU.BA.B.L);
MinxCPU.BA.B.L = I8A;
return 12;
case 0xCE: // Expand 0
return MinxCPU_ExecCE();
case 0xCF: // Expand 1
return MinxCPU_ExecCF();
case 0xD0: // SUB BA, #nnnn
I16 = Fetch16();
MinxCPU.BA.W.L = SUB16(MinxCPU.BA.W.L, I16);
return 12;
case 0xD1: // SUB HL, #nnnn
I16 = Fetch16();
MinxCPU.HL.W.L = SUB16(MinxCPU.HL.W.L, I16);
return 12;
case 0xD2: // SUB X, #nnnn
I16 = Fetch16();
MinxCPU.X.W.L = SUB16(MinxCPU.X.W.L, I16);
return 12;
case 0xD3: // SUB Y, #nnnn
I16 = Fetch16();
MinxCPU.Y.W.L = SUB16(MinxCPU.Y.W.L, I16);
return 12;
case 0xD4: // CMP BA, #nnnn
I16 = Fetch16();
SUB16(MinxCPU.BA.W.L, I16);
return 12;
case 0xD5: // CMP HL, #nnnn
I16 = Fetch16();
SUB16(MinxCPU.HL.W.L, I16);
return 12;
case 0xD6: // CMP X, #nnnn
I16 = Fetch16();
SUB16(MinxCPU.X.W.L, I16);
return 12;
case 0xD7: // CMP Y, #nnnn
I16 = Fetch16();
SUB16(MinxCPU.Y.W.L, I16);
return 12;
case 0xD8: // AND [N+#nn], #nn
I8A = Fetch8();
I8B = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, AND8(MinxCPU_OnRead(1, MinxCPU.N.D + I8A), I8B));
return 20;
case 0xD9: // OR [N+#nn], #nn
I8A = Fetch8();
I8B = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, OR8(MinxCPU_OnRead(1, MinxCPU.N.D + I8A), I8B));
return 20;
case 0xDA: // XOR [N+#nn], #nn
I8A = Fetch8();
I8B = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, XOR8(MinxCPU_OnRead(1, MinxCPU.N.D + I8A), I8B));
return 20;
case 0xDB: // CMP [N+#nn], #nn
I8A = Fetch8();
I8B = Fetch8();
SUB8(MinxCPU_OnRead(1, MinxCPU.N.D + I8A), I8B);
return 16;
case 0xDC: // TST [N+#nn], #nn
I8A = Fetch8();
I8B = Fetch8();
AND8(MinxCPU_OnRead(1, MinxCPU.N.D + I8A), I8B);
return 16;
case 0xDD: // MOV [N+#nn], #nn
I8A = Fetch8();
I8B = Fetch8();
MinxCPU_OnWrite(1, MinxCPU.N.D + I8A, I8B);
return 16;
case 0xDE: // PACK
MinxCPU.BA.B.L = (MinxCPU.BA.B.L & 0x0F) | (MinxCPU.BA.B.H << 4);
return 8;
case 0xDF: // UNPACK
MinxCPU.BA.B.H = (MinxCPU.BA.B.L >> 4);
MinxCPU.BA.B.L = MinxCPU.BA.B.L & 0x0F;
return 8;
case 0xE0: // CALLC #ss
I8A = Fetch8();
if (MinxCPU.F & MINX_FLAG_CARRY) {
CALLS(S8_TO_16(I8A));
return 20;
}
return 8;
case 0xE1: // CALLNC #ss
I8A = Fetch8();
if (!(MinxCPU.F & MINX_FLAG_CARRY)) {
CALLS(S8_TO_16(I8A));
return 20;
}
return 8;
case 0xE2: // CALLZ #ss
I8A = Fetch8();
if (MinxCPU.F & MINX_FLAG_ZERO) {
CALLS(S8_TO_16(I8A));
return 20;
}
return 8;
case 0xE3: // CALLNZ #ss
I8A = Fetch8();
if (!(MinxCPU.F & MINX_FLAG_ZERO)) {
CALLS(S8_TO_16(I8A));
return 20;
}
return 8;
case 0xE4: // JC #ss
I8A = Fetch8();
if (MinxCPU.F & MINX_FLAG_CARRY) {
JMPS(S8_TO_16(I8A));
}
return 8;
case 0xE5: // JNC #ss
I8A = Fetch8();
if (!(MinxCPU.F & MINX_FLAG_CARRY)) {
JMPS(S8_TO_16(I8A));
}
return 8;
case 0xE6: // JZ #ss
I8A = Fetch8();
if (MinxCPU.F & MINX_FLAG_ZERO) {
JMPS(S8_TO_16(I8A));
}
return 8;
case 0xE7: // JNZ #ss
I8A = Fetch8();
if (!(MinxCPU.F & MINX_FLAG_ZERO)) {
JMPS(S8_TO_16(I8A));
}
return 8;
case 0xE8: // CALLC #ssss
I16 = Fetch16();
if (MinxCPU.F & MINX_FLAG_CARRY) {
CALLS(I16);
return 24;
}
return 12;
case 0xE9: // CALLNC #ssss
I16 = Fetch16();
if (!(MinxCPU.F & MINX_FLAG_CARRY)) {
CALLS(I16);
return 24;
}
return 12;
case 0xEA: // CALLZ #ssss
I16 = Fetch16();
if (MinxCPU.F & MINX_FLAG_ZERO) {
CALLS(I16);
return 24;
}
return 12;
case 0xEB: // CALLNZ #ssss
I16 = Fetch16();
if (!(MinxCPU.F & MINX_FLAG_ZERO)) {
CALLS(I16);
return 24;
}
return 12;
case 0xEC: // JC #ssss
I16 = Fetch16();
if (MinxCPU.F & MINX_FLAG_CARRY) {
JMPS(I16);
}
return 12;
case 0xED: // JNC #ssss
I16 = Fetch16();
if (!(MinxCPU.F & MINX_FLAG_CARRY)) {
JMPS(I16);
}
return 12;
case 0xEE: // JZ #ssss
I16 = Fetch16();
if (MinxCPU.F & MINX_FLAG_ZERO) {
JMPS(I16);
}
return 12;
case 0xEF: // JNZ #ssss
I16 = Fetch16();
if (!(MinxCPU.F & MINX_FLAG_ZERO)) {
JMPS(I16);
}
return 12;
case 0xF0: // CALL #ss
I8A = Fetch8();
CALLS(S8_TO_16(I8A));
return 20;
case 0xF1: // JMP #ss
I8A = Fetch8();
JMPS(S8_TO_16(I8A));
return 8;
case 0xF2: // CALL #ssss
I16 = Fetch16();
CALLS(I16);
return 24;
case 0xF3: // JMP #ssss
I16 = Fetch16();
JMPS(I16);
return 12;
case 0xF4: // JMP HL
JMPU(MinxCPU.HL.W.L);
return 8;
case 0xF5: // JDBNZ #ss
I8A = Fetch8();
JDBNZ(S8_TO_16(I8A));
return 16;
case 0xF6: // SWAP A
MinxCPU.BA.B.L = SWAP(MinxCPU.BA.B.L);
return 8;
case 0xF7: // SWAP [HL]
MinxCPU_OnWrite(1, MinxCPU.HL.D, SWAP(MinxCPU_OnRead(1, MinxCPU.HL.D)));
return 12;
case 0xF8: // RET
RET();
return 16;
case 0xF9: // RETI
RETI();
return 16;
case 0xFA: // RETSKIP
RET();
MinxCPU.PC.W.L = MinxCPU.PC.W.L + 2;
return 16;
case 0xFB: // CALL [#nnnn]
I16 = Fetch16();
CALLX(I16);
return 20;
case 0xFC: // CINT #nn
I16 = Fetch8();
CALLI(I16);
return 20;
case 0xFD: // JINT #nn
I16 = Fetch8();
JMPI(I16);
return 8;
case 0xFE: // CRASH
MinxCPU_OnException(EXCEPTION_CRASH_INSTRUCTION, 0xFE);
return 4;
case 0xFF: // NOP
return 8;
default:
MinxCPU_OnException(EXCEPTION_UNKNOWN_INSTRUCTION, MinxCPU.IR);
return 4;
}
}
