//------------------------------------------------------------------------------ /// Configures PWM clocks A & B to run at the given frequencies. This function /// finds the best MCK divisor and prescaler values automatically. /// \param clka Desired clock A frequency (0 if not used). /// \param clkb Desired clock B frequency (0 if not used). /// \param mck Master clock frequency. //------------------------------------------------------------------------------ void PWMC_ConfigureClocks(unsigned int clka, unsigned int clkb, unsigned int mck) { unsigned int mode = 0; unsigned int result; // Clock A if (clka != 0) { result = FindClockConfiguration(clka, mck); ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clka); mode |= result; } // Clock B if (clkb != 0) { result = FindClockConfiguration(clkb, mck); ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", clkb); mode |= (result << 16); } // Configure clocks TRACE_DEBUG("Setting PWMC_MR = 0x%08X\n\r", mode); AT91C_BASE_PWMC->PWMC_MR = mode; }
/** * \brief Configures PWM clocks A & B to run at the given frequencies. * * This function finds the best MCK divisor and prescaler values automatically. * * \param clka Desired clock A frequency (0 if not used). * \param clkb Desired clock B frequency (0 if not used). * \param mck Master clock frequency. */ void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck) { uint32_t mode = 0; uint32_t result; /* Clock A */ if (clka != 0) { result = FindClockConfiguration(clka, mck); assert( result != 0 ) ; mode |= result; } /* Clock B */ if (clkb != 0) { result = FindClockConfiguration(clkb, mck); assert( result != 0 ) ; mode |= (result << 16); } /* Configure clocks */ TRACE_DEBUG( "Setting PWM_CLK = 0x%08X\n\r", mode ) ; PWM->PWM_CLK = mode; }
/** * \brief Configures PWM clocks A & B to run at the given frequencies. * * This function finds the best MCK divisor and prescaler values automatically. * * \param clka Desired clock A frequency (0 if not used). * \param clkb Desired clock B frequency (0 if not used). * \param mck Master clock frequency. */ void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck) { uint32_t mode = 0; uint32_t result; /* Clock A */ if (clka != 0) { result = FindClockConfiguration(clka, mck); ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", (unsigned int)clka); mode |= result; } /* Clock B */ if (clkb != 0) { result = FindClockConfiguration(clkb, mck); ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", (unsigned int)clkb); mode |= (result << 16); } /* Configure clocks */ TRACE_DEBUG("Setting PWM_CLK = 0x%08X\n\r", mode); PWM->PWM_CLK = mode; }