STATIC
EFI_STATUS
InitializeSataController (
EFI_PHYSICAL_ADDRESS AhciBaseAddr,
UINTN SataPortCount,
UINTN StartPort
)
{
UINT8 SataChPerSerdes;
UINT32 PortNum;
UINT32 EvenPort;
UINT32 OddPort;
SataChPerSerdes = FixedPcdGet8 (PcdSataNumChPerSerdes);
//
// SataChPerSerdes must be 2 for the Even/Odd logic in the loop below
//
ASSERT(SataChPerSerdes == 2);
for (PortNum = StartPort; PortNum < SataPortCount + StartPort; PortNum += SataChPerSerdes) {
EvenPort = (UINT32)(FixedPcdGet32 (PcdSataPortMode) >> (PortNum * 2)) & 3;
OddPort = (UINT32)(FixedPcdGet32 (PcdSataPortMode) >> ((PortNum+1) * 2)) & 3;
SataPhyInit (PortNum / SataChPerSerdes, EvenPort, OddPort);
}
//
// Reset SATA controller
//
ResetSataController (AhciBaseAddr);
//
// Set SATA capabilities
//
SetSataCapabilities (AhciBaseAddr);
//
// Set and intialize the Sata ports
//
InitializeSataPorts (AhciBaseAddr, SataPortCount);
return RegisterNonDiscoverableMmioDevice (
NonDiscoverableDeviceTypeAhci,
NonDiscoverableDeviceDmaTypeCoherent,
NULL,
NULL,
1,
AhciBaseAddr, SIZE_4KB);
}
EFI_STATUS
EFIAPI
StyxSataPlatformDxeEntryPoint (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
UINT32 PortNum;
EFI_STATUS Status;
//
// Perform SATA workarounds
//
for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata0PortCount); PortNum++) {
SetCwMinSata0 (PortNum);
}
Status = InitializeSataController (FixedPcdGet32(PcdSata0CtrlAxiSlvPort),
FixedPcdGet8(PcdSata0PortCount), 0);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "%a: failed to initialize primary SATA controller!\n",
__FUNCTION__));
return Status;
}
for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata0PortCount); PortNum++) {
SetPrdSingleSata0 (PortNum);
}
//
// Ignore the second SATA controller on pre-B1 silicon
//
if ((PcdGet32 (PcdSocCpuId) & STYX_SOC_VERSION_MASK) < STYX_SOC_VERSION_B1) {
return EFI_SUCCESS;
}
if (FixedPcdGet8(PcdSata1PortCount) > 0) {
for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata1PortCount); PortNum++) {
SetCwMinSata1 (PortNum);
}
Status = InitializeSataController (FixedPcdGet32(PcdSata1CtrlAxiSlvPort),
FixedPcdGet8(PcdSata1PortCount),
FixedPcdGet8(PcdSata0PortCount));
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "%a: failed to initialize secondary SATA controller!\n",
__FUNCTION__));
} else {
for (PortNum = 0; PortNum < FixedPcdGet8(PcdSata1PortCount); PortNum++) {
SetPrdSingleSata1 (PortNum);
}
}
}
return EFI_SUCCESS;
}
STATIC
VOID
SetSocIdStatus (
IN VOID *Fdt
)
{
UINT32 SocId;
BOOLEAN IsRevB1;
BOOLEAN DisableXgbeSmmus;
SocId = PcdGet32 (PcdSocCpuId);
IsRevB1 = (SocId & STYX_SOC_VERSION_MASK) >= STYX_SOC_VERSION_B1;
SetDeviceStatus (Fdt, "sata@e0d00000",
IsRevB1 && FixedPcdGet8 (PcdSata1PortCount) > 0);
SetDeviceStatus (Fdt, "gpio@e0020000", IsRevB1);
SetDeviceStatus (Fdt, "gpio@e0030000", IsRevB1);
SetDeviceStatus (Fdt, "gwdt@e0bb0000", IsRevB1);
#if DO_KCS
SetDeviceStatus (Fdt, "kcs@e0010000", IsRevB1);
#else
SetDeviceStatus (Fdt, "kcs@e0010000", FALSE);
#endif
if (!PcdGetBool (PcdEnableSmmus)) {
DisableSmmu (Fdt, "iommu-map", "/smb/smmu@e0a00000", "/smb/pcie@f0000000");
DisableSmmu (Fdt, "iommus", "/smb/smmu@e0200000", "/smb/sata@e0300000");
}
if (!PcdGetBool (PcdEnableSmmus) || !IsRevB1 || FixedPcdGet8 (PcdSata1PortCount) == 0) {
DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/sata@e0d00000");
}
#if DO_XGBE
DisableXgbeSmmus = !PcdGetBool (PcdEnableSmmus);
#else
DisableXgbeSmmus = TRUE;
#endif
if (DisableXgbeSmmus) {
DisableSmmu (Fdt, "iommus", "/smb/smmu@e0600000", "/smb/xgmac@e0700000");
DisableSmmu (Fdt, "iommus", "/smb/smmu@e0800000", "/smb/xgmac@e0900000");
}
}
/**
Do the platform init, can be customized by OEM/IBV
Possible things that can be done in PlatformBootManagerBeforeConsole:
> Update console variable: 1. include hot-plug devices;
> 2. Clear ConIn and add SOL for AMT
> Register new Driver#### or Boot####
> Register new Key####: e.g.: F12
> Signal ReadyToLock event
> Authentication action: 1. connect Auth devices;
> 2. Identify auto logon user.
**/
VOID
EFIAPI
PlatformBootManagerBeforeConsole (
VOID
)
{
//
// Signal EndOfDxe PI Event
//
EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);
//
// Locate the PCI root bridges and make the PCI bus driver connect each,
// non-recursively. This will produce a number of child handles with PciIo on
// them.
//
FilterAndProcess (&gEfiPciRootBridgeIoProtocolGuid, NULL, Connect);
//
// Find all display class PCI devices (using the handles from the previous
// step), and connect them non-recursively. This should produce a number of
// child handles with GOPs on them.
//
FilterAndProcess (&gEfiPciIoProtocolGuid, IsPciDisplay, Connect);
//
// Now add the device path of all handles with GOP on them to ConOut and
// ErrOut.
//
FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput);
//
// Add the hardcoded short-form USB keyboard device path to ConIn.
//
EfiBootManagerUpdateConsoleVariable (ConIn,
(EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL);
//
// Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.
//
ASSERT (FixedPcdGet8 (PcdDefaultTerminalType) == 4);
CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid);
EfiBootManagerUpdateConsoleVariable (ConIn,
(EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
EfiBootManagerUpdateConsoleVariable (ConOut,
(EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
EfiBootManagerUpdateConsoleVariable (ErrOut,
(EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
//
// Register platform-specific boot options and keyboard shortcuts.
//
PlatformRegisterOptionsAndKeys ();
}
/**
Initialize controllers that must setup in the normal world
This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
in the PEI phase.
**/
RETURN_STATUS
ArmPlatformInitialize (
IN UINTN MpId
)
{
RETURN_STATUS Status;
UINT64 BaudRate;
UINT32 ReceiveFifoDepth;
EFI_PARITY_TYPE Parity;
UINT8 DataBits;
EFI_STOP_BITS_TYPE StopBits;
Status = RETURN_SUCCESS;
//
// Initialize the Serial Debug UART
//
if (FixedPcdGet64 (PcdSerialDbgRegisterBase)) {
ReceiveFifoDepth = 0; // Use the default value for FIFO depth
Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);
BaudRate = (UINTN)FixedPcdGet64 (PcdSerialDbgUartBaudRate);
Status = PL011UartInitializePort (
(UINTN)FixedPcdGet64 (PcdSerialDbgRegisterBase),
FixedPcdGet32 (PcdSerialDbgUartClkInHz),
&BaudRate,
&ReceiveFifoDepth,
&Parity,
&DataBits,
&StopBits
);
}
return Status;
}
/**
Constructor for the Shell AcpiView Command library.
Install the handlers for acpiview UEFI Shell command.
@param ImageHandle The image handle of the process.
@param SystemTable The EFI System Table pointer.
@retval EFI_SUCCESS The Shell command handlers were installed
successfully.
@retval EFI_DEVICE_ERROR Hii package failed to install.
*/
EFI_STATUS
EFIAPI
UefiShellAcpiViewCommandLibConstructor (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
gShellAcpiViewHiiHandle = NULL;
// Check Shell Profile Debug1 bit of the profiles mask
if ((FixedPcdGet8 (PcdShellProfileMask) & BIT1) == 0) {
return EFI_SUCCESS;
}
Status = RegisterAllParsers ();
if (EFI_ERROR (Status)) {
Print (L"acpiview: Error failed to register parser.\n");
return Status;
}
gShellAcpiViewHiiHandle = HiiAddPackages (
&gShellAcpiViewHiiGuid,
gImageHandle,
UefiShellAcpiViewCommandLibStrings,
NULL
);
if (gShellAcpiViewHiiHandle == NULL) {
return EFI_DEVICE_ERROR;
}
// Install our Shell command handler
ShellCommandRegisterCommandName (
L"acpiview",
ShellCommandRunAcpiView,
ShellCommandGetManFileNameAcpiView,
0,
L"acpiview",
TRUE,
gShellAcpiViewHiiHandle,
STRING_TOKEN (STR_GET_HELP_ACPIVIEW)
);
return EFI_SUCCESS;
}
STATIC
UINT64
SerialPortGetBaseAddress (
VOID
)
{
UINT64 BaudRate;
UINT32 ReceiveFifoDepth;
EFI_PARITY_TYPE Parity;
UINT8 DataBits;
EFI_STOP_BITS_TYPE StopBits;
VOID *DeviceTreeBase;
INT32 Node, Prev;
INT32 Len;
CONST CHAR8 *Compatible;
CONST CHAR8 *NodeStatus;
CONST CHAR8 *CompatibleItem;
CONST UINT64 *RegProperty;
UINTN UartBase;
RETURN_STATUS Status;
DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeInitialBaseAddress);
if ((DeviceTreeBase == NULL) || (fdt_check_header (DeviceTreeBase) != 0)) {
return 0;
}
//
// Enumerate all FDT nodes looking for a PL011 and capture its base address
//
for (Prev = 0;; Prev = Node) {
Node = fdt_next_node (DeviceTreeBase, Prev, NULL);
if (Node < 0) {
break;
}
Compatible = fdt_getprop (DeviceTreeBase, Node, "compatible", &Len);
if (Compatible == NULL) {
continue;
}
//
// Iterate over the NULL-separated items in the compatible string
//
for (CompatibleItem = Compatible; CompatibleItem < Compatible + Len;
CompatibleItem += 1 + AsciiStrLen (CompatibleItem)) {
if (AsciiStrCmp (CompatibleItem, "arm,pl011") == 0) {
NodeStatus = fdt_getprop (DeviceTreeBase, Node, "status", &Len);
if (NodeStatus != NULL && AsciiStrCmp (NodeStatus, "okay") != 0) {
continue;
}
RegProperty = fdt_getprop (DeviceTreeBase, Node, "reg", &Len);
if (Len != 16) {
return 0;
}
UartBase = (UINTN)fdt64_to_cpu (ReadUnaligned64 (RegProperty));
BaudRate = (UINTN)FixedPcdGet64 (PcdUartDefaultBaudRate);
ReceiveFifoDepth = 0; // Use the default value for Fifo depth
Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
Status = PL011UartInitializePort (
UartBase,
FixedPcdGet32 (PL011UartClkInHz),
&BaudRate,
&ReceiveFifoDepth,
&Parity,
&DataBits,
&StopBits
);
if (!EFI_ERROR (Status)) {
return UartBase;
}
}
}
}
return 0;
}
//
// VENDOR_DEVICE_PATH SerialDxe
//
{
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },
SERIAL_DXE_FILE_GUID
},
//
// UART_DEVICE_PATH Uart
//
{
{ MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
0, // Reserved
FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits
FixedPcdGet8 (PcdUartDefaultParity), // Parity
FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits
},
//
// VENDOR_DEFINED_DEVICE_PATH Vt100
//
{
{
MESSAGING_DEVICE_PATH, MSG_VENDOR_DP,
DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH)
},
EFI_VT_100_GUID
},
/**
Entry point to the C language phase of SEC. After the SEC assembly
code has initialized some temporary memory and set up the stack,
the control is transferred to this function.
@param[in] SizeOfRam Size of the temporary memory available for use.
@param[in] TempRamBase Base address of temporary ram
@param[in] BootFirmwareVolume Base address of the Boot Firmware Volume.
@param[in] PeiCore PeiCore entry point.
@param[in] BootLoaderStack BootLoader stack.
@param[in] ApiIdx the index of API.
@return This function never returns.
**/
VOID
EFIAPI
SecStartup (
IN UINT32 SizeOfRam,
IN UINT32 TempRamBase,
IN VOID *BootFirmwareVolume,
IN PEI_CORE_ENTRY PeiCore,
IN UINT32 BootLoaderStack,
IN UINT32 ApiIdx
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
IA32_DESCRIPTOR IdtDescriptor;
SEC_IDT_TABLE IdtTableInStack;
UINT32 Index;
FSP_GLOBAL_DATA PeiFspData;
UINT64 ExceptionHandler;
UINTN IdtSize;
//
// Process all libraries constructor function linked to SecCore.
//
ProcessLibraryConstructorList ();
//
// Initialize floating point operating environment
// to be compliant with UEFI spec.
//
InitializeFloatingPointUnits ();
// |-------------------|---->
// |Idt Table |
// |-------------------|
// |PeiService Pointer | PeiStackSize
// |-------------------|
// | |
// | Stack |
// |-------------------|---->
// | |
// | |
// | Heap | PeiTemporayRamSize
// | |
// | |
// |-------------------|----> TempRamBase
IdtTableInStack.PeiService = NULL;
AsmReadIdtr (&IdtDescriptor);
if (IdtDescriptor.Base == 0) {
ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate);
for (Index = 0; Index < FixedPcdGet8(PcdFspMaxInterruptSupported); Index ++) {
CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&ExceptionHandler, sizeof (UINT64));
}
IdtSize = sizeof (IdtTableInStack.IdtTable);
} else {
IdtSize = IdtDescriptor.Limit + 1;
if (IdtSize > sizeof (IdtTableInStack.IdtTable)) {
//
// ERROR: IDT table size from boot loader is larger than FSP can support, DeadLoop here!
//
CpuDeadLoop();
} else {
CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *) IdtDescriptor.Base, IdtSize);
}
}
IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;
IdtDescriptor.Limit = (UINT16)(IdtSize - 1);
AsmWriteIdtr (&IdtDescriptor);
//
// Initialize the global FSP data region
//
FspGlobalDataInit (&PeiFspData, BootLoaderStack, (UINT8)ApiIdx);
//
// Update the base address and length of Pei temporary memory
//
SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;
SecCoreData.BootFirmwareVolumeSize = (UINT32)((EFI_FIRMWARE_VOLUME_HEADER *)BootFirmwareVolume)->FvLength;
SecCoreData.TemporaryRamBase = (VOID*)(UINTN) TempRamBase;
SecCoreData.TemporaryRamSize = SizeOfRam;
SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100;
SecCoreData.StackBase = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;
DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));
DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeSize - 0x%x\n", SecCoreData.BootFirmwareVolumeSize));
DEBUG ((DEBUG_INFO, "Fsp TemporaryRamBase - 0x%x\n", SecCoreData.TemporaryRamBase));
DEBUG ((DEBUG_INFO, "Fsp TemporaryRamSize - 0x%x\n", SecCoreData.TemporaryRamSize));
DEBUG ((DEBUG_INFO, "Fsp PeiTemporaryRamBase - 0x%x\n", SecCoreData.PeiTemporaryRamBase));
DEBUG ((DEBUG_INFO, "Fsp PeiTemporaryRamSize - 0x%x\n", SecCoreData.PeiTemporaryRamSize));
DEBUG ((DEBUG_INFO, "Fsp StackBase - 0x%x\n", SecCoreData.StackBase));
DEBUG ((DEBUG_INFO, "Fsp StackSize - 0x%x\n", SecCoreData.StackSize));
//
// Call PeiCore Entry
//
PeiCore (&SecCoreData, mPeiSecPlatformInformationPpi);
//
// Should never be here
//
CpuDeadLoop ();
}
/**
Return the Virtual Memory Map of your platform
This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU
on your platform.
@param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR
describing a Physical-to-Virtual Memory
mapping. This array must be ended by a
zero-filled entry
**/
VOID
ArmPlatformGetVirtualMemoryMap (
IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
)
{
ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
ASSERT (VirtualMemoryMap != NULL);
VirtualMemoryTable = AllocatePages (
EFI_SIZE_TO_PAGES (
sizeof (ARM_MEMORY_REGION_DESCRIPTOR)
* MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS
)
);
if (VirtualMemoryTable == NULL) {
DEBUG ((EFI_D_ERROR, "%a: Error: Failed AllocatePages()\n", __FUNCTION__));
return;
}
// System DRAM
VirtualMemoryTable[0].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
VirtualMemoryTable[0].VirtualBase = VirtualMemoryTable[0].PhysicalBase;
VirtualMemoryTable[0].Length = PcdGet64 (PcdSystemMemorySize);
VirtualMemoryTable[0].Attributes = DDR_ATTRIBUTES_CACHED;
DEBUG ((EFI_D_INFO, "%a: Dumping System DRAM Memory Map:\n"
"\tPhysicalBase: 0x%lX\n"
"\tVirtualBase: 0x%lX\n"
"\tLength: 0x%lX\n",
__FUNCTION__,
VirtualMemoryTable[0].PhysicalBase,
VirtualMemoryTable[0].VirtualBase,
VirtualMemoryTable[0].Length));
// Peripheral space before DRAM
VirtualMemoryTable[1].PhysicalBase = 0x0;
VirtualMemoryTable[1].VirtualBase = 0x0;
VirtualMemoryTable[1].Length = VirtualMemoryTable[0].PhysicalBase;
VirtualMemoryTable[1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Peripheral space after DRAM
VirtualMemoryTable[2].PhysicalBase = VirtualMemoryTable[0].Length + VirtualMemoryTable[1].Length;
VirtualMemoryTable[2].VirtualBase = VirtualMemoryTable[2].PhysicalBase;
VirtualMemoryTable[2].Length = MIN (1ULL << FixedPcdGet8 (PcdPrePiCpuMemorySize),
ArmGetPhysAddrTop ()) -
VirtualMemoryTable[2].PhysicalBase;
VirtualMemoryTable[2].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Remap the FD region as normal executable memory
VirtualMemoryTable[3].PhysicalBase = PcdGet64 (PcdFdBaseAddress);
VirtualMemoryTable[3].VirtualBase = VirtualMemoryTable[3].PhysicalBase;
VirtualMemoryTable[3].Length = FixedPcdGet32 (PcdFdSize);
VirtualMemoryTable[3].Attributes = DDR_ATTRIBUTES_CACHED;
// End of Table
ZeroMem (&VirtualMemoryTable[4], sizeof (ARM_MEMORY_REGION_DESCRIPTOR));
*VirtualMemoryMap = VirtualMemoryTable;
}
