void FuartInterrupt(void)
{
int status;
uint8_t rxData;
status = FuartIOctl(UART_IOCTL_RXSTAT_GET,0);
if(status & 0x1E){
/*
* clear FIFO before clear other flags
*/
FuartIOctl(UART_IOCTL_RXFIFO_CLR,0);
/*
* clear other error flags
*/
FuartIOctl(UART_IOCTL_RXINT_CLR,0);
}
if(status & 0x01)
{
//or,you can receive them in the interrupt directly
while(FuartRecvByte(&rxData) > 0){
ring_buffer_write( uart_interfaces[ AP80xx_FUART ].rx_buffer, &rxData,1 );
}
FuartIOctl(UART_IOCTL_RXINT_CLR,0);
// Notify thread if sufficient data are available
if ( ( uart_interfaces[ 0 ].rx_size > 0 ) &&
( ring_buffer_used_space( uart_interfaces[ AP80xx_FUART ].rx_buffer ) >= uart_interfaces[ AP80xx_FUART ].rx_size ) )
{
#ifndef NO_MICO_RTOS
mico_rtos_set_semaphore( &uart_interfaces[ AP80xx_FUART ].rx_complete );
#else
uart_interfaces[ AP80xx_FUART ].rx_complete = true;
#endif
uart_interfaces[ AP80xx_FUART ].rx_size = 0;
}
}
if(FuartIOctl(UART_IOCTL_TXSTAT_GET,0) & 0x01)
{
FuartIOctl(UART_IOCTL_TXINT_CLR,0);
#ifndef NO_MICO_RTOS
mico_rtos_set_semaphore( &uart_interfaces[ AP80xx_FUART ].tx_complete );
#else
uart_interfaces[ AP80xx_FUART ].tx_complete = true;
#endif
}
}
OSStatus internal_uart_init( mico_uart_t uart, const mico_uart_config_t* config, ring_buffer_t* optional_rx_buffer )
{
OSStatus err = kNoErr;
require_action(optional_rx_buffer!=NULL, exit, err = kParamErr);
#ifndef NO_MICO_RTOS
mico_rtos_init_semaphore(&uart_interfaces[uart].tx_complete, 1);
mico_rtos_init_semaphore(&uart_interfaces[uart].rx_complete, 1);
mico_rtos_init_mutex(&uart_interfaces[uart].tx_mutex);
#else
uart_interfaces[uart].tx_complete = false;
uart_interfaces[uart].rx_complete = false;
#endif
if(uart_mapping[uart].uart == FUART){
if( uart_mapping[uart].pin_tx->port == GPIOA && uart_mapping[uart].pin_tx->pin == 1 )
GpioFuartTxIoConfig(0);
else if( uart_mapping[uart].pin_tx->port == GPIOB && uart_mapping[uart].pin_tx->pin == 7 )
GpioFuartTxIoConfig(1);
else if( uart_mapping[uart].pin_tx->port == GPIOC && uart_mapping[uart].pin_tx->pin == 3 )
GpioFuartTxIoConfig(2);
else
return kUnsupportedErr;
if( uart_mapping[uart].pin_rx->port == GPIOA && uart_mapping[uart].pin_rx->pin == 1 )
GpioFuartRxIoConfig(0);
else if( uart_mapping[uart].pin_rx->port == GPIOB && uart_mapping[uart].pin_rx->pin == 6 )
GpioFuartRxIoConfig(1);
else if( uart_mapping[uart].pin_rx->port == GPIOC && uart_mapping[uart].pin_rx->pin == 4 )
GpioFuartRxIoConfig(2);
else
return kUnsupportedErr;
require_action( config->flow_control == FLOW_CONTROL_DISABLED, exit, err = kUnsupportedErr );
err = FuartInit(config->baud_rate, config->data_width + 5, config->parity, config->stop_bits + 1);
require_noerr(err, exit);
FuartIOctl(UART_IOCTL_RXINT_SET, 1);
if (optional_rx_buffer != NULL){
/* Note that the ring_buffer should've been initialised first */
uart_interfaces[uart].rx_buffer = optional_rx_buffer;
uart_interfaces[uart].rx_size = 0;
//platform_uart_receive_bytes( uart, optional_rx_buffer->buffer, optional_rx_buffer->size, 0 );
}
}else if(uart_mapping[uart].uart == BUART){
if( uart_mapping[uart].pin_tx->port == GPIOA && uart_mapping[uart].pin_tx->pin == 16 )
GpioBuartTxIoConfig(0);
else if( uart_mapping[uart].pin_tx->port == GPIOA && uart_mapping[uart].pin_tx->pin == 25 )
GpioBuartTxIoConfig(1);
else if( uart_mapping[uart].pin_tx->port == GPIOB && uart_mapping[uart].pin_tx->pin == 9 )
GpioBuartTxIoConfig(2);
else if( uart_mapping[uart].pin_tx->port == GPIOB && uart_mapping[uart].pin_tx->pin == 28 )
GpioBuartTxIoConfig(3);
else
return kUnsupportedErr;
if( uart_mapping[uart].pin_rx->port == GPIOA && uart_mapping[uart].pin_rx->pin == 13 )
GpioBuartRxIoConfig(0);
else if( uart_mapping[uart].pin_rx->port == GPIOA && uart_mapping[uart].pin_rx->pin == 24 )
GpioBuartRxIoConfig(1);
else if( uart_mapping[uart].pin_rx->port == GPIOB && uart_mapping[uart].pin_rx->pin == 8 )
GpioBuartRxIoConfig(2);
else if( uart_mapping[uart].pin_rx->port == GPIOB && uart_mapping[uart].pin_rx->pin == 29 )
GpioBuartRxIoConfig(3);
else
return kUnsupportedErr;
require_action( config->flow_control == FLOW_CONTROL_DISABLED, exit, err = kUnsupportedErr );
err = BuartExFifoInit( (32-2-1)*1024, 1024*2, 1024, 1);
require_noerr(err, exit);
err = BuartInit(config->baud_rate, config->data_width + 5, config->parity, config->stop_bits + 1);
require_noerr(err, exit);
BuartIOctl(UART_IOCTL_RXINT_SET, 1);
BuartIOctl(UART_IOCTL_TXINT_SET, 1);
}else
return kUnsupportedErr;
exit:
return err;
}
OSStatus platform_uart_init( platform_uart_driver_t* driver, const platform_uart_t* peripheral, const platform_uart_config_t* config, ring_buffer_t* optional_ring_buffer )
{
OSStatus err = kNoErr;
platform_mcu_powersave_disable();
require_action_quiet( ( driver != NULL ) && ( peripheral != NULL ) && ( config != NULL ), exit, err = kParamErr);
driver->rx_size = 0;
driver->tx_size = 0;
driver->last_transmit_result = kNoErr;
driver->last_receive_result = kNoErr;
driver->peripheral = (platform_uart_t*)peripheral;
driver->buart_fifo_head = 0;
#ifndef NO_MICO_RTOS
mico_rtos_init_semaphore( &driver->tx_complete, 1 );
mico_rtos_init_semaphore( &driver->rx_complete, 1 );
mico_rtos_init_mutex ( &driver->tx_mutex );
#else
driver->tx_complete = false;
driver->rx_complete = false;
#endif
if ( peripheral->uart == FUART ){
if( peripheral->pin_tx->port == GPIOA && peripheral->pin_tx->pin == 1 )
GpioFuartTxIoConfig(0);
else if( peripheral->pin_tx->port == GPIOB && peripheral->pin_tx->pin == 7 )
GpioFuartTxIoConfig(1);
else if( peripheral->pin_tx->port == GPIOC && peripheral->pin_tx->pin == 3 )
GpioFuartTxIoConfig(2);
else
return kUnsupportedErr;
if( peripheral->pin_rx->port == GPIOA && peripheral->pin_rx->pin == 1 )
GpioFuartRxIoConfig(0);
else if( peripheral->pin_rx->port == GPIOB && peripheral->pin_rx->pin == 6 )
GpioFuartRxIoConfig(1);
else if( peripheral->pin_rx->port == GPIOC && peripheral->pin_rx->pin == 4 )
GpioFuartRxIoConfig(2);
else
return kUnsupportedErr;
require_action( config->flow_control == FLOW_CONTROL_DISABLED, exit, err = kUnsupportedErr );
err = FuartInit(config->baud_rate, config->data_width + 5, config->parity, config->stop_bits + 1);
require_noerr(err, exit);
FuartIOctl(UART_IOCTL_RXINT_SET, 1);
if (optional_ring_buffer != NULL){
/* Note that the ring_buffer should've been initialised first */
driver->rx_buffer = optional_ring_buffer;
driver->rx_size = 0;
//platform_uart_receive_bytes( uart, optional_rx_buffer->buffer, optional_rx_buffer->size, 0 );
}
}else if( peripheral->uart == BUART ){
if( peripheral->pin_tx->port == GPIOA && peripheral->pin_tx->pin == 16 )
GpioBuartTxIoConfig(0);
else if( peripheral->pin_tx->port == GPIOA && peripheral->pin_tx->pin == 25 )
GpioBuartTxIoConfig(1);
else if( peripheral->pin_tx->port == GPIOB && peripheral->pin_tx->pin == 9 )
GpioBuartTxIoConfig(2);
else if( peripheral->pin_tx->port == GPIOB && peripheral->pin_tx->pin == 28 )
GpioBuartTxIoConfig(3);
else
return kUnsupportedErr;
if( peripheral->pin_rx->port == GPIOA && peripheral->pin_rx->pin == 13 )
GpioBuartRxIoConfig(0);
else if( peripheral->pin_rx->port == GPIOA && peripheral->pin_rx->pin == 24 )
GpioBuartRxIoConfig(1);
else if( peripheral->pin_rx->port == GPIOB && peripheral->pin_rx->pin == 8 )
GpioBuartRxIoConfig(2);
else if( peripheral->pin_rx->port == GPIOB && peripheral->pin_rx->pin == 29 )
GpioBuartRxIoConfig(3);
else
return kUnsupportedErr;
require_action( config->flow_control == FLOW_CONTROL_DISABLED, exit, err = kUnsupportedErr );
err = BuartExFifoInit( BUART_FIFO_START, BUART_RX_FIFO_SIZE, BUART_TX_FIFO_SIZE, 1 );
require_noerr(err, exit);
err = BuartInit( config->baud_rate, config->data_width + 5, config->parity, config->stop_bits + 1 );
require_noerr(err, exit);
BuartIOctl( UART_IOCTL_TXINT_SET, 1 );
}else
return kUnsupportedErr;
exit:
return err;
}
