uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
struct GB* gb = (struct GB*) cpu->master;
struct GBMemory* memory = &gb->memory;
switch (address >> 12) {
case GB_REGION_CART_BANK0:
case GB_REGION_CART_BANK0 + 1:
case GB_REGION_CART_BANK0 + 2:
case GB_REGION_CART_BANK0 + 3:
return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
case GB_REGION_CART_BANK1:
case GB_REGION_CART_BANK1 + 1:
case GB_REGION_CART_BANK1 + 2:
case GB_REGION_CART_BANK1 + 3:
return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
case GB_REGION_VRAM:
case GB_REGION_VRAM + 1:
return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
case GB_REGION_EXTERNAL_RAM:
case GB_REGION_EXTERNAL_RAM + 1:
if (memory->rtcAccess) {
return memory->rtcRegs[memory->activeRtcReg];
} else if (memory->sramAccess) {
return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
} else if (memory->mbcType == GB_MBC7) {
return GBMBC7Read(memory, address);
} else if (memory->mbcType == GB_HuC3) {
return 0x01; // TODO: Is this supposed to be the current SRAM bank?
}
return 0xFF;
case GB_REGION_WORKING_RAM_BANK0:
case GB_REGION_WORKING_RAM_BANK0 + 2:
return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
case GB_REGION_WORKING_RAM_BANK1:
return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
default:
if (address < GB_BASE_OAM) {
return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
}
if (address < GB_BASE_UNUSABLE) {
if (gb->video.mode < 2) {
return gb->video.oam.raw[address & 0xFF];
}
return 0xFF;
}
if (address < GB_BASE_IO) {
mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
return 0xFF;
}
if (address < GB_BASE_HRAM) {
return GBIORead(gb, address & (GB_SIZE_IO - 1));
}
if (address < GB_BASE_IE) {
return memory->hram[address & GB_SIZE_HRAM];
}
return GBIORead(gb, REG_IE);
}
}
uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
struct GB* gb = (struct GB*) cpu->master;
struct GBMemory* memory = &gb->memory;
if (gb->memory.dmaRemaining) {
const enum GBBus* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
enum GBBus dmaBus = block[memory->dmaSource >> 13];
enum GBBus accessBus = block[address >> 13];
if (dmaBus != GB_BUS_CPU && dmaBus == accessBus) {
return 0xFF;
}
if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
return 0xFF;
}
}
switch (address >> 12) {
case GB_REGION_CART_BANK0:
case GB_REGION_CART_BANK0 + 1:
case GB_REGION_CART_BANK0 + 2:
case GB_REGION_CART_BANK0 + 3:
return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
case GB_REGION_CART_BANK1:
case GB_REGION_CART_BANK1 + 1:
case GB_REGION_CART_BANK1 + 2:
case GB_REGION_CART_BANK1 + 3:
return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
case GB_REGION_VRAM:
case GB_REGION_VRAM + 1:
return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
case GB_REGION_EXTERNAL_RAM:
case GB_REGION_EXTERNAL_RAM + 1:
if (memory->rtcAccess) {
return memory->rtcRegs[memory->activeRtcReg];
} else if (memory->mbcRead) {
return memory->mbcRead(memory, address);
} else if (memory->sramAccess && memory->sram) {
return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
} else if (memory->mbcType == GB_HuC3) {
return 0x01; // TODO: Is this supposed to be the current SRAM bank?
}
return 0xFF;
case GB_REGION_WORKING_RAM_BANK0:
case GB_REGION_WORKING_RAM_BANK0 + 2:
return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
case GB_REGION_WORKING_RAM_BANK1:
return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
default:
if (address < GB_BASE_OAM) {
return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
}
if (address < GB_BASE_UNUSABLE) {
if (gb->video.mode < 2) {
return gb->video.oam.raw[address & 0xFF];
}
return 0xFF;
}
if (address < GB_BASE_IO) {
mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
return 0xFF;
}
if (address < GB_BASE_HRAM) {
return GBIORead(gb, address & (GB_SIZE_IO - 1));
}
if (address < GB_BASE_IE) {
return memory->hram[address & GB_SIZE_HRAM];
}
return GBIORead(gb, REG_IE);
}
}