/* Determine whether the given cache is enabled. */
int
frv_cache_enabled (FRV_CACHE *cache)
{
SIM_CPU *current_cpu = cache->cpu;
int hsr0 = GET_HSR0 ();
if (GET_HSR0_ICE (hsr0) && cache == CPU_INSN_CACHE (current_cpu))
return 1;
if (GET_HSR0_DCE (hsr0) && cache == CPU_DATA_CACHE (current_cpu))
return 1;
return 0;
}
USI
frvbf_read_imem_USI (SIM_CPU *current_cpu, PCADDR vpc)
{
USI hsr0;
vpc = check_insn_read_address (current_cpu, vpc, 3);
hsr0 = GET_HSR0 ();
if (GET_HSR0_ICE (hsr0))
{
FRV_CACHE *cache;
USI value;
/* We don't want this to show up in the cache statistics. That read
is done in frvbf_simulate_insn_prefetch. So read the cache or memory
passively here. */
cache = CPU_INSN_CACHE (current_cpu);
if (frv_cache_read_passive_SI (cache, vpc, &value))
return value;
}
return sim_core_read_unaligned_4 (current_cpu, vpc, read_map, vpc);
}
