VOID RT30xx_ChipAGCInit(
IN PRTMP_ADAPTER pAd,
IN UCHAR BandWidth)
{
UCHAR R66 = 0x30;
if (pAd->LatchRfRegs.Channel <= 14)
{ /* BG band*/
/* Gary was verified Amazon AP and find that RT307x has BBP_R66 invalid default value */
if (IS_RT3070(pAd)||IS_RT3090(pAd) || IS_RT3390(pAd))
{
R66 = 0x1C + 2*GET_LNA_GAIN(pAd);
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
}
}
else
{
/* A band */
if (BandWidth == BW_20)
{
R66 = (UCHAR)(0x32 + (GET_LNA_GAIN(pAd)*5)/3);
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
}
#ifdef DOT11_N_SUPPORT
else
{
R66 = (UCHAR)(0x3A + (GET_LNA_GAIN(pAd)*5)/3);
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
}
#endif // DOT11_N_SUPPORT //
}
}
VOID RT28xxATERxVGAInit(
IN PRTMP_ADAPTER pAd)
{
PATE_INFO pATEInfo = &(pAd->ate);
UCHAR R66;
CHAR LNAGain = GET_LNA_GAIN(pAd);
if (pATEInfo->Channel <= 14)
{
/* BG band */
R66 = (UCHAR)(0x2E + LNAGain);
}
else
{
/* A band */
if (pATEInfo->TxWI.BW == BW_20)
{
/* A band, BW == 20 */
R66 = (UCHAR)(0x32 + (LNAGain*5)/3);
}
else
{
/* A band, BW == 40 */
R66 = (UCHAR)(0x3A + (LNAGain*5)/3);
}
}
ATEBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
return;
}
char ConvertToRssi(struct rt_rtmp_adapter *pAd, char Rssi, u8 RssiNumber)
{
u8 RssiOffset, LNAGain;
/* Rssi equals to zero should be an invalid value */
if (Rssi == 0)
return -99;
LNAGain = GET_LNA_GAIN(pAd);
if (pAd->LatchRfRegs.Channel > 14) {
if (RssiNumber == 0)
RssiOffset = pAd->ARssiOffset0;
else if (RssiNumber == 1)
RssiOffset = pAd->ARssiOffset1;
else
RssiOffset = pAd->ARssiOffset2;
} else {
if (RssiNumber == 0)
RssiOffset = pAd->BGRssiOffset0;
else if (RssiNumber == 1)
RssiOffset = pAd->BGRssiOffset1;
else
RssiOffset = pAd->BGRssiOffset2;
}
return (-12 - RssiOffset - LNAGain - Rssi);
}
CHAR ConvertToRssi(RTMP_ADAPTER *pAd, CHAR Rssi, UCHAR rssi_idx)
{
UCHAR RssiOffset, LNAGain;
/* Rssi equals to zero or rssi_idx larger than 3 should be an invalid value*/
if (Rssi == 0 || rssi_idx >= 3)
return -99;
LNAGain = GET_LNA_GAIN(pAd);
if (pAd->LatchRfRegs.Channel > 14)
RssiOffset = pAd->ARssiOffset[rssi_idx];
else
RssiOffset = pAd->BGRssiOffset[rssi_idx];
#ifdef RT65xx
/*
Recommended by CSD team:
2.4G : RSSI_report = RSSI_bpp + EEPROM_0x46[15:8 or 7:0] - EEPROM_0x44[7:0]
5G : RSSI_report = RSSI_bbp + EEPROM_0x4A[15:8 or 7:0] - EEPROM_0x44 or 0x48 or 0x4c[15:8]
*/
if (IS_RT65XX(pAd))
return (Rssi + RssiOffset - LNAGain);
else
#endif /* RT65xx */
return (-12 - RssiOffset - LNAGain - Rssi);
}
static UCHAR ChipAGCAdjust(
IN PRTMP_ADAPTER pAd,
IN CHAR Rssi,
IN UCHAR OrigR66Value)
{
UCHAR R66 = OrigR66Value;
CHAR lanGain = GET_LNA_GAIN(pAd);
if (pAd->LatchRfRegs.Channel <= 14)
{ /*BG band*/
R66 = 0x2E + lanGain;
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
R66 += 0x10;
}
else
{ /*A band*/
if (pAd->CommonCfg.BBPCurrentBW == BW_20)
R66 = 0x32 + (lanGain * 5) / 3;
else
R66 = 0x3A + (lanGain * 5) / 3;
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
R66 += 0x10;
}
if (OrigR66Value != R66)
rtmp_bbp_set_agc(pAd, R66, RX_CHAIN_ALL);
return R66;
}
static VOID Default_ChipAGCInit(RTMP_ADAPTER *pAd, UCHAR BandWidth)
{
UCHAR R66 = 0x30, lan_gain;
lan_gain = GET_LNA_GAIN(pAd);
if (pAd->LatchRfRegs.Channel <= 14)
{ // BG band
{
R66 = 0x2E + lan_gain;
}
}
else
{ //A band
{
if (BandWidth == BW_20)
R66 = (UCHAR)(0x32 + (lan_gain * 5) / 3);
#ifdef DOT11_N_SUPPORT
else
R66 = (UCHAR)(0x3A + (lan_gain * 5) / 3);
#endif // DOT11_N_SUPPORT //
}
}
rtmp_bbp_set_agc(pAd, R66, RX_CHAIN_ALL);
}
CHAR ConvertToRssi(
IN PRTMP_ADAPTER pAd,
IN CHAR Rssi,
IN UCHAR RssiNumber)
{
UCHAR RssiOffset, LNAGain;
// Rssi equals to zero should be an invalid value
if (Rssi == 0)
return -99;
LNAGain = GET_LNA_GAIN(pAd);
if (pAd->LatchRfRegs.Channel > 14)
{
if (RssiNumber == 0)
RssiOffset = pAd->ARssiOffset0;
else if (RssiNumber == 1)
RssiOffset = pAd->ARssiOffset1;
else
RssiOffset = pAd->ARssiOffset2;
}
else
{
if (RssiNumber == 0)
RssiOffset = pAd->BGRssiOffset0;
else if (RssiNumber == 1)
RssiOffset = pAd->BGRssiOffset1;
else
RssiOffset = pAd->BGRssiOffset2;
}
return (-12 - RssiOffset - LNAGain - Rssi);
}
CHAR ConvertToRssi(RTMP_ADAPTER *pAd, CHAR Rssi, UCHAR rssi_idx)
{
UCHAR RssiOffset, LNAGain;
CHAR BaseVal;
/* Rssi equals to zero or rssi_idx larger than 3 should be an invalid value*/
if (Rssi == 0 || rssi_idx >= 3)
return -99;
LNAGain = GET_LNA_GAIN(pAd);
if (pAd->LatchRfRegs.Channel > 14)
RssiOffset = pAd->ARssiOffset[rssi_idx];
else
RssiOffset = pAd->BGRssiOffset[rssi_idx];
BaseVal = -12;
#ifdef RT6352
if (IS_RT6352(pAd))
BaseVal = -2;
#endif /* RT6352 */
#ifdef RT65xx
/*
Recommended by CSD team about MT76x0:
SW/QA owners should read the "external-LNA gain" and "RSSI OFFSET" content in EEPROM as "SIGNED".
2.4G : RSSI_report = RSSI_bpp + EEPROM_0x46[15:8 or 7:0] - EEPROM_0x44[7:0]
5G : RSSI_report = RSSI_bbp + EEPROM_0x4A[15:8 or 7:0] - EEPROM_0x44 or 0x48 or 0x4c[15:8]
*/
if (IS_MT76x0(pAd))
return (Rssi + (CHAR)RssiOffset - (CHAR)LNAGain);
if (IS_MT76x2(pAd)) {
CHAR extra_gain = 0;
if (LNAGain & 0x80) {
if (LNAGain == 0xFF)
LNAGain = 0;
else
LNAGain &= 0x7F;
extra_gain = LNAGain;
} else
extra_gain = 0 - (CHAR)LNAGain;
if (is_external_lna_mode(pAd, pAd->CommonCfg.Channel) == TRUE)
extra_gain = LNAGain = 0;
if (pAd->LatchRfRegs.Channel > 14)
return (Rssi + pAd->ARssiOffset[rssi_idx] - extra_gain);
else
return (Rssi + pAd->BGRssiOffset[rssi_idx] - extra_gain);
}
if (IS_RT8592(pAd))
return (Rssi - LNAGain - RssiOffset);
#endif /* RT65xx */
return (BaseVal - RssiOffset - LNAGain - Rssi);
}
VOID RT35xx_SetAGCInitValue(
IN PRTMP_ADAPTER pAd,
IN UCHAR BandWidth)
{
UCHAR R66 = 0x30;
if (pAd->LatchRfRegs.Channel <= 14)
{ // BG band
R66 = 0x1C + 2*GET_LNA_GAIN(pAd);
RT3572WriteBBPR66(pAd, R66);
}
else
{ //A band
R66 = (UCHAR)(0x22 + (GET_LNA_GAIN(pAd)*5)/3);
RT3572WriteBBPR66(pAd, R66);
}
}
static VOID Default_ChipSwitchChannel(
IN PRTMP_ADAPTER pAd,
IN UCHAR Channel,
IN BOOLEAN bScan)
{
MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_ERROR, ("%s(): dummy channel switch function!\n", __FUNCTION__));
pAd->LatchRfRegs.Channel = Channel;
pAd->hw_cfg.lan_gain = GET_LNA_GAIN(pAd);
}
VOID RT35xx_RxSensitivityTuning(
IN PRTMP_ADAPTER pAd)
{
UCHAR R66;
R66 = 0x26 + GET_LNA_GAIN(pAd);
#ifdef RALINK_ATE
if (ATE_ON(pAd))
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x26 + GET_LNA_GAIN(pAd)));
}
else
#endif /* RALINK_ATE */
#ifdef RT35xx
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
#endif /* RT35xx */
DBGPRINT(RT_DEBUG_TRACE,("turn off R17 tuning, restore to 0x%02x\n", R66));
}
/*
==========================================================================
Description:
dynamic tune BBP R66 to find a balance between sensibility and
noise isolation
IRQL = DISPATCH_LEVEL
==========================================================================
*/
UCHAR RT35xx_ChipAGCAdjust(
IN RTMP_ADAPTER *pAd,
IN CHAR Rssi,
IN UCHAR OrigR66Value)
{
UCHAR R66 = OrigR66Value;
CHAR lanGain = GET_LNA_GAIN(pAd);
if (!(IS_RT3572(pAd) || IS_RT3593(pAd)))
{
DBGPRINT(RT_DEBUG_ERROR, ("RT35xx_ChipAGCAdjust - Mismatch MACVersion = 0x%x \n", pAd->MACVersion));
return R66;
}
if (pAd->LatchRfRegs.Channel <= 14)
{ /*BG band*/
R66 = 0x1C + 2 * lanGain;
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
R66 += 0x20;
}
else
{ /*A band*/
if (pAd->CommonCfg.BBPCurrentBW == BW_20)
{
R66 = 0x32 + (lanGain*5) / 3;
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
R66 += 0x10;
}
else
{
R66 = 0x3A + (lanGain*5)/3;
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
R66 += 0x10;
}
#ifdef RT3593
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) {
RT3593_R66_MID_LOW_SENS_GET(pAd, R66);
} else {
RT3593_R66_NON_MID_LOW_SEMS_GET(pAd, R66);
}
#endif /* RT3593 */
}
if (OrigR66Value != R66)
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
return R66;
}
VOID RT35xx_SetAGCInitValue(
IN PRTMP_ADAPTER pAd,
IN UCHAR BandWidth)
{
UCHAR R66;
CHAR lanGain = GET_LNA_GAIN(pAd);
if (pAd->LatchRfRegs.Channel <= 14)
R66 = 0x1C + 2 * lanGain;
else
R66 = (UCHAR)(0x22 + (lanGain * 5) / 3);
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
}
VOID RT35xx_RxSensitivityTuning(
IN PRTMP_ADAPTER pAd)
{
UCHAR R66;
R66 = 0x26 + GET_LNA_GAIN(pAd);
#ifdef RT35xx
if (IS_RT3572(pAd))
AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL);
#endif /* RT35xx */
DBGPRINT(RT_DEBUG_TRACE,("turn off R17 tuning, restore to 0x%02x\n", R66));
}
static VOID RxSensitivityTuning(RTMP_ADAPTER *pAd)
{
UCHAR R66 = 0x26 + GET_LNA_GAIN(pAd);
#ifdef RALINK_ATE
if (ATE_ON(pAd))
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
}
else
#endif /* RALINK_ATE */
{
rtmp_bbp_set_agc(pAd, R66, RX_CHAIN_ALL);
}
DBGPRINT(RT_DEBUG_TRACE,("turn off R17 tuning, restore to 0x%02x\n", R66));
}
VOID RT30xx_RTMPSetAGCInitValue(
IN PRTMP_ADAPTER pAd,
IN UCHAR BandWidth)
{
UCHAR R66 = 0x30;
if (pAd->LatchRfRegs.Channel <= 14)
{ /* BG band*/
/* Gary was verified Amazon AP and find that RT307x has BBP_R66 invalid default value */
if (IS_RT3070(pAd)||IS_RT3090(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd))
{
R66 = 0x1C + 2*GET_LNA_GAIN(pAd);
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
}
}
}
}
VOID RT35xx_ChipSwitchChannel(
IN PRTMP_ADAPTER pAd,
IN UCHAR Channel,
IN BOOLEAN bScan)
{
CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/
UCHAR index;
UINT32 Value = 0; /*BbpReg, Value;*/
UCHAR RFValue;
UINT32 i = 0;
i = i; /* avoid compile warning */
RFValue = 0;
/* Search Tx power value*/
/*
We can't use ChannelList to search channel, since some central channl's txpowr doesn't list
in ChannelList, so use TxPower array instead.
*/
for (index = 0; index < MAX_NUM_OF_CHANNELS; index++)
{
if (Channel == pAd->TxPower[index].Channel)
{
TxPwer = pAd->TxPower[index].Power;
TxPwer2 = pAd->TxPower[index].Power2;
break;
}
}
if (index == MAX_NUM_OF_CHANNELS)
{
DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel));
}
#ifdef RT35xx
/* 3562:RFIC_3052/ 3062:RFIC_3022 */
if (IS_RT3572(pAd) /*&& (pAd->RfIcType == RFIC_3052)*/)
{
for (index = 0; index < NUM_OF_3572_CHNL; index++)
{
if (Channel == FreqItems3572[index].Channel)
{
/* for 2.4G, restore BBP25, BBP26*/
if (Channel <= 14)
{
BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, pAd->Bbp25);
BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R26, pAd->Bbp26);
}
/* hard code for 5GGhz, Gary 2008-12-10*/
else
{
/* Enable IQ Phase Correction*/
BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x09);
/* IQ Phase correction value*/
BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R26, 0xFF);
}
/* Programming channel parameters*/
RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3572[index].N);
RT30xxWriteRFRegister(pAd, RF_R03, FreqItems3572[index].K);
RT30xxReadRFRegister(pAd, RF_R06, &RFValue);
if (Channel <= 14)
RFValue = (RFValue & 0xF0) | FreqItems3572[index].R | 0x8;
else
RFValue = (RFValue & 0xF0) | FreqItems3572[index].R | 0x4;
RT30xxWriteRFRegister(pAd, RF_R06, RFValue);
/* Pll mode for 2.4G or 5G*/
RT30xxReadRFRegister(pAd, RF_R05, &RFValue);
if (Channel <= 14)
RFValue = (RFValue & 0xF3) | 0x4;
else
RFValue = (RFValue & 0xF3) | 0x8;
RT30xxWriteRFRegister(pAd, RF_R05, RFValue);
/* Set Tx0 Power*/
RT30xxReadRFRegister(pAd, RF_R12, (PUCHAR)&RFValue);
if (Channel <= 14)
RFValue = 0x60 | TxPwer;
else
RFValue = 0xE0 | (TxPwer & 0x3) | ((TxPwer & 0xC) << 1);
RT30xxWriteRFRegister(pAd, RF_R12, RFValue);
/* Set Tx1 Power*/
RT30xxReadRFRegister(pAd, RF_R13, (PUCHAR)&RFValue);
if (Channel <= 14)
RFValue = 0x60 | TxPwer2;
else
RFValue = 0xE0 | (TxPwer2 & 0x3) | ((TxPwer2 & 0xC) << 1);
RT30xxWriteRFRegister(pAd, RF_R13, RFValue);
/* Tx/Rx Stream setting*/
RT30xxReadRFRegister(pAd, RF_R01, (PUCHAR)&RFValue);
RFValue &= 0x03; /*clear bit[7~2]*/
if (pAd->Antenna.field.TxPath == 1)
RFValue |= 0xA0;
else if (pAd->Antenna.field.TxPath == 2)
RFValue |= 0x80;
if (pAd->Antenna.field.RxPath == 1)
RFValue |= 0x50;
else if (pAd->Antenna.field.RxPath == 2)
RFValue |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R01, (UCHAR)RFValue);
/* Set RF offset*/
RT30xxReadRFRegister(pAd, RF_R23, (PUCHAR)&RFValue);
RFValue = (RFValue & 0x80) | pAd->RfFreqOffset;
RT30xxWriteRFRegister(pAd, RF_R23, (UCHAR)RFValue);
/* Set BW*/
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
{
RFValue = pAd->Mlme.CaliBW40RfR24;
/*DISABLE_11N_CHECK(pAd);*/
}
else
{
RFValue = pAd->Mlme.CaliBW20RfR24;
}
/* R24, R31, one is for tx, the other is for rx*/
RT30xxWriteRFRegister(pAd, RF_R24, (UCHAR)RFValue);
RT30xxWriteRFRegister(pAd, RF_R31, (UCHAR)RFValue);
/* Enable RF tuning*/
RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue);
if (Channel <= 14)
/*RFValue = (RFValue & 0x37) | 0xCC;*/
RFValue = 0xd8; /*?? to check 3572?? hardcode*/
else
RFValue = (RFValue & 0x37) | 0x14;
RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue);
/* TSSI_BS*/
RT30xxReadRFRegister(pAd, RF_R09, (PUCHAR)&RFValue);
if (Channel <= 14)
RFValue = 0xC3; /*RFValue = (RFValue & 0xBF) | 0x40;*/
else
RFValue = 0xC0; /*RFValue = (RFValue & 0xBF) | 0x40;*/
RT30xxWriteRFRegister(pAd, RF_R09, (UCHAR)RFValue);
/* Loop filter 1*/
RT30xxWriteRFRegister(pAd, RF_R10, (UCHAR)0xF1);
/* Loop filter 2*/
if (Channel <= 14)
RT30xxWriteRFRegister(pAd, RF_R11, (UCHAR)0xB9);
else
RT30xxWriteRFRegister(pAd, RF_R11, (UCHAR)0x00);
/* tx_mx2_ic*/
if (Channel <= 14)
RT30xxWriteRFRegister(pAd, RF_R15, (UCHAR)0x53);
else
RT30xxWriteRFRegister(pAd, RF_R15, (UCHAR)0x43);
/* tx_mx1_ic*/
/*RT30xxReadRFRegister(pAd, RF_R16, (PUCHAR)&RFValue);*/
if (Channel <= 14)
{
RFValue = 0x4c;
RFValue &= (~0x7); /* clean bit [2:0]*/
RFValue |= pAd->TxMixerGain24G;
}
else
{
RFValue = 0x7a;
RFValue &= (~0x7); /* clean bit [2:0]*/
RFValue |= pAd->TxMixerGain5G;
}
RT30xxWriteRFRegister(pAd, RF_R16, (UCHAR)RFValue);
/* tx_lo1*/
RT30xxWriteRFRegister(pAd, RF_R17, (UCHAR)0x23);
/* tx_lo2*/
RFValue = ((Channel <= 14) ? (0x93) : ((Channel <= 64) ? (0xb7) : ((Channel <= 128) ? (0x74) : (0x72))));
RT30xxWriteRFRegister(pAd, RF_R19, (UCHAR)RFValue);
/* rx_l01*/
RFValue = ((Channel <= 14) ? (0xB3) : ((Channel <= 64) ? (0xF6) : ((Channel <= 128) ? (0xF4) : (0xF3))));
RT30xxWriteRFRegister(pAd, RF_R20, (UCHAR)RFValue);
/* pfd_delay*/
RFValue = ((Channel <= 14) ? (0x15) : ((Channel <= 64) ? (0x3d) : ((Channel <= 128) ? (0x01) : (0x01))));
RT30xxWriteRFRegister(pAd, RF_R25, (UCHAR)RFValue);
/* rx_lo2*/
if (Channel <= 14)
RT30xxWriteRFRegister(pAd, RF_R26, (UCHAR)0x85);
else
RT30xxWriteRFRegister(pAd, RF_R26, (UCHAR)0x87);
/* ldo_rf_vc*/
if (Channel <= 14)
RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)0x00);
else
RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)0x01);
/* drv_cc*/
if (Channel <= 14)
RT30xxWriteRFRegister(pAd, RF_R29, (UCHAR)0x9B);
else
RT30xxWriteRFRegister(pAd, RF_R29, (UCHAR)0x9F);
RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
if (Channel <= 14)
Value = ((Value & 0xFFFF7FFF) | 0x00000080);
else
Value = (Value & 0xFFFF7F7F);
RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
/* Enable RF tuning, this must be in the last*/
RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue);
RFValue = RFValue | 0x1;
RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue);
RTMPusecDelay(2000);
/* latch channel for future usage.*/
pAd->LatchRfRegs.Channel = Channel;
DBGPRINT(RT_DEBUG_TRACE, ("RT35xx: SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
Channel,
pAd->RfIcType,
TxPwer,
TxPwer2,
pAd->Antenna.field.TxPath,
FreqItems3572[index].N,
FreqItems3572[index].K,
FreqItems3572[index].R));
break;
}
}
}
else
#endif /* RT35xx */
{
switch (pAd->RfIcType)
{
default:
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d : unknown RFIC=%d\n",
Channel, pAd->RfIcType));
break;
}
}
/* Change BBP setting during siwtch from a->g, g->a*/
if (Channel <= 14)
{
ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
/* Rx High power VGA offset for LNA select*/
{
if (pAd->NicConfig2.field.ExternalLNAForG)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x04);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
#ifdef RT35xx
if (IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x00);
#endif /* RT35xx */
{
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
#ifdef RT35xx
if (IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x80);
#endif /* RT35xx */
}
else
{
ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/
UINT8 bbpValue;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue. */
/* Set the BBP_R82 value here */
bbpValue = 0xF2;
#ifdef RT35xx
if (IS_RT3572(pAd))
{
/* TODO: check if the BBP_R82 value is the same in both of following cases!!!*/
/* Rx High power VGA offset for LNA select*/
bbpValue = 0x94;
}
#endif /* RT35xx */
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue);
/* Rx High power VGA offset for LNA select*/
if (pAd->NicConfig2.field.ExternalLNAForA)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x02);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R*/
#ifdef RT35xx
if (IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x00);
#endif /* RT35xx */
{
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
#ifdef RT35xx
if (IS_RT3572(pAd))
RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x80);
#endif /* RT35xx */
}
/* R66 should be set according to Channel and use 20MHz when scanning*/
/*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x2E + GET_LNA_GAIN(pAd)));*/
if (bScan)
RTMPSetAGCInitValue(pAd, BW_20);
else
RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW);
/* On 11A, We should delay and wait RF/BBP to be stable*/
/* and the appropriate time should be 1000 micro seconds */
/* 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.*/
RTMPusecDelay(1000);
}
/*
==========================================================================
Description:
AsicSwitchChannel() dedicated for RT28xx ATE.
==========================================================================
*/
VOID RT28xxATEAsicSwitchChannel(
IN PRTMP_ADAPTER pAd)
{
PATE_INFO pATEInfo = &(pAd->ate);
UINT32 Value = 0;
CHAR TxPwer = 0, TxPwer2 = 0;
UCHAR index = 0, BbpValue = 0, Channel = 0;
UINT32 R2 = 0, R3 = DEFAULT_RF_TX_POWER, R4 = 0;
RTMP_RF_REGS *RFRegTable = NULL;
SYNC_CHANNEL_WITH_QA(pATEInfo, &Channel);
/* fill Tx power value */
TxPwer = pATEInfo->TxPower0;
TxPwer2 = pATEInfo->TxPower1;
RFRegTable = RF2850RegTable;
switch (pAd->RfIcType)
{
/* But only 2850 and 2750 support 5.5GHz band... */
case RFIC_2820:
case RFIC_2850:
case RFIC_2720:
case RFIC_2750:
for (index = 0; index < NUM_OF_2850_CHNL; index++)
{
if (Channel == RFRegTable[index].Channel)
{
R2 = RFRegTable[index].R2;
/* If TX path is 1, bit 14 = 1. */
if (pAd->Antenna.field.TxPath == 1)
{
R2 |= 0x4000;
}
if (pAd->Antenna.field.TxPath == 2)
{
if (pATEInfo->TxAntennaSel == 1)
{
/* If TX Antenna select is 1 , bit 14 = 1; Disable Ant 2 */
R2 |= 0x4000;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
BbpValue &= 0xE7; /* 11100111B */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
}
else if (pATEInfo->TxAntennaSel == 2)
{
/* If TX Antenna select is 2 , bit 15 = 1; Disable Ant 1 */
R2 |= 0x8000;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
BbpValue &= 0xE7;
BbpValue |= 0x08;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
}
else
{
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpValue);
BbpValue &= 0xE7;
BbpValue |= 0x10;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpValue);
}
}
if (pAd->Antenna.field.RxPath == 2)
{
switch (pATEInfo->RxAntennaSel)
{
case 1:
R2 |= 0x20040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x00;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
case 2:
R2 |= 0x10040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x01;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
default:
R2 |= 0x40;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
/* Only enable two Antenna to receive. */
BbpValue |= 0x08;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
}
}
else if (pAd->Antenna.field.RxPath == 1)
{
/* write 1 to off RxPath */
R2 |= 0x20040;
}
if (pAd->Antenna.field.RxPath == 3)
{
switch (pATEInfo->RxAntennaSel)
{
case 1:
R2 |= 0x20040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x00;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
case 2:
R2 |= 0x10040;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x01;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
case 3:
R2 |= 0x30000;
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x02;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
default:
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BbpValue);
BbpValue &= 0xE4;
BbpValue |= 0x10;
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BbpValue);
break;
}
}
if (Channel > 14)
{
/* initialize R3, R4 */
R3 = (RFRegTable[index].R3 & 0xffffc1ff);
R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pATEInfo->RFFreqOffset << 15);
/*
According the Rory's suggestion to solve the middle range issue.
5.5G band power range : 0xF9~0X0F, TX0 Reg3 bit9/TX1 Reg4 bit6="0"
means the TX power reduce 7dB.
*/
/* R3 */
if ((TxPwer >= -7) && (TxPwer < 0))
{
TxPwer = (7+TxPwer);
R3 |= (TxPwer << 10);
DBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer=%d \n", TxPwer));
}
else
{
TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
R3 |= (TxPwer << 10) | (1 << 9);
}
/* R4 */
if ((TxPwer2 >= -7) && (TxPwer2 < 0))
{
TxPwer2 = (7+TxPwer2);
R4 |= (TxPwer2 << 7);
DBGPRINT(RT_DEBUG_TRACE, ("ATEAsicSwitchChannel: TxPwer2=%d \n", TxPwer2));
}
else
{
TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
R4 |= (TxPwer2 << 7) | (1 << 6);
}
}
else
{
/* Set TX power0. */
R3 = (RFRegTable[index].R3 & 0xffffc1ff) | (TxPwer << 9);
/* Set frequency offset and TX power1. */
R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pATEInfo->RFFreqOffset << 15) | (TxPwer2 <<6);
}
/* based on BBP current mode before changing RF channel */
if (pATEInfo->TxWI.BW == BW_40)
{
R4 |=0x200000;
}
/* Update variables. */
pAd->LatchRfRegs.Channel = Channel;
pAd->hw_cfg.lan_gain = GET_LNA_GAIN(pAd);
pAd->LatchRfRegs.R1 = RFRegTable[index].R1;
pAd->LatchRfRegs.R2 = R2;
pAd->LatchRfRegs.R3 = R3;
pAd->LatchRfRegs.R4 = R4;
RtmpRfIoWrite(pAd);
break;
}
}
break;
default:
break;
}
/* Change BBP setting during switch from a->g, g->a */
if (Channel <= 14)
{
UINT32 TxPinCfg = 0x00050F0A;/* 2007.10.09 by Brian : 0x0005050A ==> 0x00050F0A */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - pAd->hw_cfg.lan_gain));
/* According the Rory's suggestion to solve the middle range issue. */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForG)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 2.4 G band selection PIN */
rtmp_mac_set_band(pAd, BAND_24G);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
/* calibration power unbalance issues */
if (pAd->Antenna.field.TxPath == 2)
{
if (pATEInfo->TxAntennaSel == 1)
{
TxPinCfg &= 0xFFFFFFF7;
}
else if (pATEInfo->TxAntennaSel == 2)
{
TxPinCfg &= 0xFFFFFFFD;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
/* channel > 14 */
else
{
UINT32 TxPinCfg = 0x00050F05;/* 2007.10.09 by Brian : 0x00050505 ==> 0x00050F05 */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - pAd->hw_cfg.lan_gain));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - pAd->hw_cfg.lan_gain));
/* According the Rory's suggestion to solve the middle range issue. */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForA)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R91, &BbpValue);
ASSERT((BbpValue == 0x04));
/* 5 G band selection PIN, bit1 and bit2 are complement */
rtmp_mac_set_band(pAd, BAND_5G);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
ATE_CHIP_RX_VGA_GAIN_INIT(pAd);
#ifdef RELEASE_EXCLUDE
/*
On 11A, We should delay and wait RF/BBP to be stable
and the appropriate time should be 1000 micro seconds.
2005/06/05 - On 11G, We also need this delay time.
Otherwise it's difficult to pass the WHQL.
*/
#endif /* RELEASE_EXCLUDE */
RtmpOsMsDelay(1);
#ifndef RTMP_RF_RW_SUPPORT
if (Channel > 14)
{
/* When 5.5GHz band the LSB of TxPwr will be used to reduced 7dB or not. */
DBGPRINT(RT_DEBUG_TRACE, ("RT28xx:SwitchChannel#%d(RF=%d, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
}
else
{
DBGPRINT(RT_DEBUG_TRACE, ("RT28xx:SwitchChannel#%d(RF=%d, Pwr0=%u, Pwr1=%u, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
(R3 & 0x00003e00) >> 9,
(R4 & 0x000007c0) >> 6,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
}
#endif /* !RTMP_RF_RW_SUPPORT */
}
VOID RT28xx_ChipSwitchChannel(
IN PRTMP_ADAPTER pAd,
IN UCHAR Channel,
IN BOOLEAN bScan)
{
CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/
UCHAR index;
UINT32 Value = 0; /*BbpReg, Value;*/
UCHAR RFValue;
UINT32 i = 0;
ULONG R2 = 0, R3 = DEFAULT_RF_TX_POWER, R4 = 0;
RTMP_RF_REGS *RFRegTable;
i = i; /* avoid compile warning */
RFValue = 0;
/* Search Tx power value*/
/*
We can't use ChannelList to search channel, since some central channl's txpowr doesn't list
in ChannelList, so use TxPower array instead.
*/
for (index = 0; index < MAX_NUM_OF_CHANNELS; index++)
{
if (Channel == pAd->TxPower[index].Channel)
{
TxPwer = pAd->TxPower[index].Power;
TxPwer2 = pAd->TxPower[index].Power2;
break;
}
}
if (index == MAX_NUM_OF_CHANNELS)
{
DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel));
}
RFRegTable = RF2850RegTable;
switch (pAd->RfIcType)
{
case RFIC_2820:
case RFIC_2850:
case RFIC_2720:
case RFIC_2750:
for (index = 0; index < NUM_OF_2850_CHNL; index++)
{
if (Channel == RFRegTable[index].Channel)
{
R2 = RFRegTable[index].R2;
if (pAd->Antenna.field.TxPath == 1)
{
R2 |= 0x4000; /*If TXpath is 1, bit 14 = 1;*/
}
if ((pAd->Antenna.field.RxPath == 2)
)
{
R2 |= 0x40; /*write 1 to off Rxpath.*/
}
else if ((pAd->Antenna.field.RxPath == 1)
)
{
R2 |= 0x20040; /*write 1 to off RxPath*/
}
if (Channel > 14)
{
/* initialize R3, R4*/
R3 = (RFRegTable[index].R3 & 0xffffc1ff);
R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->RfFreqOffset << 15);
/* 5G band power range: 0xF9~0X0F, TX0 Reg3 bit9/TX1 Reg4 bit6="0" means the TX power reduce 7dB*/
/*R3*/
if ((TxPwer >= -7) && (TxPwer < 0))
{
TxPwer = (7+TxPwer);
/* TxPwer is not possible larger than 15 */
R3 |= (TxPwer << 10);
DBGPRINT(RT_DEBUG_TRACE, ("AsicSwitchChannel: TxPwer=%d \n", TxPwer));
}
else
{
TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
R3 |= (TxPwer << 10) | (1 << 9);
}
/* R4*/
if ((TxPwer2 >= -7) && (TxPwer2 < 0))
{
TxPwer2 = (7+TxPwer2);
R4 |= (TxPwer2 << 7);
DBGPRINT(RT_DEBUG_TRACE, ("AsicSwitchChannel: TxPwer2=%d \n", TxPwer2));
}
else
{
TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
R4 |= (TxPwer2 << 7) | (1 << 6);
}
}
else
{
R3 = (RFRegTable[index].R3 & 0xffffc1ff) | (TxPwer << 9); /* set TX power0*/
R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->RfFreqOffset << 15) | (TxPwer2 <<6);/* Set freq Offset & TxPwr1*/
}
/* Based on BBP current mode before changing RF channel.*/
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40)
)
{
R4 |=0x200000;
}
/* Update variables*/
pAd->LatchRfRegs.Channel = Channel;
pAd->LatchRfRegs.R1 = RFRegTable[index].R1;
pAd->LatchRfRegs.R2 = R2;
pAd->LatchRfRegs.R3 = R3;
pAd->LatchRfRegs.R4 = R4;
/* Set RF value 1's set R3[bit2] = [0]*/
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
RTMPusecDelay(200);
/* Set RF value 2's set R3[bit2] = [1]*/
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 | 0x04));
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
RTMPusecDelay(200);
/* Set RF value 3's set R3[bit2] = [0]*/
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
break;
}
}
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%lu, Pwr1=%lu, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
(R3 & 0x00003e00) >> 9,
(R4 & 0x000007c0) >> 6,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
break;
default:
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d : unknown RFIC=%d\n", Channel, pAd->RfIcType));
break;
}
/* Change BBP setting during siwtch from a->g, g->a*/
if (Channel <= 14)
{
ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue.*/
/* Rx High power VGA offset for LNA select*/
{
if (pAd->NicConfig2.field.ExternalLNAForG)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x04);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
RtmpUpdateFilterCoefficientControl(pAd, Channel);
}
else
{
ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/
UINT8 bbpValue;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue. */
/* Set the BBP_R82 value here */
bbpValue = 0xF2;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue);
/* Rx High power VGA offset for LNA select*/
if (pAd->NicConfig2.field.ExternalLNAForA)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x02);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R*/
{
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
/* R66 should be set according to Channel and use 20MHz when scanning*/
if (bScan)
RTMPSetAGCInitValue(pAd, BW_20);
else
RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW);
/*
On 11A, We should delay and wait RF/BBP to be stable
and the appropriate time should be 1000 micro seconds
005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.
*/
RTMPusecDelay(1000);
}
VOID RT30xx_ChipSwitchChannel(
IN PRTMP_ADAPTER pAd,
IN UCHAR Channel,
IN BOOLEAN bScan)
{
CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/
UCHAR index;
UINT32 Value = 0; /*BbpReg, Value;*/
UCHAR RFValue;
UINT32 i = 0;
UCHAR Tx0FinePowerCtrl = 0, Tx1FinePowerCtrl = 0;
BBP_R109_STRUC BbpR109 = {{0}};
i = i; /* avoid compile warning */
RFValue = 0;
/* Search Tx power value*/
/*
We can't use ChannelList to search channel, since some central channl's txpowr doesn't list
in ChannelList, so use TxPower array instead.
*/
for (index = 0; index < MAX_NUM_OF_CHANNELS; index++)
{
if (Channel == pAd->TxPower[index].Channel)
{
TxPwer = pAd->TxPower[index].Power;
TxPwer2 = pAd->TxPower[index].Power2;
#ifdef RT33xx
#endif /* RT33xx */
break;
}
}
if (index == MAX_NUM_OF_CHANNELS)
{
DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel));
}
#ifdef RT30xx
/* The RF programming sequence is difference between 3xxx and 2xxx*/
if ((IS_RT30xx(pAd)) &&
((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) ||
(pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) || (pAd->RfIcType == RFIC_3320)))
{
/* modify by WY for Read RF Reg. error */
UCHAR calRFValue;
for (index = 0; index < NUM_OF_3020_CHNL; index++)
{
if (Channel == FreqItems3020[index].Channel)
{
/* Programming channel parameters*/
RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3020[index].N);
/*
RT3370/RT3390 RF version is 0x3320 RF_R3 [7:4] is not reserved bits
RF_R3[6:4] (pa1_bc_cck) : PA1 Bias CCK
RF_R3[7] (pa2_cc_cck) : PA2 Cascode Bias CCK
*/
RT30xxReadRFRegister(pAd, RF_R03, (PUCHAR)(&RFValue));
RFValue = (RFValue & 0xF0) | (FreqItems3020[index].K & ~0xF0); /* <bit 3:0>:K<bit 3:0>*/
RT30xxWriteRFRegister(pAd, RF_R03, RFValue);
RT30xxReadRFRegister(pAd, RF_R06, &RFValue);
RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
RT30xxWriteRFRegister(pAd, RF_R06, RFValue);
/* Set Tx0 Power*/
RT30xxReadRFRegister(pAd, RF_R12, &RFValue);
RFValue = (RFValue & 0xE0) | TxPwer;
RT30xxWriteRFRegister(pAd, RF_R12, RFValue);
/*Set Tx1 Power*/
RT30xxReadRFRegister(pAd, RF_R13, &RFValue);
RFValue = (RFValue & 0xE0) | TxPwer2;
RT30xxWriteRFRegister(pAd, RF_R13, RFValue);
#ifdef RT33xx
#endif /* RT33xx */
/* Tx/Rx Stream setting*/
RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
RFValue &= 0x03; /*clear bit[7~2]*/
if (pAd->Antenna.field.TxPath == 1)
RFValue |= 0xA0;
else if (pAd->Antenna.field.TxPath == 2)
RFValue |= 0x80;
if (pAd->Antenna.field.RxPath == 1)
RFValue |= 0x50;
else if (pAd->Antenna.field.RxPath == 2)
RFValue |= 0x40;
RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
/* Set RF offset*/
RT30xxReadRFRegister(pAd, RF_R23, &RFValue);
RFValue = (RFValue & 0x80) | pAd->RfFreqOffset;
RT30xxWriteRFRegister(pAd, RF_R23, RFValue);
/* Set BW*/
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
{
calRFValue = pAd->Mlme.CaliBW40RfR24;
}
else
{
calRFValue = pAd->Mlme.CaliBW20RfR24;
}
/*
RT3370/RT3390 RF version is 0x3320 RF_R24 [7:6] is not reserved bits
RF_R24[6] (BB_Rx1_out_en) : enable baseband output and ADC input
RF_R24[7] (BB_Tx1_out_en) : enable DAC output or baseband input
*/
RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RFValue));
calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0>*/
RT30xxWriteRFRegister(pAd, RF_R24, calRFValue);
/*
RT3370/RT3390 RF version is 0x3320 RF_R31 [7:6] is not reserved bits
RF_R31[4:0] (rx_agc_fc) : capacitor control in baseband filter
RF_R31[5] (rx_ h20M) : rx_ h20M: 0=10 MHz and 1=20MHz
RF_R31[7:6] (drv_bc_cck) : Driver Bias CCK
*/
/* Set BW*/
if (IS_RT3390(pAd)) /* RT3390 has different AGC for Tx and Rx*/
{
if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
{
calRFValue = pAd->Mlme.CaliBW40RfR31;
}
else
{
calRFValue = pAd->Mlme.CaliBW20RfR31;
}
}
RT30xxReadRFRegister(pAd, RF_R31, (PUCHAR)(&RFValue));
calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:rx_h20M<bit 5> and <bit 4:0>:rx_agc_fc<bit 4:0>*/
RT30xxWriteRFRegister(pAd, RF_R31, calRFValue);
/* Enable RF tuning*/
RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
RFValue = RFValue | 0x1;
RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue);
/* latch channel for future usage.*/
pAd->LatchRfRegs.Channel = Channel;
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
Channel,
pAd->RfIcType,
TxPwer,
TxPwer2,
pAd->Antenna.field.TxPath,
FreqItems3020[index].N,
FreqItems3020[index].K,
FreqItems3020[index].R));
break;
}
}
}
else
#endif /* RT30xx */
{
switch (pAd->RfIcType)
{
default:
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d : unknown RFIC=%d\n",
Channel, pAd->RfIcType));
break;
}
}
/* Change BBP setting during siwtch from a->g, g->a*/
if (Channel <= 14)
{
ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue.*/
/* Rx High power VGA offset for LNA select*/
{
if (pAd->NicConfig2.field.ExternalLNAForG)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x04);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
{
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
else
{
ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/
UINT8 bbpValue;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue.*/
/* Set the BBP_R82 value here */
bbpValue = 0xF2;
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue);
/* Rx High power VGA offset for LNA select*/
if (pAd->NicConfig2.field.ExternalLNAForA)
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 5G band selection PIN, bit1 and bit2 are complement*/
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x02);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R*/
{
/* Turn off unused PA or LNA when only 1T or 1R*/
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
/* R66 should be set according to Channel and use 20MHz when scanning*/
if (bScan)
RTMPSetAGCInitValue(pAd, BW_20);
else
RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW);
/*
On 11A, We should delay and wait RF/BBP to be stable
and the appropriate time should be 1000 micro seconds
2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.
*/
RTMPusecDelay(1000);
}
/*
==========================================================================
Description:
dynamic tune BBP R66 to find a balance between sensibility and
noise isolation
IRQL = DISPATCH_LEVEL
==========================================================================
*/
UCHAR RT35xx_ChipStaBBPAdjust(
IN RTMP_ADAPTER *pAd,
IN CHAR Rssi,
IN UCHAR R66)
{
UCHAR OrigR66Value = 0;/*, R66UpperBound = 0x30, R66LowerBound = 0x30;*/
if (pAd->LatchRfRegs.Channel <= 14)
{ /*BG band*/
if (IS_RT3572(pAd)|| IS_RT3593(pAd))
{
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
{
R66 = 0x1C + 2*GET_LNA_GAIN(pAd) + 0x20;
if (OrigR66Value != R66)
{
RT3572WriteBBPR66(pAd, R66);
}
}
else
{
R66 = 0x1C + 2*GET_LNA_GAIN(pAd);
if (OrigR66Value != R66)
{
RT3572WriteBBPR66(pAd, R66);
}
}
}
else
DBGPRINT(RT_DEBUG_ERROR, ("RT35xx_ChipStaBBPAdjust - Mismatch MACVersion = 0x%x \n", pAd->MACVersion));
}
else
{ /*A band*/
if (pAd->CommonCfg.BBPCurrentBW == BW_20)
{
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
{
R66 = 0x32 + (GET_LNA_GAIN(pAd)*5)/3 + 0x10;
if (OrigR66Value != R66)
{
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, R66);
}
}
else
{
R66 = 0x32 + (GET_LNA_GAIN(pAd)*5)/3;
if (OrigR66Value != R66)
{
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, R66);
}
}
}
else
{
if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY)
{
R66 = 0x3A + (GET_LNA_GAIN(pAd)*5)/3 + 0x10;
if (OrigR66Value != R66)
{
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, R66);
}
}
else
{
R66 = 0x3A + (GET_LNA_GAIN(pAd)*5)/3;
if (OrigR66Value != R66)
{
if (IS_RT3572(pAd) || IS_RT3593(pAd))
RT3572WriteBBPR66(pAd, R66);
}
}
}
}
return 0;
}
VOID RT30xxATEAsicSwitchChannel(
IN PRTMP_ADAPTER pAd)
{
CHAR TxPwer = 0, TxPwer2 = 0;
UCHAR index = 0, Channel = 0;
UINT32 Value = 0;
#ifdef A_BAND_SUPPORT
UCHAR BbpValue = 0;
#endif /* A_BAND_SUPPORT */
#ifdef RTMP_RF_RW_SUPPORT
/* Added to prevent RF register reading error */
UCHAR RFValue = 0;
#endif /* RTMP_RF_RW_SUPPORT */
#ifdef RALINK_QA
/* For QA mode, TX power values are passed from UI */
if ((pAd->ate.bQATxStart == TRUE) || (pAd->ate.bQARxStart == TRUE))
{
if (pAd->ate.Channel != pAd->LatchRfRegs.Channel)
{
pAd->ate.Channel = pAd->LatchRfRegs.Channel;
}
return;
}
else
#endif /* RALINK_QA */
Channel = pAd->ate.Channel;
/* Fill Tx power value */
TxPwer = pAd->ate.TxPower0;
TxPwer2 = pAd->ate.TxPower1;
/*
The RF programming sequence is difference between 3xxx and 2xxx.
The 3070 is 1T1R. Therefore, we don't need to set the number of Tx/Rx path
and the only job is to set the parameters of channels.
*/
if ((IS_RT30xx(pAd)) &&
((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) ||
(pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) || (pAd->RfIcType == RFIC_3320)))
{
for (index = 0; index < NUM_OF_3020_CHNL; index++)
{
if (Channel == FreqItems3020[index].Channel)
{
/* Programming channel parameters. */
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R02, FreqItems3020[index].N);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R03, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xF0) | (FreqItems3020[index].K&(~0xF0));
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R03, (UCHAR)RFValue);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R06, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R06, (UCHAR)RFValue);
/* Set Tx Power. */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R12, (PUCHAR)&RFValue);
RFValue = (RFValue & 0xE0) | TxPwer;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R12, (UCHAR)RFValue);
/* Set RF offset. */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R23, (PUCHAR)&RFValue);
RFValue = (RFValue & 0x80) | pAd->ate.RFFreqOffset;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R23, (UCHAR)RFValue);
/* Set BW. */
if (pAd->ate.TxWI.BW == BW_40)
{
RFValue = pAd->Mlme.CaliBW40RfR24;
}
else
{
RFValue = pAd->Mlme.CaliBW20RfR24;
}
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R24, (UCHAR)RFValue);
/* Enable RF tuning */
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R07, (PUCHAR)&RFValue);
RFValue = RFValue | 0x1;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R07, (UCHAR)RFValue);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
/* Latch channel for future usage */
pAd->LatchRfRegs.Channel = Channel;
ATEAsicSetTxRxPath(pAd);
ATE_RF_IO_READ8_BY_REG_ID(pAd, RF_R30, (PUCHAR)&RFValue);
RFValue |= 0x80;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
RTMPusecDelay(1000);
RFValue &= 0x7F;
ATE_RF_IO_WRITE8_BY_REG_ID(pAd, RF_R30, (UCHAR)RFValue);
break;
}
}
DBGPRINT(RT_DEBUG_TRACE, ("%s::SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
__FUNCTION__,
Channel,
pAd->RfIcType,
TxPwer,
TxPwer2,
pAd->Antenna.field.TxPath,
FreqItems3020[index].N,
FreqItems3020[index].K,
FreqItems3020[index].R));
}
/* Change BBP setting during switch from a->g, g->a */
if (Channel <= 14)
{
UINT32 TxPinCfg = 0x00050F0A; /* 2007.10.09 by Brian : 0x0005050A ==> 0x00050F0A */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
if (IS_RT3352(pAd) || IS_RT5350(pAd))
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x38);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
}
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForG)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
/* 2.4 G band selection PIN */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x04);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
/* Calibration power unbalance issues */
if (pAd->Antenna.field.TxPath == 2)
{
if (pAd->ate.TxAntennaSel == 1)
{
TxPinCfg &= 0xFFFFFFF7;
}
else if (pAd->ate.TxAntennaSel == 2)
{
TxPinCfg &= 0xFFFFFFFD;
}
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
#ifdef A_BAND_SUPPORT
else
{
UINT32 TxPinCfg = 0x00050F05; /* 2007.10.09 by Brian : 0x00050505 ==> 0x00050F05 */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
/* According the Rory's suggestion to solve the middle range issue. */
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
/* Rx High power VGA offset for LNA select */
if (pAd->NicConfig2.field.ExternalLNAForA)
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
}
else
{
ATE_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
}
ATE_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R91, &BbpValue);
ASSERT((BbpValue == 0x04));
/* 5 G band selection PIN, bit1 and bit2 are complement */
RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
Value &= (~0x6);
Value |= (0x02);
RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
/* Turn off unused PA or LNA when only 1T or 1R. */
if (pAd->Antenna.field.TxPath == 1)
{
TxPinCfg &= 0xFFFFFFF3;
}
if (pAd->Antenna.field.RxPath == 1)
{
TxPinCfg &= 0xFFFFF3FF;
}
RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
}
#endif /* A_BAND_SUPPORT */
ATE_CHIP_RX_VGA_GAIN_INIT(pAd);
RtmpOsMsDelay(1);
#ifndef RTMP_RF_RW_SUPPORT
if (Channel <= 14)
{
DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%u, Pwr1=%u, %dT) to , R1=0x%08x, R2=0x%08x, R3=0x%08x, R4=0x%08x\n",
Channel,
pAd->RfIcType,
(pAd->LatchRfRegs.R3 & 0x00003e00) >> 9,
(pAd->LatchRfRegs.R4 & 0x000007c0) >> 6,
pAd->Antenna.field.TxPath,
pAd->LatchRfRegs.R1,
pAd->LatchRfRegs.R2,
pAd->LatchRfRegs.R3,
pAd->LatchRfRegs.R4));
}
