static void __init setup_intr(unsigned int intr, unsigned int cpu, unsigned int pin, unsigned int polarity, unsigned int trigtype) { /* Setup Intr to Pin mapping */ if (pin & GIC_MAP_TO_NMI_MSK) { GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin); /* FIXME: hack to route NMI to all cpu's */ for (cpu = 0; cpu < NR_CPUS; cpu += 32) { GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)), 0xffffffff); } } else { GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), GIC_MAP_TO_PIN_MSK | pin); /* Setup Intr to CPU mapping */ GIC_SH_MAP_TO_VPE_SMASK(intr, cpu); } /* Setup Intr Polarity */ GIC_SET_POLARITY(intr, polarity); /* Setup Intr Trigger Type */ GIC_SET_TRIGGER(intr, trigtype); /* Init Intr Masks */ GIC_SET_INTR_MASK(intr, 0); }
static void gic_unmask_irq(unsigned int irq) { pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); irq -= _irqbase; /* FIXME: this is wrong for !GICISWORDLITTLEENDIAN */ GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_SMASK_31_0_OFS + (irq / 32))), 1 << (irq % 32)); }
static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, unsigned int pin, unsigned int polarity, unsigned int trigtype, unsigned int flags) { /* Setup Intr to Pin mapping */ if (pin & GIC_MAP_TO_NMI_MSK) { GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin); /* FIXME: hack to route NMI to all cpu's */ for (cpu = 0; cpu < NR_CPUS; cpu += 32) { GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)), 0xffffffff); } } else { GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), GIC_MAP_TO_PIN_MSK | pin); /* Setup Intr to CPU mapping */ GIC_SH_MAP_TO_VPE_SMASK(intr, cpu); } /* Setup Intr Polarity */ GIC_SET_POLARITY(intr, polarity); /* Setup Intr Trigger Type */ GIC_SET_TRIGGER(intr, trigtype); /* Init Intr Masks */ GIC_CLR_INTR_MASK(intr); /* Initialise per-cpu Interrupt software masks */ if (flags & GIC_FLAG_IPI) set_bit(intr, pcpu_masks[cpu].pcpu_mask); #ifdef CONFIG_RALINK_SOC if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0)) #else if (flags & GIC_FLAG_TRANSPARENT) #endif GIC_SET_INTR_MASK(intr); if (trigtype == GIC_TRIG_EDGE) gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE; }
static void gic_irq_ack(unsigned int irq) { #if gic_wedgeb2bok == 0 unsigned long flags; #endif pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); irq -= _irqbase; GICWRITE(GIC_REG_ADDR(SHARED, (GIC_SH_RMASK_31_0_OFS + (irq / 32))), 1 << (irq % 32)); if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) { if (!gic_wedgeb2bok) spin_lock_irqsave(&gic_wedgeb2b_lock, flags); GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); if (!gic_wedgeb2bok) { (void) GIC_REG(SHARED, GIC_SH_CONFIG); spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags); } } }