/**
* \brief Initialize the GMAC with the Gmac controller address
* \param pGmacd Pointer to GMAC Driver instance.
* \param pHw Pointer to HW address for registers.
* \param bID HW ID for power management
* \param enableCAF Enable/Disable CopyAllFrame.
* \param enableNBC Enable/Disable NoBroadCast.
*/
void GMACD_Init(sGmacd *pGmacd,
Gmac *pHw,
uint8_t bID,
uint8_t enableCAF,
uint8_t enableNBC )
{
uint32_t dwNcfgr, dwDcfgr;
/* Check parameters */
// assert(GRX_BUFFERS * GMAC_RX_UNITSIZE > GMAC_FRAME_LENTGH_MAX);
TRACE_DEBUG("GMAC_Init\n\r");
/* Initialize struct */
pGmacd->pHw = pHw;
pGmacd->bId = bID;
/* Power ON */
PMC_EnablePeripheral(bID);
/* Disable TX & RX and more */
GMAC_NetworkControl(pHw, 0);
GMAC_DisableAllQueueIt(pHw, ~0u);
GMAC_ClearStatistics(pHw);
/* Clear all status bits in the receive status register. */
GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA |GMAC_RSR_HNO);
/* Clear all status bits in the transmit status register */
GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE
| GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP
| GMAC_TSR_UND | GMAC_TSR_HRESP );
/* Clear All interrupts */
GMAC_GetItStatus(pHw, GMAC_QUE_0);
GMAC_GetItStatus(pHw, GMAC_QUE_1);
GMAC_GetItStatus(pHw, GMAC_QUE_2);
/* Enable the copy of data into the buffers
ignore broadcasts, and don't copy FCS. */
dwNcfgr = GMAC_NCFGR_FD | GMAC_NCFGR_DBW(0) | GMAC_NCFGR_CLK_MCK_64;
/* enable 1536 buffer */
// dwNcfgr |= GMAC_NCFGR_MAXFS;
if( enableCAF ) {
dwNcfgr |= GMAC_NCFGR_CAF;
}
if( enableNBC ) {
dwNcfgr |= GMAC_NCFGR_NBC;
}
dwDcfgr = (GMAC_DCFGR_DRBS(8) | (0<<8) | (0<<10) );
GMAC_Configure(pHw, dwNcfgr);
GMAC_DmaConfigure(pHw, dwDcfgr);
}
/**
* \brief Process successfully sent packets
* \param pGmacd Pointer to GMAC Driver instance.
*/
static void GMACD_TxCompleteHandler(sGmacd *pGmacd, gmacQueList_t qId)
{
Gmac *pHw = pGmacd->pHw;
sGmacTxDescriptor *pTxTd;
fGmacdTransferCallback fTxCb;
uint32_t tsr;
/* Clear status */
tsr = GMAC_GetTxStatus(pHw);
GMAC_ClearTxStatus(pHw, tsr);
while (!GCIRC_EMPTY(
pGmacd->queueList[qId].wTxHead, pGmacd->queueList[qId].wTxTail)) {
pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail];
/* Make hw descriptor updates visible to CPU */
GMAC_CACHE_COHERENCE
/* Exit if frame has not been sent yet:
* On TX completion, the GMAC set the USED bit only into the
* very first buffer descriptor of the sent frame.
* Otherwise it updates this descriptor with status error bits.
* This is the descriptor write back.
*/
if ((pTxTd->status.val & GMAC_TX_USED_BIT) == 0)
break;
/* Process all buffers of the current transmitted frame */
while ((pTxTd->status.val & GMAC_TX_LAST_BUFFER_BIT) == 0) {
GCIRC_INC(pGmacd->queueList[qId].wTxTail,
pGmacd->queueList[qId].wTxListSize);
pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail];
memory_sync();
}
/* Notify upper layer that a frame has been sent */
fTxCb = pGmacd->queueList[qId].fTxCbList[pGmacd->queueList[qId].wTxTail];
if (fTxCb)
fTxCb(tsr);
/* Go to next frame */
GCIRC_INC(pGmacd->queueList[qId].wTxTail, pGmacd->queueList[qId].wTxListSize);
}
/* If a wakeup has been scheduled, notify upper layer that it can
send other packets, send will be successful. */
if (pGmacd->queueList[qId].fWakupCb &&
GCIRC_SPACE(pGmacd->queueList[qId].wTxHead,
pGmacd->queueList[qId].wTxTail,
pGmacd->queueList[qId].wTxListSize) >=
pGmacd->queueList[qId].bWakeupThreshold)
pGmacd->queueList[qId].fWakupCb();
}
static void __MacInitialize(tagMacDriver *pDrive)
{
Gmac *pHw;
tagQueue *que;
u32 index;
u32 value;
pHw = pDrive->pHw;
GMAC_DEBUG("Mac Initialize start...\n\r");
//make it power on
PMC_EnablePeripheral(pDrive->bId);
//first,we must stop the device to receive or send
GMAC_NetworkControl(pHw, 0);
//disable all the interrupts
GMAC_DisableAllQueueIt(pHw, ~0u);
//do the stat clearing
GMAC_ClearStatistics(pHw);
/* Clear all status bits in the receive status register. */
GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC
| GMAC_RSR_BNA |GMAC_RSR_HNO);
/* Clear all status bits in the transmit status register */
GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE
| GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP
| GMAC_TSR_HRESP );
//here we begin to configure the mac device
for(index =0;index < CN_QUE_NUM;index ++)
{
que = &pDrive->queueList[CN_QUE_0];
GMAC_GetItStatus(pHw, index); //read for clear
/*initialize the bd*/
__MacBdSndInit(index);
__MacBdRcvInit(index);
/*set the dma configuration*/
if(index == CN_QUE_0)
{
value = (GMAC_DCFGR_DRBS(que->rcvbuflen >> 6) )
| GMAC_DCFGR_RXBMS(3) | GMAC_DCFGR_TXPBMS |GMAC_DCFGR_DDRP|GMAC_DCFGR_FBLDO_INCR4;
}
else
{
/**
* \brief Reset TX queue when errors are detected
* \param pGmacd Pointer to GMAC Driver instance.
*/
static void GMACD_TxErrorHandler(sGmacd *pGmacd, gmacQueList_t qId)
{
Gmac *pHw = pGmacd->pHw;
sGmacTxDescriptor *pTxTd;
fGmacdTransferCallback fTxCb;
uint32_t tsr;
/* Clear TXEN bit into the Network Configuration Register:
* this is a workaround to recover from TX lockups that
* occur on sama5d3 gmac (r1p24f2) when using scatter-gather.
* This issue has never been seen on sama5d4 gmac (r1p31).
*/
GMAC_TransmitEnable(pHw, 0);
/* The following step should be optional since this function is called
* directly by the IRQ handler. Indeed, according to Cadence
* documentation, the transmission is halted on errors such as
* too many retries or transmit under run.
* However it would become mandatory if the call of this function
* were scheduled as a task by the IRQ handler (this is how Linux
* driver works). Then this function might compete with GMACD_Send().
*
* Setting bit 10, tx_halt, of the Network Control Register is not enough:
* We should wait for bit 3, tx_go, of the Transmit Status Register to
* be cleared at transmit completion if a frame is being transmitted.
*/
GMAC_TransmissionHalt(pHw);
while (GMAC_GetTxStatus(pHw) & GMAC_TSR_TXGO);
/* Treat frames in TX queue including the ones that caused the error. */
while (!GCIRC_EMPTY(pGmacd->queueList[qId].wTxHead,
pGmacd->queueList[qId].wTxTail)) {
int tx_completed = 0;
pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail];
/* Make hw descriptor updates visible to CPU */
GMAC_CACHE_COHERENCE
/* Check USED bit on the very first buffer descriptor to validate
* TX completion.
*/
if (pTxTd->status.val & GMAC_TX_USED_BIT)
tx_completed = 1;
/* Go to the last buffer descriptor of the frame */
while ((pTxTd->status.val & GMAC_TX_LAST_BUFFER_BIT) == 0) {
GCIRC_INC(pGmacd->queueList[qId].wTxTail,
pGmacd->queueList[qId].wTxListSize);
pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail];
GMAC_CACHE_COHERENCE
}
/* Notify upper layer that a frame status */
fTxCb = pGmacd->queueList[qId].fTxCbList[pGmacd->queueList[qId].wTxTail];
if (fTxCb)
fTxCb(tx_completed ? GMAC_TSR_TXCOMP : 0);
// TODO: which error to notify?
/* Go to next frame */
GCIRC_INC(pGmacd->queueList[qId].wTxTail, pGmacd->queueList[qId].wTxListSize);
}
/* Reset TX queue */
GMACD_ResetTx(pGmacd, qId);
/* Clear status */
tsr = GMAC_GetTxStatus(pHw);
GMAC_ClearTxStatus(pHw, tsr);
/* Now we are ready to start transmission again */
GMAC_TransmitEnable(pHw, 1);
if (pGmacd->queueList[qId].fWakupCb)
pGmacd->queueList[qId].fWakupCb();
}
/**
* \brief GMAC Interrupt handler
* \param pGmacd Pointer to GMAC Driver instance.
*/
void GMACD_Handler(sGmacd *pGmacd )
{
Gmac *pHw = pGmacd->pHw;
sGmacTxDescriptor *pTxTd;
fGmacdTransferCallback *pTxCb = NULL;
uint32_t isr;
uint32_t rsr;
uint32_t tsr;
uint32_t rxStatusFlag;
uint32_t txStatusFlag;
isr = GMAC_GetItStatus(pHw);
rsr = GMAC_GetRxStatus(pHw);
tsr = GMAC_GetTxStatus(pHw);
isr &= ~(GMAC_GetItMask(pHw)| 0xF8030300);
/* RX packet */
if ((isr & GMAC_ISR_RCOMP) || (rsr & GMAC_RSR_REC)) {
asm("nop");
rxStatusFlag = GMAC_RSR_REC;
/* Frame received */
/* Check OVR */
if (rsr & GMAC_RSR_RXOVR) {
rxStatusFlag |= GMAC_RSR_RXOVR;
}
/* Check BNA */
if (rsr & GMAC_RSR_BNA) {
rxStatusFlag |= GMAC_RSR_BNA;
}
/* Check HNO */
if (rsr & GMAC_RSR_HNO) {
rxStatusFlag |= GMAC_RSR_HNO;
}
/* Clear status */
GMAC_ClearRxStatus(pHw, rxStatusFlag);
/* Invoke callbacks */
if (pGmacd->fRxCb)
{
pGmacd->fRxCb(rxStatusFlag);
}
}
/* TX packet */
if ((isr & GMAC_ISR_TCOMP) || (tsr & GMAC_TSR_TXCOMP)) {
asm("nop");
txStatusFlag = GMAC_TSR_TXCOMP;
/* A frame transmitted Check RLE */
if (tsr & GMAC_TSR_RLE) {
/* Status RLE & Number of discarded buffers */
txStatusFlag = GMAC_TSR_RLE
| GCIRC_CNT(pGmacd->wTxHead,
pGmacd->wTxTail,
pGmacd->wTxListSize);
pTxCb = &pGmacd->fTxCbList[pGmacd->wTxTail];
GMACD_ResetTx(pGmacd);
TRACE_INFO("Tx RLE!!\n\r");
GMAC_TransmitEnable(pHw, 1);
}
/* Check COL */
if (tsr & GMAC_TSR_COL) {
txStatusFlag |= GMAC_TSR_COL;
}
/* Check TFC */
if (tsr & GMAC_TSR_TFC) {
txStatusFlag |= GMAC_TSR_TFC;
}
/* Check UND */
if (tsr & GMAC_TSR_UND) {
txStatusFlag |= GMAC_TSR_UND;
}
/* Check HRESP */
if (tsr & GMAC_TSR_HRESP) {
txStatusFlag |= GMAC_TSR_HRESP;
}
/* Check LCO */
if (tsr & GMAC_TSR_LCO) {
txStatusFlag |= GMAC_TSR_LCO;
}
/* Clear status */
GMAC_ClearTxStatus(pHw, txStatusFlag);
if (!GCIRC_EMPTY(pGmacd->wTxHead, pGmacd->wTxTail))
{
/* Check the buffers */
do {
pTxTd = &pGmacd->pTxD[pGmacd->wTxTail];
pTxCb = &pGmacd->fTxCbList[pGmacd->wTxTail];
/* Exit if buffer has not been sent yet */
if ((pTxTd->status.val & (uint32_t)GMAC_TX_USED_BIT) == 0) {
break;
}
/* Notify upper layer that a packet has been sent */
if (*pTxCb) {
(*pTxCb)(txStatusFlag);
}
GCIRC_INC( pGmacd->wTxTail, pGmacd->wTxListSize );
} while (GCIRC_CNT(pGmacd->wTxHead, pGmacd->wTxTail, pGmacd->wTxListSize));
}
if (tsr & GMAC_TSR_RLE) {
/* Notify upper layer RLE */
if (*pTxCb) {
(*pTxCb)(txStatusFlag);
}
}
/* If a wakeup has been scheduled, notify upper layer that it can
send other packets, send will be successfull. */
if((GCIRC_SPACE(pGmacd->wTxHead,
pGmacd->wTxTail,
pGmacd->wTxListSize) >= pGmacd->bWakeupThreshold) && pGmacd->fWakupCb)
{
pGmacd->fWakupCb();
}
}
/* PAUSE Frame */
if (isr & GMAC_ISR_PFNZ) TRACE_INFO("Pause!\n\r");
if (isr & GMAC_ISR_PTZ) TRACE_INFO("Pause TO!\n\r");
}
