/**
* \brief Initialize the GMAC with the Gmac controller address
* \param pGmacd Pointer to GMAC Driver instance.
* \param pHw Pointer to HW address for registers.
* \param bID HW ID for power management
* \param enableCAF Enable/Disable CopyAllFrame.
* \param enableNBC Enable/Disable NoBroadCast.
*/
void GMACD_Init(sGmacd *pGmacd,
Gmac *pHw,
uint8_t bID,
uint8_t enableCAF,
uint8_t enableNBC )
{
uint32_t dwNcfgr, dwDcfgr;
/* Check parameters */
// assert(GRX_BUFFERS * GMAC_RX_UNITSIZE > GMAC_FRAME_LENTGH_MAX);
TRACE_DEBUG("GMAC_Init\n\r");
/* Initialize struct */
pGmacd->pHw = pHw;
pGmacd->bId = bID;
/* Power ON */
PMC_EnablePeripheral(bID);
/* Disable TX & RX and more */
GMAC_NetworkControl(pHw, 0);
GMAC_DisableAllQueueIt(pHw, ~0u);
GMAC_ClearStatistics(pHw);
/* Clear all status bits in the receive status register. */
GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA |GMAC_RSR_HNO);
/* Clear all status bits in the transmit status register */
GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE
| GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP
| GMAC_TSR_UND | GMAC_TSR_HRESP );
/* Clear All interrupts */
GMAC_GetItStatus(pHw, GMAC_QUE_0);
GMAC_GetItStatus(pHw, GMAC_QUE_1);
GMAC_GetItStatus(pHw, GMAC_QUE_2);
/* Enable the copy of data into the buffers
ignore broadcasts, and don't copy FCS. */
dwNcfgr = GMAC_NCFGR_FD | GMAC_NCFGR_DBW(0) | GMAC_NCFGR_CLK_MCK_64;
/* enable 1536 buffer */
// dwNcfgr |= GMAC_NCFGR_MAXFS;
if( enableCAF ) {
dwNcfgr |= GMAC_NCFGR_CAF;
}
if( enableNBC ) {
dwNcfgr |= GMAC_NCFGR_NBC;
}
dwDcfgr = (GMAC_DCFGR_DRBS(8) | (0<<8) | (0<<10) );
GMAC_Configure(pHw, dwNcfgr);
GMAC_DmaConfigure(pHw, dwDcfgr);
}
error_t samv71EthInit(NetInterface *interface)
{
error_t error;
volatile uint32_t status;
//Debug message
TRACE_INFO("Initializing SAMV71 Ethernet MAC...\r\n");
//Save underlying network interface
nicDriverInterface = interface;
//Enable GMAC peripheral clock
PMC->PMC_PCER1 = (1 << (ID_GMAC - 32));
//GPIO configuration
samv71EthInitGpio(interface);
//Configure MDC clock speed
GMAC->GMAC_NCFGR = GMAC_NCFGR_CLK_MCK_96;
//Enable management port (MDC and MDIO)
GMAC->GMAC_NCR |= GMAC_NCR_MPE;
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Set the MAC address
GMAC->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
GMAC->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
//Configure the receive filter
GMAC->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN;
//DMA configuration
GMAC->GMAC_DCFGR = GMAC_DCFGR_DRBS(SAMV71_ETH_RX_BUFFER_SIZE / 64) |
GMAC_DCFGR_TXPBMS | GMAC_DCFGR_RXBMS_FULL | GMAC_DCFGR_FBLDO_INCR4;
GMAC->GMAC_RBSRPQ[0] = GMAC_RBSRPQ_RBS(SAMV71_ETH_DUMMY_BUFFER_SIZE / 64);
GMAC->GMAC_RBSRPQ[1] = GMAC_RBSRPQ_RBS(SAMV71_ETH_DUMMY_BUFFER_SIZE / 64);
GMAC->GMAC_RBSRPQ[2] = GMAC_RBSRPQ_RBS(SAMV71_ETH_DUMMY_BUFFER_SIZE / 64);
//Initialize hash table
GMAC->GMAC_HRB = 0;
GMAC->GMAC_HRT = 0;
//Initialize buffer descriptors
samv71EthInitBufferDesc(interface);
//Clear transmit status register
GMAC->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
//Clear receive status register
GMAC->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
//First disable all GMAC interrupts
GMAC->GMAC_IDR = 0xFFFFFFFF;
GMAC->GMAC_IDRPQ[0] = 0xFFFFFFFF;
GMAC->GMAC_IDRPQ[1] = 0xFFFFFFFF;
GMAC->GMAC_IDRPQ[2] = 0xFFFFFFFF;
//Only the desired ones are enabled
GMAC->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
//Read GMAC ISR register to clear any pending interrupt
status = GMAC->GMAC_ISR;
//Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
NVIC_SetPriorityGrouping(SAMV71_ETH_IRQ_PRIORITY_GROUPING);
//Configure GMAC interrupt priority
NVIC_SetPriority(GMAC_IRQn, NVIC_EncodePriority(SAMV71_ETH_IRQ_PRIORITY_GROUPING,
SAMV71_ETH_IRQ_GROUP_PRIORITY, SAMV71_ETH_IRQ_SUB_PRIORITY));
//Enable the GMAC to transmit and receive data
GMAC->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
//Force the TCP/IP stack to check the link state
osSetEvent(&interface->nicRxEvent);
//SAMV71 Ethernet MAC is now ready to send
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
