static void pxa168_gpio_save(struct gpio_regs *context)
{
unsigned int i;
for (i = 0; i < 4; i++) {
context->gpdr[i] = __raw_readl(GPIO_BANK(i) + GPDR_OFFSET);
context->grer[i] = __raw_readl(GPIO_BANK(i) + GRER_OFFSET);
context->gfer[i] = __raw_readl(GPIO_BANK(i) + GFER_OFFSET);
context->gedr[i] = __raw_readl(GPIO_BANK(i) + GEDR_OFFSET);
context->gapmask[i] = __raw_readl(GPIO_BANK(i) + GAPMASK_OFFSET);
}
}
static void pxa168_gpio_restore(struct gpio_regs *context)
{
unsigned int i;
for (i = 0; i < 4; i++) {
__raw_writel(context->gpdr[i], GPIO_BANK(i) + GPDR_OFFSET);
__raw_writel(context->grer[i], GPIO_BANK(i) + GRER_OFFSET);
__raw_writel(context->gfer[i], GPIO_BANK(i) + GFER_OFFSET);
__raw_writel(context->gedr[i], GPIO_BANK(i) + GEDR_OFFSET);
__raw_writel(context->gapmask[i], GPIO_BANK(i) + GAPMASK_OFFSET);
}
}
void gpio_toggle_value(int gp)
{
struct davinci_gpio *bank;
bank = GPIO_BANK(gp);
gpio_set_value(gp, !gpio_get_value(gp));
}
/*static*/ void GpioPlateformImplementation::internalPinSetupOutput( const int pin )
{
const int pinNum = SUNXI_GPD( pin );
const unsigned int val = 1; // 0 = input , 1 = output
unsigned int cfg;
unsigned int bank = GPIO_BANK( pinNum );
unsigned int index = GPIO_CFG_INDEX( pinNum );
unsigned int offset = GPIO_CFG_OFFSET( pinNum );
if( s_sunxi_pio_base == 0)
return ;
struct sunxi_gpio *pio = &((struct sunxi_gpio_reg *) s_sunxi_pio_base )->gpio_bank[bank];
cfg = *(&pio->cfg[0] + index);
cfg &= ~(0xf << offset);
cfg |= val << offset;
*(&pio->cfg[0] + index) = cfg;
return ;
}
unsigned int
gpio_get (unsigned int pin)
{
gpio_init_inpin(pin);
volatile unsigned int *Reg = (GPIO_BANK(pin) + 0x10);
return (((*Reg) & GPIO_MASK(pin)) != 0);
}
int gpio_set_pullup(unsigned int pin, unsigned int pull) {
unsigned int gpio_num = GPIO_NUM(pin);
unsigned int bank = GPIO_BANK(gpio_num);
unsigned int offset = gpio_num % 32;
if (pmu == 0 || iomux == 0) {
return -1;
}
if (pin < RK30_PIN0_PB4) {
unsigned long *base = (unsigned long *) (pmu + PMU_GPIO0A_PULL
+ ((offset / 8) * 4));
offset = (offset % 8) * 2;
unsigned long value = *base;
value &= ~(0x03 << offset);
value |= (0x03 << (16 + offset) | (pull << offset));
*base = value;
} else {
unsigned long *base = (unsigned long *) (iomux + GRF_GPIO0B_PULL - 4
+ bank * 16 + ((offset / 8) * 4));
offset = (7 - (offset % 8)) * 2;
unsigned long value = *base;
value &= ~(0x03 << offset);
value |= ((0x03 << (16 + offset)) | (pull << offset));
*base = value;
}
return 0;
}
int gpio_direction_input(int gp)
{
struct davinci_gpio *bank;
bank = GPIO_BANK(gp);
setbits_le32(&bank->dir, 1U << GPIO_BIT(gp));
return 0;
}
int gpio_direction_output(int gp, int value)
{
struct davinci_gpio *bank;
bank = GPIO_BANK(gp);
clrbits_le32(&bank->dir, 1U << GPIO_BIT(gp));
gpio_set_value(gp, value);
return 0;
}
int gpio_get_value(int gp)
{
struct davinci_gpio *bank;
unsigned int ip;
bank = GPIO_BANK(gp);
ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gp));
return ip ? 1 : 0;
}
int gpio_set_cfgpin(unsigned int pin, unsigned int val) {
unsigned int gpio_num = GPIO_NUM(pin);
#if defined(RK3188)
unsigned int bank = GPIO_BANK(gpio_num);
unsigned int offset = GPIO_OFFSET(gpio_num);
#elif defined(AM3352)
unsigned int bank = GPIO_BANK(pin);
unsigned long offset = 1 << gpio_num;
#endif
debug("PIN: %d\n", pin);
debug("GPIO_NUM: %d\n", gpio_num);
debug("GPIO_BANK: %d\n", bank);
debug("OFFSET: 0x%08lx\n", offset);
if (gpio[bank].gpio_pio_base == 0) {
return -1;
}
struct gpio_reg *pio = ((struct gpio_reg *) gpio[bank].gpio_pio_base);
debug("GPIO_OE: 0x%08lx\n", pio->gpio_oe);
if (val == GPIO_INPUT) {
#if defined(RK3188)
pio->gpio_swport_ddr &= ~offset;
#elif defined(AM3352)
pio->gpio_oe |= offset;
#endif
} else {
#if defined(RK3188)
pio->gpio_swport_ddr |= offset;
#elif defined(AM3352)
pio->gpio_oe &= ~offset;
#endif
}
debug("GPIO_OE: 0x%08lx\n", pio->gpio_oe);
return 0;
}
void gpio_set_value(int gp, int value)
{
struct davinci_gpio *bank;
bank = GPIO_BANK(gp);
if (value)
bank->set_data = 1U << GPIO_BIT(gp);
else
bank->clr_data = 1U << GPIO_BIT(gp);
}
int sunxi_gpio_set_pull(u32 pin, u32 val)
{
u32 bank = GPIO_BANK(pin);
u32 index = GPIO_PULL_INDEX(pin);
u32 offset = GPIO_PULL_OFFSET(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
return 0;
}
int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
{
u32 bank = GPIO_BANK(pin);
u32 index = GPIO_CFG_INDEX(pin);
u32 offset = GPIO_CFG_OFFSET(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
return 0;
}
static int sunxi_gpio_input(u32 pin)
{
u32 dat;
u32 bank = GPIO_BANK(pin);
u32 num = GPIO_NUM(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
dat = readl(&pio->dat);
dat >>= num;
return dat & 0x1;
}
int sunxi_gpio_input(unsigned int pin) {
unsigned int dat;
unsigned int bank = GPIO_BANK(pin);
unsigned int num = GPIO_NUM(pin);
if(SUNXI_PIO_BASE == 0)
{
return -1;
}
struct sunxi_gpio *pio =&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
dat = *(&pio->dat);
dat >>= num;
return (dat & 0x1);
}
static int sunxi_gpio_input(u32 pin)
{
u32 dat;
u32 bank = GPIO_BANK(pin);
u32 num = GPIO_NUM(pin);
struct sunxi_gpio *pio =
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
dat = readl(&pio->dat);
dat >>= num;
return dat & 0x1;
}
int gpio_get_cfgpin(unsigned int pin) {
unsigned int gpio_num = GPIO_NUM(pin);
#if defined(RK3188)
unsigned int bank = GPIO_BANK(gpio_num);
unsigned int offset = GPIO_OFFSET(gpio_num);
#elif defined(AM3352)
unsigned int bank = GPIO_BANK(pin);
unsigned int offset = 1 << gpio_num;
#endif
if (gpio[bank].gpio_pio_base == 0) {
return -1;
}
struct gpio_reg *pio = ((struct gpio_reg *) gpio[bank].gpio_pio_base);
#if defined(RK3188)
return !!(pio->gpio_swport_ddr & offset);
#elif defined(AM3352)
return !!(pio->gpio_oe & offset);
#endif
}
int sunxi_gpio_get_cfgpin(u32 pin)
{
u32 cfg;
u32 bank = GPIO_BANK(pin);
u32 index = GPIO_CFG_INDEX(pin);
u32 offset = GPIO_CFG_OFFSET(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
cfg = readl(&pio->cfg[0] + index);
cfg >>= offset;
return cfg & 0xf;
}
int gpio_set_value(unsigned gpio, int value)
{
struct davinci_gpio *bank;
bank = GPIO_BANK(gpio);
if (value)
bank->set_data = 1U << GPIO_BIT(gpio);
else
bank->clr_data = 1U << GPIO_BIT(gpio);
return 0;
}
int gpio_input(unsigned int pin) {
unsigned int gpio_num = GPIO_NUM(pin);
#if defined(RK3188)
unsigned int bank = GPIO_BANK(gpio_num);
unsigned int offset = GPIO_OFFSET(gpio_num);
#elif defined(AM3352)
unsigned int bank = GPIO_BANK(pin);
unsigned int offset = 1 << gpio_num;
#endif
if (gpio[bank].gpio_pio_base == 0) {
return -1;
}
struct gpio_reg *pio = ((struct gpio_reg *) gpio[bank].gpio_pio_base);
#if defined(RK3188)
return !!(pio->gpio_ext_port & offset);
#elif defined(AM3352)
return !!(pio->gpio_datain & offset);
#endif
}
int sunxi_gpio_output(unsigned int pin, unsigned int val) {
unsigned int bank = GPIO_BANK(pin);
unsigned int num = GPIO_NUM(pin);
if(SUNXI_PIO_BASE == 0)
{
return -1;
}
struct sunxi_gpio *pio =&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
if(val)
*(&pio->dat) |= 1 << num;
else
*(&pio->dat) &= ~(1 << num);
return 0;
}
int sunxi_gpio_get_cfgpin(unsigned int pin) {
unsigned int cfg;
unsigned int bank = GPIO_BANK(pin);
unsigned int index = GPIO_CFG_INDEX(pin);
unsigned int offset = GPIO_CFG_OFFSET(pin);
if (SUNXI_PIO_BASE == 0) {
return -1;
}
struct sunxi_gpio *pio = &((struct sunxi_gpio_reg *) SUNXI_PIO_BASE)->gpio_bank[bank];
cfg = *(&pio->cfg[0] + index);
cfg >>= offset;
return (cfg & 0xf);
}
void EXTI15_10_IRQHandler(void) {
// TODO(rqou): How to share this vector (or if it is even necessary)
portTickType time_now = xTaskGetTickCountFromISR();
if (EXTI->PR & (1 << GPIO_PIN(PINDEF_BUTTON0))) {
// Clear pending
EXTI->PR = (1 << GPIO_PIN(PINDEF_BUTTON0));
// Invert is necessary because pin idles at 1
int newState =
!(GPIO_BANK(PINDEF_BUTTON0)->IDR & (1 << GPIO_PIN(PINDEF_BUTTON0)));
if (time_now - button0_last_toggle >= DEBOUNCE_DELAY) {
button0_state = newState;
}
button0_last_toggle = time_now;
button0_actual_state = newState;
}
if (EXTI->PR & (1 << GPIO_PIN(PINDEF_BUTTON1))) {
// Clear pending
EXTI->PR = (1 << GPIO_PIN(PINDEF_BUTTON1));
// Invert is necessary because pin idles at 1
int newState =
!(GPIO_BANK(PINDEF_BUTTON1)->IDR & (1 << GPIO_PIN(PINDEF_BUTTON1)));
if (time_now - button1_last_toggle >= DEBOUNCE_DELAY) {
// Invert is necessary because pin idles at 1
button1_state = newState;
}
button1_last_toggle = time_now;
button1_actual_state = newState;
}
}
int sunxi_gpio_get_cfgpin(u32 pin) {
u32 cfg;
u32 bank = GPIO_BANK(pin);
u32 index = GPIO_CFG_INDEX(pin);
u32 offset = GPIO_CFG_OFFSET(pin);
struct sunxi_gpio *pio =
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
cfg = readl(&pio->cfg[0] + index);
cfg >>= offset;
return (cfg & 0xf);
}
int gpio_output(unsigned int pin, unsigned int val) {
unsigned int gpio_num = GPIO_NUM(pin);
#if defined(RK3188)
unsigned int bank = GPIO_BANK(gpio_num);
unsigned int offset = GPIO_OFFSET(gpio_num);
#elif defined(AM3352)
unsigned int bank = GPIO_BANK(pin);
unsigned int offset = 1 << gpio_num;
#endif
if (gpio[bank].gpio_pio_base == 0) {
return -1;
}
struct gpio_reg *pio = ((struct gpio_reg *) gpio[bank].gpio_pio_base);
debug("GPIO_DATAOUT: 0x%08lx\n", pio->gpio_dataout);
if (!val) {
#if defined(RK3188)
pio->gpio_swport_dr &= ~offset;
#elif defined(AM3352)
pio->gpio_cleardataout = offset;
#endif
} else {
#if defined(RK3188)
pio->gpio_swport_dr |= offset;
#elif defined(AM3352)
pio->gpio_setdataout = offset;
#endif
debug("GPIO_SWPORT_DR: 0x%08lx\n", pio->gpio_dataout);
}
return 0;
}
void gpio_info(void)
{
int gp, dir, val;
struct davinci_gpio *bank;
for (gp = 0; gp < MAX_NUM_GPIOS; ++gp) {
bank = GPIO_BANK(gp);
dir = in_le32(&bank->dir) & (1U << GPIO_BIT(gp));
val = gpio_get_value(gp);
printf("% 4d: %s: %d [%c] %s\n",
gp, dir ? " in" : "out", val,
gpio_registry[gp].is_registered ? 'x' : ' ',
gpio_registry[gp].name);
}
}
int sunxi_gpio_set_cfgpin(unsigned int pin, unsigned int val) {
unsigned int cfg;
unsigned int bank = GPIO_BANK(pin);
unsigned int index = GPIO_CFG_INDEX(pin);
unsigned int offset = GPIO_CFG_OFFSET(pin);
if(SUNXI_PIO_BASE == 0) {
return -1;
}
struct sunxi_gpio *pio =
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
cfg = *(&pio->cfg[0] + index);
cfg &= ~(0xf << offset);
cfg |= val << offset;
*(&pio->cfg[0] + index) = cfg;
return 0;
}
static int sunxi_gpio_output(u32 pin, u32 val)
{
u32 dat;
u32 bank = GPIO_BANK(pin);
u32 num = GPIO_NUM(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
dat = readl(&pio->dat);
if (val)
dat |= 0x1 << num;
else
dat &= ~(0x1 << num);
writel(dat, &pio->dat);
return 0;
}
int sunxi_gpio_set_cfgpin(u32 pin, u32 val) {
u32 cfg;
u32 bank = GPIO_BANK(pin);
u32 index = GPIO_CFG_INDEX(pin);
u32 offset = GPIO_CFG_OFFSET(pin);
struct sunxi_gpio *pio =
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
cfg = readl(&pio->cfg[0] + index);
cfg &= ~(0xf << offset);
cfg |= val << offset;
writel(cfg, &pio->cfg[0] + index);
return 0;
}
static int sunxi_gpio_output(u32 pin, u32 val)
{
u32 dat;
u32 bank = GPIO_BANK(pin);
u32 num = GPIO_NUM(pin);
struct sunxi_gpio *pio =
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];
dat = readl(&pio->dat);
if (val)
dat |= 0x1 << num;
else
dat &= ~(0x1 << num);
writel(dat, &pio->dat);
return 0;
}
