/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. Configures the DAP Hardware I/O pins for JTAG mode: - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. - TDO to input mode. */ void PORT_JTAG_SETUP() { PIN_SWCLK_TCK_PORT->BSRR = PIN_SWCLK_TCK | PIN_SWDIO_TMS | PIN_TDI | PIN_TDO; PIN_nRESET_PORT->BRR = PIN_nRESET; PIN_nRESET_HIGH(); GPIO_INIT(PIN_TDO_PORT, INIT_JTAG_IN); GPIO_INIT(PIN_SWCLK_TCK_PORT, INIT_JTAG_OUT); }
/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: - SWCLK, SWDIO, nRESET to output mode and set to default high level. - TDI, TDO, nTRST to HighZ mode (pins are unused in SWD mode). */ void PORT_SWD_SETUP() { PIN_SWCLK_TCK_PORT->BSRR = (PIN_SWCLK_TCK | PIN_SWDIO_TMS); PIN_nRESET_PORT->BRR = PIN_nRESET; #if ( DAP_JTAG != 0 ) GPIO_INIT(PIN_TDI_PORT, INIT_SWD_TDx); #endif GPIO_INIT(PIN_SWCLK_TCK_PORT, INIT_SWD_PINS); PIN_nRESET_HIGH(); }
void BoardInit(void) { // Enable GPIOA-GPIOC RCC->APB2ENR |= (RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN); // Enable SWJ only GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE); GPIO_INIT(GPIOA, INIT_PINS_A); GPIO_INIT(GPIOA, INIT_PINS_A3); GPIO_INIT(GPIOB, INIT_PINS_B); GPIO_INIT(GPIOC, INIT_PINS_C); LEDS_SETUP(); }
int main() { __disable_interrupt(); //InitQueue(&uart_rx_cirqueue); //InitQueue(&uart_tx_cirqueue); CLK_SYSCLKConfig(CLK_PRESCALER_HSIDIV1); //GPIO_Init(GPIOD, GPIO_PIN_3|GPIO_PIN_2|GPIO_PIN_0, GPIO_MODE_OUT_PP_LOW_SLOW); GPIO_INIT();//led GPIO_Init(GPIOD, GPIO_PIN_2,GPIO_MODE_OUT_PP_HIGH_FAST);//开启U10的控制引脚 pir_RI_io_init();//pir中断 T4_Init(); //Uart_Init(); CommInit(); /*AWU configuration --------------------------------------------*/ AWU_Config(); OSInit(); CommBufInit();//创建信号量的操作不能再OSInit();之前,也就是不能在OS_InitEventList();之前 OSTaskCreate( task0, (void *)OS_TASK_0_STK_SIZE, &Task0Stack[OS_TASK_0_STK_SIZE-1], OS_TASK_0_PRIO ); OSTaskCreate( task1, (void *)OS_TASK_1_STK_SIZE, &Task1Stack[OS_TASK_1_STK_SIZE-1], OS_TASK_1_PRIO ); //OSTaskCreate( task2, (void *)OS_TASK_2_STK_SIZE, &Task2Stack[OS_TASK_2_STK_SIZE-1], OS_TASK_2_PRIO ); OSStart(); return 0; }
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) { GPIO_InitTypeDef gpio_init; static DMA_HandleTypeDef hdma_dac; GPIO_INIT(DACx_GPIO, DACx_PIN, GPIO_MODE_ANALOG, GPIO_NOPULL, 0, 0); DACx_CLK_ENABLE(); DAC_DMAx_CLK_ENABLE(); DAC_TIMx_CLK_ENABLE(); hdma_dac.Instance = DAC_DMAx_STREAM; hdma_dac.Init.Channel = DAC_DMAx_CHANNEL; hdma_dac.Init.Direction = DMA_MEMORY_TO_PERIPH; hdma_dac.Init.PeriphInc = DMA_PINC_DISABLE; hdma_dac.Init.MemInc = DMA_MINC_ENABLE; hdma_dac.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; hdma_dac.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; hdma_dac.Init.Mode = DMA_CIRCULAR; hdma_dac.Init.Priority = DMA_PRIORITY_MEDIUM; HAL_DMA_Init(&hdma_dac); #if DAC_OUTn == 1 __HAL_LINKDMA(hdac, DMA_Handle1, hdma_dac); #endif #if DAC_OUTn == 2 __HAL_LINKDMA(hdac, DMA_Handle2, hdma_dac); #endif }
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) { #ifdef PTP_TIMx PTP_TIMx_CLK_ENABLE(); GPIO_InitTypeDef gpio_init; GPIO_INIT(PTP_TIMx_CH1_GPIO, PTP_TIMx_CH1_PIN, GPIO_MODE_AF_PP, GPIO_PULLUP, GPIO_SPEED_HIGH, PTP_TIMx_AF); #endif }
static void gpio_init(void) { int i; for (i=0; i<keynum; i++) { if (gamekeys[i].gpio) { GPIO_INIT(gamekeys[i].gpio); printk("initial %s success \n", gamekeys[i].name); } else { printk("initial %s is not use \n", gamekeys[i].name); } } }
void main(void) { /* Infinite loop */ RCC_INIT(); GPIO_INIT(); EXTI_INIT(); TIME1_INIT(); USART1_INIT(); TIME2_INIT(); //InitTSL2561(); //get_light_flag = 0; //time_counter =0; /* 485继电器小板测试用程序 while(1) { GPIO_WriteHigh(GPIOD,GPIO_PIN_2); GPIO_WriteHigh(GPIOD,GPIO_PIN_3); GPIO_WriteHigh(GPIOA,GPIO_PIN_3); Delay(1000000); GPIO_WriteLow(GPIOD,GPIO_PIN_3); GPIO_WriteLow(GPIOD,GPIO_PIN_2); GPIO_WriteLow(GPIOA,GPIO_PIN_3); Delay(1000000); } */ enableInterrupts(); while (1) { GPIO_WriteLow(GPIOD,GPIO_PIN_4);//使能485接收 bsp_ModbusRTUSlave_decode(); } }
int main(int argc, char **argv) { LIBGPIO_OBJ *p = GPIO_INIT(); if (p == NULL) { SYS_ERROR("libgpio_init failed.\r\n"); return 0; } while(1) { #if 1 GPIO_PWR_RED(p); SYS_ERROR("power red \r\n"); sleep(5); GPIO_PWR_GREEN(p); SYS_ERROR("power green \r\n"); sleep(5); #endif #if 0 GPIO_STATE_RED(p); SYS_WARNING("state red \r\n"); sleep(5); GPIO_STATE_GREEN(p); SYS_ERROR("state green \r\n"); sleep(5); #endif #if 0 GPIO_3G_GREEN_ON(p); SYS_ERROR("3G on \r\n"); sleep(5); GPIO_3G_GREEN_OFF(p); SYS_ERROR("3G off \r\n"); sleep(5); #endif } SYS_INFO("CLR\r\n"); GPIO_DESTROY(p); return 0; }
/* * board_final_init() * * Do any final initialization, such as adding commands to the * user interface. * * If you don't want a user interface, put the startup code here. * This routine is called just before CFE starts its user interface. * * Input parameters: * nothing * * Return value: * nothing */ void board_final_init(void) { char *addr, *mask, *wait_time; char buf[512], *cur = buf; #ifdef CFG_ROMBOOT char *laddr = NULL; #endif #if !CFG_SIM char *boot_cfg = NULL; char *go_cmd = "go;"; #endif int commit = 0; uint32 ncdl; #if CFG_WL && CFG_WLU && CFG_SIM char *ssid; #endif ui_init_bcm947xxcmds(); /* Force commit of embedded NVRAM */ commit = restore_defaults; /* Set the SDRAM NCDL value into NVRAM if not already done */ if ((getintvar(NULL, "sdram_ncdl") == 0) && ((ncdl = si_memc_get_ncdl(sih)) != 0)) { sprintf(buf, "0x%x", ncdl); nvram_set("sdram_ncdl", buf); commit = 1; } /* Set the bootloader version string if not already done */ sprintf(buf, "CFE %s", EPI_VERSION_STR); if (strcmp(nvram_safe_get("pmon_ver"), buf) != 0) { nvram_set("pmon_ver", buf); commit = 1; } /* Set the size of the nvram area if not already done */ sprintf(buf, "%d", MAX_NVRAM_SPACE); if (strcmp(nvram_safe_get("nvram_space"), buf) != 0) { nvram_set("nvram_space", buf); commit = 1; } #ifdef RTL8365MB int ret = -1, retry = 0; rtk_port_mac_ability_t pa; GPIO_INIT(); for(retry = 0; ret && retry < 10; ++retry) { ret = rtk_switch_init(); if(ret) cfe_usleep(10000); else break; } printf("rtl8354mb initialized(%d)(retry %d) %s\n", ret, retry, ret?"failed":""); ret = rtk_port_phyEnableAll_set(1); if(ret) printf("rtk port_phyEnableAll Failed!(%d)\n", ret); else printf("rtk port_phyEnableAll ok\n"); /* configure & set GMAC ports */ pa.forcemode = MAC_FORCE; pa.speed = SPD_1000M; pa.duplex = FULL_DUPLEX; pa.link = 1; pa.nway = 0; pa.rxpause = 0; pa.txpause = 0; ret = rtk_port_macForceLinkExt_set(EXT_PORT0, MODE_EXT_RGMII, &pa); if(ret) printf("rtk port_macForceLink_set ext_Port0 Failed!(%d)\n", ret); else printf("rtk port_macForceLink_set ext_Port0 ok\n"); /* asic chk */ rtk_uint32 retVal, retVal2; rtk_uint32 data, data2; if((retVal = rtl8367c_getAsicReg(0x1311, &data)) != RT_ERR_OK || (retVal2 = rtl8367c_getAsicReg(0x1305, &data2)) != RT_ERR_OK) { printf("get failed(%d)(%d). (%x)(supposed to be 0x1016)\n", retVal, retVal2, data); } else { /* get ok, then chk reg*/ printf("get ok, chk 0x1311:%x(0x1016), 0x1305:%x(b4~b7:0x1)\n", data, data2); if(data != 0x1016){ printf("\n!! rtl reg 0x1311 error: (%d)(get %x)\n", retVal, data); } if((data2 & 0xf0) != 0x10) { printf("\n!! rtl reg 0x1305 error: (%d)(get %x)\n", retVal, data2); } } /* reset tx/rx delay */ retVal = rtk_port_rgmiiDelayExt_set(EXT_PORT0, 1, 4); if (retVal != RT_ERR_OK) printf("\n!! rtl set delay failed (%d)\n", retVal); #endif #if CFG_FLASH || CFG_SFLASH || CFG_NFLASH #if !CFG_SIM /* Commit NVRAM only if in FLASH */ if ( #ifdef BCMNVRAMW !nvram_inotp() && #endif commit) { printf("Committing NVRAM..."); nvram_commit(); printf("done\n"); if (restore_defaults) { #ifdef BCM_DEVINFO /* devinfo nvram hash table sync */ devinfo_nvram_sync(); #endif printf("Waiting for wps button release..."); reset_release_wait(); printf("done\n"); } } /* Reboot after restoring defaults */ if (restore_defaults) si_watchdog(sih, 1); #endif /* !CFG_SIM */ #else if (commit) printf("Flash not configured, not commiting NVRAM...\n"); #endif /* CFG_FLASH || CFG_SFLASH || CFG_NFLASH */ /* * Read the wait_time NVRAM variable and set the tftp max retries. * Assumption: tftp_rrq_timeout & tftp_recv_timeout are set to 1sec. */ if ((wait_time = nvram_get("wait_time")) != NULL) { tftp_max_retries = atoi(wait_time); if (tftp_max_retries > MAX_WAIT_TIME) tftp_max_retries = MAX_WAIT_TIME; else if (tftp_max_retries < MIN_WAIT_TIME) tftp_max_retries = MIN_WAIT_TIME; } #ifdef CFG_ROMBOOT else if (board_bootdev_rom(sih)) { tftp_max_retries = 10; } #endif /* Configure network */ if (cfe_finddev("eth0")) { int res; if ((addr = nvram_get("lan_ipaddr")) && (mask = nvram_get("lan_netmask"))) sprintf(buf, "ifconfig eth0 -addr=%s -mask=%s", addr, mask); else sprintf(buf, "ifconfig eth0 -auto"); res = ui_docommand(buf); #ifdef CFG_ROMBOOT /* Try indefinite netboot only while booting from ROM * and we are sure that we dont have valid nvram in FLASH */ while (board_bootdev_rom(sih) && !addr) { char ch; cur = buf; /* Check if something typed at console */ if (console_status()) { console_read(&ch, 1); /* Check for Ctrl-C */ if (ch == 3) { if (laddr) MFREE(osh, laddr, MAX_SCRIPT_FSIZE); xprintf("Stopped auto netboot!!!\n"); return; } } if (!res) { char *bserver, *bfile, *load_ptr; if (!laddr) laddr = MALLOC(osh, MAX_SCRIPT_FSIZE); if (!laddr) { load_ptr = (char *) 0x00008000; xprintf("Failed malloc for boot_script, Using :0x%x\n", (unsigned int)laddr); } else { load_ptr = laddr; } bserver = (bserver = env_getenv("BOOT_SERVER")) ? bserver:"192.168.1.1"; if ((bfile = env_getenv("BOOT_FILE"))) { int len; if (((len = strlen(bfile)) > 5) && !strncmp((bfile + len - 5), "cfesh", 5)) { cur += sprintf(cur, "batch -raw -tftp -addr=0x%x -max=0x%x %s:%s;", (unsigned int)load_ptr, MAX_SCRIPT_FSIZE, bserver, bfile); } if (((len = strlen(bfile)) > 3)) { if (!strncmp((bfile + len - 3), "elf", 3)) { cur += sprintf(cur, "boot -elf -tftp -max=0x5000000 %s:%s;", bserver, bfile); } if (!strncmp((bfile + len - 3), "raw", 3)) { cur += sprintf(cur, "boot -raw -z -tftp -addr=0x00008000" " -max=0x5000000 %s:%s;", bserver, bfile); } } } else { /* Make last effort */ cur += sprintf(cur, "batch -raw -tftp -addr=0x%x -max=0x%x %s:%s;", (unsigned int)load_ptr, MAX_SCRIPT_FSIZE, bserver, "cfe_script.cfesh"); cur += sprintf(cur, "boot -elf -tftp -max=0x5000000 %s:%s;", bserver, "boot_file.elf"); cur += sprintf(cur, "boot -raw -z -tftp -addr=0x00008000" " -max=0x5000000 %s:%s;", bserver, "boot_file.raw"); } ui_docommand(buf); cfe_sleep(3*CFE_HZ); } sprintf(buf, "ifconfig eth0 -auto"); res = ui_docommand(buf); } #endif /* CFG_ROMBOOT */ } #if CFG_WL && CFG_WLU && CFG_SIM if ((ssid = nvram_get("wl0_ssid"))) { sprintf(buf, "wl join %s", ssid); ui_docommand(buf); } #endif #if !CFG_SIM /* Try to run boot_config command if configured. * make sure to leave space for "go" command. */ if ((boot_cfg = nvram_get("boot_config"))) { if (strlen(boot_cfg) < (sizeof(buf) - sizeof(go_cmd))) cur += sprintf(cur, "%s;", boot_cfg); else printf("boot_config too long, skipping to autoboot\n"); } /* Boot image */ cur += sprintf(cur, go_cmd); #endif /* !CFG_SIM */ /* Startup */ if (cur > buf) env_setenv("STARTUP", buf, ENV_FLG_NORMAL); }
/** Disable JTAG/SWD I/O Pins. Disables the DAP Hardware I/O pins which configures: - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. */ void PORT_OFF() { GPIO_INIT(PIN_SWCLK_TCK_PORT, INIT_OFF_1); GPIO_INIT(PIN_nRESET_PORT, INIT_OFF_2); }
void PORT_USB_CONNECT_SETUP(void) { RCC->APB2ENR |= PIN_USB_CONNECT_RCC; PIN_USB_CONNECT_OFF(); GPIO_INIT(PIN_USB_CONNECT_PORT, INIT_PIN_USB_CONNECT); }
void LEDS_SETUP (void) { RCC->APB2ENR |= LED_CONNECTED_RCC; LED_CONNECTED_PORT->BRR = (LED_CONNECTED_PIN | LED_RUNNING_PIN); GPIO_INIT(LED_CONNECTED_PORT, INIT_PINS_LED); }
int main(void) { int i, done = 0; int s; // MCG_FLL_RTC_OSC(); // Enable UART Pins SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK; PORTC_PCR16 = PORT_PCR_MUX(0x03); //Rx PORTC_PCR17 = PORT_PCR_MUX(0x03); //Tx // Initialize UART uart_init(); // MCG_BLPE(); CLOCK_100MHZ(); GPIO_INIT(); ADC1_INIT(); DAC1_INIT(); // lptmr_init(); PDB_INIT(); FTM_INIT(); // Start the PDB (ADC Conversions) PDB0_SC |= PDB_SC_SWTRIG_MASK; for(;;) { int stage; // Print out a binary and decimal representation of the resultant ADC conversion. // printf("\nBinary ADC conversion result: %b,\tDecimal ADC conversion result: %d\n\r", ADC1_RA, ADC1_RA); // // // Delay for UART print. // for( i = 0; i < 1000000; ++i ){ // // } if( adcConvComplete && (done == 0) ) { adcConvComplete = 0; if(sampleCounter == 0) { deltaStep = 1.0; } else { deltaStep = 0.0; } // lp1Out = lp1Cheby((float)ADC1_RA, &xvlp1[0], &yvlp1[0]); // usStart = microsecTicks; // Run first lowpass filter lp1Out = lp1Cheby(deltaStep, &xvlp1[0], &yvlp1[0]); // usTotal = microsecTicks - usStart; // printf("%i\n\r", usTotal); // for(s=0; s<10000; s++); // Cascade the filters if desired // for(stage=1; stage < LP1_CASCADE; stage++) // { // lp1OutRecurs = lp1Out; // lp1Out = lp1Cheby(lp1OutRecurs, &xvlp1[stage], &yvlp1[stage]); // } printf("%.6i\n\r", lp1Out); // Execute filter for finite number of samples if(sampleCounter > (SAMPLES_TO_RUN - 1)) { // Halt ADC sampling PDB_STOP(); done = 1; printf("Samples Completed: %d.\n\r", sampleCounter); GPIOA_PDOR &= GPIO_PIN(LED_GREEN); } sampleCounter++; } } return 0; }
#define GPIO_NAME_SYS "sys" #define GPIO_NAME_RESET "reset" #define GPIO_R 0x01 #define GPIO_W 0x02 #define GPIO_RW (GPIO_R | GPIO_W) struct gpio { char name[1+GPIO_NAME_LEN]; int number; int flag; }; #define GPIO_INIT(_name, _number, _flag) {.name=_name, .number=_number, .flag=_flag} static struct gpio GPIO[] = { GPIO_INIT(GPIO_NAME_SATA, GPIO_NUMBER_SATA, GPIO_W), GPIO_INIT(GPIO_NAME_SYS, GPIO_NUMBER_SYS, GPIO_W), GPIO_INIT(GPIO_NAME_RESET, GPIO_NUMBER_RESET, GPIO_RW), }; #define ASIZE(x) (sizeof(x)/sizeof((x)[0])) #define COUNT ASIZE(GPIO) #define println(fmt, args...) printf(fmt "\n", ##args) #define dprintln println static inline struct gpio * getgpio_byname(char *name) { int i;