dci_dev DCI device descriptor
dci_unit DCI unit descriptor
dci_reg DCI register list
*/
DIB dci_dib = {
IOBA_DC, IOLN_DC, &dcx_rd, &dcx_wr,
2, IVCL(DCI), VEC_DCI, {&dci_iack, &dco_iack}
};
UNIT dci_unit = { UDATA(&dci_svc, 0, 0), KBD_POLL_WAIT };
REG dci_reg[] = {
{BRDATA(BUF, dci_buf, DEV_RDX, 8, DCX_LINES)},
{BRDATA(CSR, dci_csr, DEV_RDX, 16, DCX_LINES)},
{GRDATA(IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0)},
{DRDATA(LINES, dcx_desc.lines, 6), REG_HRO},
{GRDATA(DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO},
{GRDATA(DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO},
{GRDATA(DEVVEC, dci_dib.vec, DEV_RDX, 16, 0), REG_HRO},
{NULL}
};
MTAB dci_mod[] = {
{MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dcx_desc},
{UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *)&dcx_desc},
{MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *)&dcx_desc},
{MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
{ BRDATA (ER1, rper1, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (HR, rmhr, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (OF, rpof, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (DC, rpdc, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (ER2, rper2, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (ER3, rper3, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (EC1, rpec1, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (EC2, rpec2, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (MR, rpmr, DEV_RDX, 16, RP_NUMDR) },
{ BRDATA (MR2, rmmr2, DEV_RDX, 16, RP_NUMDR) },
{ DRDATA (STIME, rp_swait, 24), REG_NZ + PV_LEFT },
{ DRDATA (RTIME, rp_rwait, 24), REG_NZ + PV_LEFT },
{ URDATA (CAPAC, rp_unit[0].capac, 10, T_ADDR_W, 0,
RP_NUMDR, PV_LEFT | REG_HRO) },
{ FLDATA (STOP_IOE, rp_stopioe, 0) },
{ GRDATA (CTRLTYPE, rp_dib.lnt, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB rp_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "MASSBUS", "MASSBUS", NULL, &mba_show_num },
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },
{ UNIT_DUMMY, 0, NULL, "BADBLOCK", &rp_set_bad },
{ (UNIT_DTYPE+UNIT_ATT), (RM03_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RM03", NULL, NULL },
{ (UNIT_DTYPE+UNIT_ATT), (RP04_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RP04", NULL, NULL },
{ (UNIT_DTYPE+UNIT_ATT), (RM80_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
"RM80", NULL, NULL },
{ (UNIT_DTYPE+UNIT_ATT), (RP06_DTYPE << UNIT_V_DTYPE) + UNIT_ATT,
{ UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
UNIT_ROABLE+(TYPE_5440 << UNIT_V_DTYPE), SIZE_5440) }
};
REG dp_reg[] = {
{ HRDATA (CMD, dp_cmd, 3) },
{ HRDATA (STA, dp_sta, 8) },
{ HRDATA (BUF, dp_db, 8) },
{ HRDATA (PLAT, dp_plat, 1) },
{ HRDATA (HDSC, dp_hdsc, 6) },
{ HRDATA (CYL, dp_cyl, 9) },
{ HRDATA (SVUN, dp_svun, 8), REG_HIDDEN },
{ BRDATA (DBUF, dpxb, 16, 8, DP_NUMBY) },
{ HRDATA (DBPTR, dp_bptr, 9), REG_RO },
{ FLDATA (FIRST, dp_1st, 0) },
{ GRDATA (IREQ, int_req[l_DPC], 16, DP_NUMDR + 1, i_DPC) },
{ GRDATA (IENB, int_enb[l_DPC], 16, DP_NUMDR + 1, i_DPC) },
{ BRDATA (IARM, dpd_arm, 16, 1, DP_NUMDR) },
{ DRDATA (RTIME, dp_rtime, 0), PV_LEFT | REG_NZ },
{ DRDATA (STIME, dp_stime, 0), PV_LEFT | REG_NZ },
{ DRDATA (WTIME, dp_wtime, 0), PV_LEFT | REG_NZ },
{ URDATA (UCYL, dp_unit[0].CYL, 16, 9, 0,
DP_NUMDR, REG_RO) },
{ URDATA (UST, dp_unit[0].STD, 16, 8, 0,
DP_NUMDR, REG_RO) },
{ URDATA (CAPAC, dp_unit[0].capac, 10, T_ADDR_W, 0,
DP_NUMDR, PV_LEFT | REG_HRO) },
{ HRDATA (DEVNO, dp_dib.dno, 8), REG_HRO },
{ HRDATA (SELCH, dp_dib.sch, 2), REG_HRO },
{ NULL }
};
ts_unit TS unit list
ts_reg TS register list
ts_mod TS modifier list
*/
#define IOLN_TS 004
DIB ts_dib = {
IOBA_AUTO, IOLN_TS, &ts_rd, &ts_wr,
1, IVCL (TS), VEC_AUTO, { NULL }
};
UNIT ts_unit = { UDATA (&ts_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) };
REG ts_reg[] = {
{ GRDATA (TSSR, tssr, DEV_RDX, 16, 0) },
{ GRDATA (TSBA, tsba, DEV_RDX, 22, 0) },
{ GRDATA (TSDBX, tsdbx, DEV_RDX, 8, 0) },
{ GRDATA (CHDR, cmdhdr, DEV_RDX, 16, 0) },
{ GRDATA (CADL, cmdadl, DEV_RDX, 16, 0) },
{ GRDATA (CADH, cmdadh, DEV_RDX, 16, 0) },
{ GRDATA (CLNT, cmdlnt, DEV_RDX, 16, 0) },
{ GRDATA (MHDR, msghdr, DEV_RDX, 16, 0) },
{ GRDATA (MRFC, msgrfc, DEV_RDX, 16, 0) },
{ GRDATA (MXS0, msgxs0, DEV_RDX, 16, 0) },
{ GRDATA (MXS1, msgxs1, DEV_RDX, 16, 0) },
{ GRDATA (MXS2, msgxs2, DEV_RDX, 16, 0) },
{ GRDATA (MXS3, msgxs3, DEV_RDX, 16, 0) },
{ GRDATA (MSX4, msgxs4, DEV_RDX, 16, 0) },
{ GRDATA (WADL, wchadl, DEV_RDX, 16, 0) },
{ GRDATA (WADH, wchadh, DEV_RDX, 16, 0) },
ptr_unit PTR unit descriptor
ptr_reg PTR register list
*/
DIB ptr_dib = {
IOBA_PTR, IOLN_PTR, &ptr_rd, &ptr_wr,
1, IVCL (PTR), VEC_PTR, { NULL }
};
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT
};
REG ptr_reg[] = {
{ GRDATA (BUF, ptr_unit.buf, DEV_RDX, 8, 0) },
{ GRDATA (CSR, ptr_csr, DEV_RDX, 16, 0) },
{ FLDATA (INT, int_req, INT_V_PTR) },
{ FLDATA (ERR, ptr_csr, CSR_V_ERR) },
{ FLDATA (BUSY, ptr_csr, CSR_V_BUSY) },
{ FLDATA (DONE, ptr_csr, CSR_V_DONE) },
{ FLDATA (IE, ptr_csr, CSR_V_IE) },
{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ FLDATA (DEVDIS, ptr_dev.flags, DEV_V_DIS), REG_HRO },
{ NULL }
};
MTAB ptr_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
*/
DIB ry_dib = {
IOBA_RY, IOLN_RY, &ry_rd, &ry_wr,
1, IVCL (RY), VEC_RY, { NULL }
};
UNIT ry_unit[] = {
{ UDATA (&ry_svc, UNIT_DEN+UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
RY_SIZE) },
{ UDATA (&ry_svc, UNIT_DEN+UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF,
RY_SIZE) }
};
REG ry_reg[] = {
{ GRDATA (RYCS, ry_csr, DEV_RDX, 16, 0) },
{ GRDATA (RYBA, ry_ba, DEV_RDX, 16, 0) },
{ GRDATA (RYWC, ry_wc, DEV_RDX, 8, 0) },
{ GRDATA (RYDB, ry_dbr, DEV_RDX, 16, 0) },
{ GRDATA (RYES, ry_esr, DEV_RDX, 12, 0) },
{ GRDATA (RYERR, ry_ecode, DEV_RDX, 8, 0) },
{ GRDATA (RYTA, ry_track, DEV_RDX, 8, 0) },
{ GRDATA (RYSA, ry_sector, DEV_RDX, 8, 0) },
{ DRDATA (STAPTR, ry_state, 4), REG_RO },
{ FLDATA (INT, IREQ (RY), INT_V_RY) },
{ FLDATA (ERR, ry_csr, RYCS_V_ERR) },
{ FLDATA (TR, ry_csr, RYCS_V_TR) },
{ FLDATA (IE, ry_csr, RYCS_V_IE) },
{ FLDATA (DONE, ry_csr, RYCS_V_DONE) },
{ DRDATA (CTIME, ry_cwait, 24), PV_LEFT },
{ DRDATA (STIME, ry_swait, 24), PV_LEFT },
DIB dz_dib = {
IOBA_DZ, IOLN_DZ * DZ_MUXES, &dz_rd, &dz_wr,
2, IVCL(DZRX), VEC_DZRX, {&dz_rxinta, &dz_txinta}
};
UNIT dz_unit = { UDATA(&dz_svc, UNIT_IDLE | UNIT_ATTABLE | DZ_8B_DFLT, 0) };
REG dz_reg[] = {
{BRDATA(CSR, dz_csr, DEV_RDX, 16, DZ_MUXES)},
{BRDATA(RBUF, dz_rbuf, DEV_RDX, 16, DZ_MUXES)},
{BRDATA(LPR, dz_lpr, DEV_RDX, 16, DZ_MUXES)},
{BRDATA(TCR, dz_tcr, DEV_RDX, 16, DZ_MUXES)},
{BRDATA(MSR, dz_msr, DEV_RDX, 16, DZ_MUXES)},
{BRDATA(TDR, dz_tdr, DEV_RDX, 16, DZ_MUXES)},
{BRDATA(SAENB, dz_sae, DEV_RDX, 1, DZ_MUXES)},
{GRDATA(RXINT, dz_rxi, DEV_RDX, DZ_MUXES, 0)},
{GRDATA(TXINT, dz_txi, DEV_RDX, DZ_MUXES, 0)},
{FLDATA(MDMCTL, dz_mctl, 0)},
{FLDATA(AUTODS, dz_auto, 0)},
{GRDATA(DEVADDR, dz_dib.ba, DEV_RDX, 32, 0), REG_HRO},
{GRDATA(DEVVEC, dz_dib.vec, DEV_RDX, 16, 0), REG_HRO},
{NULL}
};
MTAB dz_mod[] = {
{TT_MODE, TT_MODE_7B, "7b", "7B", NULL},
{TT_MODE, TT_MODE_8B, "8b", "8B", NULL},
{TT_MODE, TT_MODE_7P, "7p", "7P", NULL},
{MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dz_desc},
{UNIT_ATT, UNIT_ATT, "summary", NULL,
{ GRDATAD (MXS2, msgxs2, DEV_RDX, 16, 0, "message packet extended status 2") },
{ GRDATAD (MXS3, msgxs3, DEV_RDX, 16, 0, "message packet extended status 3") },
{ GRDATAD (MSX4, msgxs4, DEV_RDX, 16, 0, "message packet extended status 4") },
{ GRDATAD (WADL, wchadl, DEV_RDX, 16, 0, "write char packet low address") },
{ GRDATAD (WADH, wchadh, DEV_RDX, 16, 0, "write char packet high address") },
{ GRDATAD (WLNT, wchlnt, DEV_RDX, 16, 0, "write char packet length") },
{ GRDATAD (WOPT, wchopt, DEV_RDX, 16, 0, "write char packet options") },
{ GRDATAD (WXOPT, wchxopt, DEV_RDX, 16, 0, "write char packet extended options") },
{ FLDATAD (INT, IREQ (TS), INT_V_TS, "interrupt pending") },
{ FLDATAD (ATTN, ts_qatn, 0, "attention message pending") },
{ FLDATAD (BOOT, ts_bcmd, 0, "boot request pending") },
{ FLDATAD (OWNC, ts_ownc, 0, "if set, tape owns command buffer") },
{ FLDATAD (OWNM, ts_ownm, 0, "if set, tape owns message buffer") },
{ DRDATAD (TIME, ts_time, 24, "delay"), PV_LEFT + REG_NZ },
{ DRDATAD (POS, ts_unit.pos, T_ADDR_W, "position"), PV_LEFT + REG_RO },
{ GRDATA (DEVADDR, ts_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, ts_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB ts_mod[] = {
{ MTUF_WLK, 0, "write enabled", "WRITEENABLED",
NULL, NULL, NULL, "Write enable tape drive" },
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED",
NULL, NULL, NULL, "Write lock tape drive" },
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "FORMAT", "FORMAT",
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL, "Set/Display tape format (SIMH, E11, TPC, P7B)" },
{ MTAB_XTD|MTAB_VUN|MTAB_VALR, 0, "CAPACITY", "CAPACITY",
&sim_tape_set_capac, &sim_tape_show_capac, NULL, "Set/Display capacity" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 004, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL, "Bus address" },
dli_dev DLI device descriptor
dli_unit DLI unit descriptor
dli_reg DLI register list
*/
DIB dli_dib = {
IOBA_DL, IOLN_DL, &dlx_rd, &dlx_wr,
2, IVCL (DLI), VEC_DLI, { &dli_iack, &dlo_iack }
};
UNIT dli_unit = { UDATA (&dli_svc, 0, 0), KBD_POLL_WAIT };
REG dli_reg[] = {
{ BRDATA (BUF, dli_buf, DEV_RDX, 16, DLX_LINES) },
{ BRDATA (CSR, dli_csr, DEV_RDX, 16, DLX_LINES) },
{ GRDATA (IREQ, dli_ireq[DLI_RCI], DEV_RDX, DLX_LINES, 0) },
{ GRDATA (DSI, dli_ireq[DLI_DSI], DEV_RDX, DLX_LINES, 0) },
{ DRDATA (LINES, dlx_desc.lines, 6), REG_HRO },
{ GRDATA (DEVADDR, dli_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVIOLN, dli_dib.lnt, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, dli_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB dli_mod[] = {
{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dlx_desc },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &dlx_desc },
{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &dlx_desc },
UNIT mt_unit[] = {
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
{ UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) }
};
REG mt_reg[] = {
{ HRDATA (STA, mt_sta, 8) },
{ HRDATA (BUF, mt_db, 8) },
{ BRDATA (DBUF, mtxb, 16, 8, MT_MAXFR) },
{ HRDATA (DBPTR, mt_bptr, 16) },
{ HRDATA (DBLNT, mt_blnt, 17), REG_RO },
{ FLDATA (XFR, mt_xfr, 0) },
{ GRDATA (IREQ, int_req[l_MT], 16, MT_NUMDR, i_MT) },
{ GRDATA (IENB, int_enb[l_MT], 16, MT_NUMDR, i_MT) },
{ BRDATA (IARM, mt_arm, 16, 1, MT_NUMDR) },
{ FLDATA (STOP_IOE, mt_stopioe, 0) },
{ DRDATA (WTIME, mt_wtime, 24), PV_LEFT + REG_NZ },
{ DRDATA (RTIME, mt_rtime, 24), PV_LEFT + REG_NZ },
{ URDATA (UST, mt_unit[0].UST, 16, 8, 0, MT_NUMDR, 0) },
{ URDATA (CMD, mt_unit[0].UCMD, 16, 8, 0, MT_NUMDR, 0) },
{ URDATA (POS, mt_unit[0].pos, 10, T_ADDR_W, 0,
MT_NUMDR, PV_LEFT | REG_RO) },
{ HRDATA (DEVNO, mt_dib.dno, 8), REG_HRO },
{ HRDATA (SELCH, mt_dib.sch, 1), REG_HRO },
{ NULL }
};
MTAB mt_mod[] = {
lpt_dev LPT device descriptor
lpt_unit LPT unit descriptor
lpt_reg LPT register list
*/
DIB lpt_dib = {
IOBA_LPT, IOLN_LPT, &lpt_rd, &lpt_wr,
1, IVCL(LPT), VEC_LPT, {NULL}
};
UNIT lpt_unit = {
UDATA(&lpt_svc, UNIT_SEQ + UNIT_ATTABLE + UNIT_TEXT, 0), SERIAL_OUT_WAIT
};
REG lpt_reg[] = {
{GRDATA(BUF, lpt_unit.buf, DEV_RDX, 8, 0)},
{GRDATA(CSR, lpt_csr, DEV_RDX, 16, 0)},
{FLDATA(INT, IREQ(LPT), INT_V_LPT)},
{FLDATA(ERR, lpt_csr, CSR_V_ERR)},
{FLDATA(DONE, lpt_csr, CSR_V_DONE)},
{FLDATA(IE, lpt_csr, CSR_V_IE)},
{DRDATA(POS, lpt_unit.pos, T_ADDR_W), PV_LEFT},
{DRDATA(TIME, lpt_unit.wait, 24), PV_LEFT},
{FLDATA(STOP_IOE, lpt_stopioe, 0)},
{GRDATA(DEVADDR, lpt_dib.ba, DEV_RDX, 32, 0), REG_HRO},
{GRDATA(DEVVEC, lpt_dib.vec, DEV_RDX, 16, 0), REG_HRO},
{NULL}
};
MTAB lpt_mod[] = {
{MTAB_XTD | MTAB_VDV, 004, "ADDRESS", "ADDRESS",
#define IOLN_DC 010
DIB dci_dib = {
IOBA_AUTO, IOLN_DC * DCX_LINES, &dcx_rd, &dcx_wr,
2, IVCL (DCI), VEC_AUTO, { &dci_iack, &dco_iack }, IOLN_DC,
};
UNIT dci_unit = { UDATA (&dci_svc, 0, 0), TMLN_SPD_9600_BPS };
REG dci_reg[] = {
{ BRDATAD (BUF, dci_buf, DEV_RDX, 8, DCX_LINES, "input control/stats register") },
{ BRDATAD (CSR, dci_csr, DEV_RDX, 16, DCX_LINES, "input buffer") },
{ GRDATAD (IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0, "interrupt requests") },
{ DRDATAD (TIME, dci_unit.wait, 24, "input polling interval"), PV_LEFT },
{ DRDATA (LINES, dcx_desc.lines, 6), REG_HRO },
{ GRDATA (DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO },
{ GRDATA (DEVVEC, dci_dib.vec, DEV_RDX, 16, 0), REG_HRO },
{ NULL }
};
MTAB dci_mod[] = {
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 1, NULL, "DISCONNECT",
&tmxr_dscln, NULL, &dcx_desc, "Disconnect a specific line" },
{ UNIT_ATT, UNIT_ATT, "summary", NULL,
NULL, &tmxr_show_summ, (void *) &dcx_desc, "Display a summary of line states" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "CONNECTIONS", NULL,
NULL, &tmxr_show_cstat, (void *) &dcx_desc, "Display current connections" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "STATISTICS", NULL,
NULL, &tmxr_show_cstat, (void *) &dcx_desc, "Display multiplexer statistics" },
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 010, "ADDRESS", "ADDRESS",
static I8255 u39 = {
{ 0,0,U39_ADDR,8,2},
&sagelp_dev,
i8255_write,i8255_read,u39_reset,u39_calla,u39_callb,u39_callc,u39_ckmode
};
UNIT sagelp_unit = {
UDATA (NULL, UNIT_SEQ|UNIT_ATTABLE|UNIT_TEXT, 0), SERIAL_OUT_WAIT
};
REG sagelp_reg[] = {
{ HRDATA(PORTA, u39.porta, 8) },
{ HRDATA(PORTB, u39.portb, 8) },
{ HRDATA(PORTC, u39.portc, 8) },
{ HRDATA(CTRL, u39.ctrl, 8) },
{ GRDATA (BUF, sagelp_unit.buf, 16, 8, 0) },
{ DRDATA (POS, sagelp_unit.pos, T_ADDR_W), PV_LEFT },
{ NULL }
};
static MTAB sagelp_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "IO", "IO", &set_iobase, &show_iobase, NULL },
{ UNIT_OFFLINE, UNIT_OFFLINE, "offline", "OFFLINE", NULL },
{ UNIT_OFFLINE, 0, "online", "ONLINE", NULL },
{ 0 }
};
DEBTAB sagelp_dt[] = {
{ "WRA", DBG_PP_WRA },
{ "RDB", DBG_PP_RDB },
{ "RDC", DBG_PP_RDC },
