PUBLIC void GSP_Wait_Finish(void)
{
while(1)
{
if(GSP_WORKSTATUS_GET() == 0)
{
break;
}
}
}
/*
func:GSP_ClocksCheckPhase0
desc: check all clock except iommu
*/
PUBLIC int GSP_ClocksCheckPhase0(void)
{
int ret = 0;
//check GSP enable
if(0==(GSP_REG_READ(GSP_MOD_EN)&GSP_MOD_EN_BIT)) {
printk(KERN_ERR "%s: err: gsp enable is not set!%lx:%08x\n",__FUNCTION__,
(ulong)GSP_MOD_EN,GSP_REG_READ(GSP_MOD_EN));
ret++;
} else {
if(GSP_WORKSTATUS_GET() != 0) {
printk(KERN_ERR "%s: err:busy is still on!!!!\n",__FUNCTION__);
ret++;
}
}
//check GSP clock select
if(GSP_CLK_SEL_BIT_MASK!=(GSP_REG_READ(GSP_CLOCK_BASE)&GSP_CLK_SEL_BIT_MASK)) {
printk(KERN_INFO "%s: info: gsp clock select is not set to hightest freq!%lx:%08x\n",__FUNCTION__,
(ulong)GSP_CLOCK_BASE,GSP_REG_READ(GSP_CLOCK_BASE));
}
//check GSP AUTO_GATE clock
if(0==(GSP_REG_READ(GSP_AUTO_GATE_ENABLE_BASE)&GSP_AUTO_GATE_ENABLE_BIT)) {
printk(KERN_ERR "%s: err: gsp auto gate clock is not enable!%lx:%08x\n",__FUNCTION__,
(ulong)GSP_AUTO_GATE_ENABLE_BASE,GSP_REG_READ(GSP_AUTO_GATE_ENABLE_BASE));
ret++;
}
//check GSP EMC clock
if(0==(GSP_REG_READ(GSP_EMC_MATRIX_BASE)&GSP_EMC_MATRIX_BIT)) {
printk(KERN_ERR "%s: err: gsp emc clock is not enable!%lx:%08x\n",__FUNCTION__,
(ulong)GSP_EMC_MATRIX_BASE,GSP_REG_READ(GSP_EMC_MATRIX_BASE));
ret++;
}
return (ret>0)?GSP_KERNEL_CLOCK_ERR:GSP_NO_ERR;
}
PUBLIC void GSP_Wait_Finish(void)
{
if(GSP_WORKSTATUS_GET() != 0) {
printk(KERN_ERR "%s: err:busy is still on!!!!\n",__FUNCTION__);
}
}
